Commit Graph

873647 Commits

Author SHA1 Message Date
Saeed Mahameed 75af77c4bd page_pool: Add API to update numa node
Add page_pool_update_nid() to be called by page pool consumers when they
detect numa node changes.

It will update the page pool nid value to start allocating from the new
effective numa node.

This is to mitigate page pool allocating pages from a wrong numa node,
where the pool was originally allocated, and holding on to pages that
belong to a different numa node, which causes performance degradation.

For pages that are already being consumed and could be returned to the
pool by the consumer, in next patch we will add a check per page to avoid
recycling them back to the pool and return them to the page allocator.

Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
Acked-by: Jonathan Lemon <jonathan.lemon@gmail.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Acked-by: Jesper Dangaard Brouer <brouer@redhat.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: hongrongxuan <hongrongxuan@huawei.com>
2024-06-12 13:16:51 +08:00
Xiongfeng Wang 3370a82d1d asm-generic: introduce io_stop_wc() and add implementation for ARM64
For memory accesses with write-combining attributes (e.g. those returned
by ioremap_wc()), the CPU may wait for prior accesses to be merged with
subsequent ones. But in some situation, such wait is bad for the
performance.

We introduce io_stop_wc() to prevent the merging of write-combining
memory accesses before this macro with those after it.

We add implementation for ARM64 using DGH instruction and provide NOP
implementation for other architectures.

Signed-off-by: Xiongfeng Wang <wangxiongfeng2@huawei.com>
Suggested-by: Will Deacon <will@kernel.org>
Suggested-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20211221035556.60346-1-wangxiongfeng2@huawei.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: hongrongxuan <hongrongxuan@huawei.com>

 Conflicts:
	arch/arm64/include/asm/barrier.h
	include/asm-generic/barrier.h
2024-06-12 13:16:50 +08:00
hongrongxuan f1759b64e4 arm64: Add HWCAP for Data Gathering Hint instruction 2024-06-12 13:16:50 +08:00
Hao Lan 1cfcd56e3e net: sfp: Synchronize some CMIS transceiver modules from ethtool
driver inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I9A3QT
CVE: NA

----------------------------------------------------------------------

Currently, the SFF-8024 Identifier Values that according to the standard
support for the Common Management Interface Specification (CMIS)
based on standard identifier values in the ethtool is more than in the
kernel. When the driver needs to use a newer Identifier Value, the kernel
interface does not support it. Therefore, we synchronize the CMIS mode
Identifier Values which supported by the ethtool to the kernel.

Signed-off-by: Hao Lan <lanhao@huawei.com>
Signed-off-by: Jiantao Xiao <xiaojiantao1@h-partners.com>
Signed-off-by: hongrongxuan <hongrongxuan@huawei.com>
2024-06-12 13:16:49 +08:00
刘诗 e8f63ff212 drm: support virtualbox display
insmod oc iso by virtualbox, need adjust accuracy.

Signed-off-by: aurelianliu <aurelianliu@tencent.com>
2024-06-12 13:16:49 +08:00
Carrie.Cai 403acd3e81 add support for Montage Mont-TSSE driver
Signed-off-by: Carrie.Cai <carrie.cai@montage-tech.com>
2024-06-12 13:16:49 +08:00
Xiang Chen 6e7d318920 scsi: hisi_sas: Remove hisi_hba->timer for v3 hw
hisi_hba->timer is not used for v3 hw but there are two places that some
operations related to hisi_hba->timer are called by v3 hw:

 - Deleting the timer in function hisi_sas_v3_hw() which is only for v3 hw;

 - Deleting the timer in function hisi_sas_controller_reset_prepare() which
   is common for v1/v2/v3 hw.

We can remove the timer in the first case, but for the second scenario we
need to remove it only for v3 hw, so check hw->sht which is NULL only for
v3 hw before deleting hisi_hba->timer.

Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
Link: https://lore.kernel.org/r/1705904747-62186-5-git-send-email-chenxiang66@hisilicon.com
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
Signed-off-by: Slim6882 <yangjunshuo@huawei.com>
2024-06-12 13:16:48 +08:00
Huang Cun da001515c1 ipmi_si: resolve ipmi_si compilation error when ACPI is not enabled
during the CI check, when using make allyesconfig, there is a compilation
error with ipmi_si.

Signed-off-by: Huang Cun <cunhuang@tencent.com>
2024-06-12 13:16:48 +08:00
Huang Cun 33d6865086 mpt3sas: eliminate the kconfig warning
Signed-off-by: Huang Cun <cunhuang@tencent.com>
2024-06-12 13:16:48 +08:00
Huang Cun 421f160199 ock: ci: remove NET_QOS Kconfig
The CI check will execute make allyesconfig, and the opencloud kernel
code controlled by this macros has been deprecated, so remove it.

Signed-off-by: Huang Cun <cunhuang@tencent.com>
2024-06-12 13:16:47 +08:00
Huang Cun bec7f2888b config: remove CONFIG_BT_SHARE_CFS_BANDWIDTH and CONFIG_HT_ISOLATE
The CI check will execute make dist-check-diff-config, and the code
controlled by these two macros has been deprecated, so remove it.

Signed-off-by: Huang Cun <cunhuang@tencent.com>
2024-06-12 13:16:47 +08:00
Hao Chen 6b0cffb484 net: vxlan: add macro definition for number of IANA VXLAN-GPE port
Add macro definition for number of IANA VXLAN-GPE port for generic use.

Signed-off-by: Hao Chen <chenhao288@hisilicon.com>
Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: hongrongxuan <hongrongxuan@huawei.com>
2024-06-12 13:16:46 +08:00
Randy Dunlap 75bf92c7c0 DIM: fix dim.h kernel-doc and headers
Lots of fixes to kernel-doc in structs, enums, and functions.
Also add header files that are being used but not yet #included.

Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
Cc: Yamin Friedman <yaminf@mellanox.com>
Cc: Tal Gilboa <talgi@mellanox.com>
Cc: Saeed Mahameed <saeedm@mellanox.com>
Cc: Doug Ledford <dledford@redhat.com>
Cc: Jason Gunthorpe <jgg@mellanox.com>
Cc: linux-rdma@vger.kernel.org
Cc: netdev@vger.kernel.org
Signed-off-by: Jakub Kicinski <jakub.kicinski@netronome.com>
Signed-off-by: hongrongxuan <hongrongxuan@huawei.com>
2024-06-12 13:16:46 +08:00
Alexander Lobakin 078962c273 mm: constify page_is_pfmemalloc() argument
The function only tests for page->index, so its argument should be
const.

Signed-off-by: Alexander Lobakin <alobakin@pm.me>
Reviewed-by: Jesse Brandeburg <jesse.brandeburg@intel.com>
Acked-by: David Rientjes <rientjes@google.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Signed-off-by: hongrongxuan <hongrongxuan@huawei.com>
2024-06-12 13:16:46 +08:00
Alexander Lobakin 44552e86fc net: introduce common dev_page_is_reusable()
A bunch of drivers test the page before reusing/recycling for two
common conditions:
 - if a page was allocated under memory pressure (pfmemalloc page);
 - if a page was allocated at a distant memory node (to exclude
   slowdowns).

Introduce a new common inline for doing this, with likely() already
folded inside to make driver code a bit simpler.

Suggested-by: David Rientjes <rientjes@google.com>
Suggested-by: Jakub Kicinski <kuba@kernel.org>
Cc: John Hubbard <jhubbard@nvidia.com>
Signed-off-by: Alexander Lobakin <alobakin@pm.me>
Reviewed-by: Jesse Brandeburg <jesse.brandeburg@intel.com>
Acked-by: David Rientjes <rientjes@google.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Signed-off-by: hongrongxuan <hongrongxuan@huawei.com>
2024-06-12 13:16:45 +08:00
Xin Long 599e4e0f53 net: add inline function skb_csum_is_sctp
This patch is to define a inline function skb_csum_is_sctp(), and
also replace all places where it checks if it's a SCTP CSUM skb.
This function would be used later in many networking drivers in
the following patches.

Suggested-by: Alexander Duyck <alexander.duyck@gmail.com>
Signed-off-by: Xin Long <lucien.xin@gmail.com>
Reviewed-by: Alexander Duyck <alexanderduyck@fb.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Signed-off-by: hongrongxuan <hongrongxuan@huawei.com>
2024-06-12 13:16:45 +08:00
Russell King fd23055d7f net: sfp: add more extended compliance codes
SFF-8024 is used to define various constants re-used in several SFF
SFP-related specifications.  Split these constants from the enum, and
rename them to indicate that they're defined by SFF-8024.

Add and use updated SFF-8024 extended compliance code definitions for
10GBASE-T, 5GBASE-T and 2.5GBASE-T modules.

Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: hongrongxuan <hongrongxuan@huawei.com>
2024-06-12 13:16:45 +08:00
hongrongxuan d0fb58f7e8 tencent.config: enable CONFIG_PCI_IOV by default
This config is required by HNS3 driver, so enable it by default.

Signed-off-by: hongrongxuan <hongrongxuan@huawei.com>
2024-06-12 13:16:44 +08:00
Marc Zyngier 9170a1344b arm64: Add HWCAP for self-synchronising virtual counter
Since userspace can make use of the CNTVSS_EL0 instruction, expose
it via a HWCAP.

Suggested-by: Will Deacon <will@kernel.org>
Acked-by: Will Deacon <will@kernel.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20211017124225.3018098-18-maz@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
Signed-off-by: hongrongxuan <hongrongxuan@huawei.com>

 Conflicts:
	Documentation/arm64/cpu-feature-registers.rst
	arch/arm64/include/asm/hwcap.h
	arch/arm64/include/uapi/asm/hwcap.h
	arch/arm64/kernel/cpufeature.c
	arch/arm64/kernel/cpuinfo.c
2024-06-12 13:16:44 +08:00
Marc Zyngier c604df9a30 arm64: Add handling of CNTVCTSS traps
Since CNTVCTSS obey the same control bits as CNTVCT, add the necessary
decoding to the hook table. Note that there is no known user of
this at the moment.

Acked-by: Will Deacon <will@kernel.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20211017124225.3018098-17-maz@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
Signed-off-by: hongrongxuan <hongrongxuan@huawei.com>
2024-06-12 13:16:43 +08:00
Marc Zyngier e303d58c5a arm64: Add CNT{P,V}CTSS_EL0 alternatives to cnt{p,v}ct_el0
CNTPCTSS_EL0 and CNTVCTSS_EL0 are alternatives to the usual
CNTPCT_EL0 and CNTVCT_EL0 that do not require a previous ISB
to be synchronised (SS stands for Self-Synchronising).

Use the ARM64_HAS_ECV capability to control alternative sequences
that switch to these low(er)-cost primitives. Note that the
counter access in the VDSO is for now left alone until we decide
whether we want to allow this.

Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20211017124225.3018098-16-maz@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
Signed-off-by: hongrongxuan <hongrongxuan@huawei.com>
2024-06-12 13:16:43 +08:00
Marc Zyngier 594dfdf6a8 arm64: Add a capability for FEAT_ECV
Add a new capability to detect the Enhanced Counter Virtualization
feature (FEAT_ECV).

Reviewed-by: Oliver Upton <oupton@google.com>
Acked-by: Will Deacon <will@kernel.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20211017124225.3018098-15-maz@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
Signed-off-by: hongrongxuan <hongrongxuan@huawei.com>

 Conflicts:
	arch/arm64/tools/cpucaps
2024-06-12 13:16:43 +08:00
Anshuman Khandual c2d26c3ea5 arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR0 register
Enable EVC, FGT, EXS features bits in ID_AA64MMFR0 register as per ARM DDI
0487F.a specification.

Suggested-by: Will Deacon <will@kernel.org>
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Link: https://lore.kernel.org/r/1593748297-1965-2-git-send-email-anshuman.khandual@arm.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: hongrongxuan <hongrongxuan@huawei.com>

 Conflicts:
	arch/arm64/include/asm/sysreg.h
2024-06-12 13:16:42 +08:00
hongrongxuan f1cb9a5cbf kabi: reserve space for arm64 cpufeature related structure
Reserve space for the structure cpu_hwcap_keys and cpu_hwcaps.

Signed-off-by: hongrongxuan <hongrongxuan@huawei.com>
2024-06-12 13:16:42 +08:00
Marc Zyngier 9c07a988cf clocksource/drivers/arch_arm_timer: Move workaround synchronisation around
We currently handle synchronisation when workarounds are enabled
by having an ISB in the __arch_counter_get_cnt?ct_stable() helpers.

While this works, this prevents us from relaxing this synchronisation.

Instead, move it closer to the point where the synchronisation is
actually needed. Further patches will subsequently relax this.

Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20211017124225.3018098-14-maz@kernel.org
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: hongrongxuan <hongrongxuan@huawei.com>
2024-06-12 13:16:42 +08:00
Oliver Upton 44affb5b69 clocksource/drivers/arm_arch_timer: Fix masking for high freq counters
Unfortunately, the architecture provides no means to determine the bit
width of the system counter. However, we do know the following from the
specification:

 - the system counter is at least 56 bits wide
 - Roll-over time of not less than 40 years

To date, the arch timer driver has depended on the first property,
assuming any system counter to be 56 bits wide and masking off the rest.
However, combining a narrow clocksource mask with a high frequency
counter could result in prematurely wrapping the system counter by a
significant margin. For example, a 56 bit wide, 1GHz system counter
would wrap in a mere 2.28 years!

This is a problem for two reasons: v8.6+ implementations are required to
provide a 64 bit, 1GHz system counter. Furthermore, before v8.6,
implementers may select a counter frequency of their choosing.

Fix the issue by deriving a valid clock mask based on the second
property from above. Set the floor at 56 bits, since we know no system
counter is narrower than that.

[maz: fixed width computation not to lose the last bit, added
      max delta generation for the timer]

Suggested-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Oliver Upton <oupton@google.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210807191428.3488948-1-oupton@google.com
Link: https://lore.kernel.org/r/20211017124225.3018098-13-maz@kernel.org
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: hongrongxuan <hongrongxuan@huawei.com>
2024-06-12 13:16:41 +08:00
Marc Zyngier db32538c11 clocksource/drivers/arm_arch_timer: Drop unnecessary ISB on CVAL programming
Switching from TVAL to CVAL has a small drawback: we need an ISB
before reading the counter. We cannot get rid of it, but we can
instead remove the one that comes just after writing to CVAL.

This reduces the number of ISBs from 3 to 2 when programming
the timer.

Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20211017124225.3018098-12-maz@kernel.org
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: hongrongxuan <hongrongxuan@huawei.com>
2024-06-12 13:16:41 +08:00
Marc Zyngier c03cea65f4 clocksource/drivers/arm_arch_timer: Remove any trace of the TVAL programming interface
TVAL usage is now long gone, get rid of the leftovers.

Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20211017124225.3018098-11-maz@kernel.org
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: hongrongxuan <hongrongxuan@huawei.com>
2024-06-12 13:16:40 +08:00
Marc Zyngier afb00d6664 clocksource/drivers/arm_arch_timer: Work around broken CVAL implementations
The Applied Micro XGene-1 SoC has a busted implementation of the
CVAL register: it looks like it is based on TVAL instead of the
other way around. The net effect of this implementation blunder
is that the maximum deadline you can program in the timer is
32bit wide.

Use a MIDR check to notice the broken CPU, and reduce the width
of the timer to 32bit.

Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20211017124225.3018098-10-maz@kernel.org
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: hongrongxuan <hongrongxuan@huawei.com>
2024-06-12 13:16:40 +08:00
Marc Zyngier d1c780e52f clocksource/drivers/arm_arch_timer: Advertise 56bit timer to the core code
Proudly tell the code code that we have a timer able to handle
56 bits deltas.

Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20211017124225.3018098-9-maz@kernel.org
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: hongrongxuan <hongrongxuan@huawei.com>
2024-06-12 13:16:40 +08:00
Marc Zyngier bfd77a4d3b clocksource/drivers/arm_arch_timer: Move MMIO timer programming over to CVAL
Similarily to the sysreg-based timer, move the MMIO over to using
the CVAL registers instead of TVAL. Note that there is no warranty
that the 64bit MMIO access will be atomic, but the timer is always
disabled at the point where we program CVAL.

Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20211017124225.3018098-8-maz@kernel.org
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: hongrongxuan <hongrongxuan@huawei.com>
2024-06-12 13:16:39 +08:00
Marc Zyngier 41681d18a2 clocksource/drivers/arm_arch_timer: Fix MMIO base address vs callback ordering issue
The MMIO timer base address gets published after we have registered
the callbacks and the interrupt handler, which is... a bit dangerous.

Fix this by moving the base address publication to the point where
we register the timer, and expose a pointer to the timer structure
itself rather than a naked value.

Reviewed-by: Oliver Upton <oupton@google.com>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20211017124225.3018098-7-maz@kernel.org
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: hongrongxuan <hongrongxuan@huawei.com>

 Conflicts:
	drivers/clocksource/arm_arch_timer.c
2024-06-12 13:16:39 +08:00
Marc Zyngier 820709ef96 clocksource/drivers/arm_arch_timer: Move drop _tval from erratum function names
The '_tval' name in the erratum handling function names doesn't
make much sense anymore (and they were using CVAL the first place).

Drop the _tval tag.

Reviewed-by: Oliver Upton <oupton@google.com>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Tested-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20211017124225.3018098-6-maz@kernel.org
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: hongrongxuan <hongrongxuan@huawei.com>
2024-06-12 13:16:39 +08:00
Marc Zyngier 3bdca4d900 clocksource/drivers/arm_arch_timer: Move system register timer programming over to CVAL
In order to cope better with high frequency counters, move the
programming of the timers from the countdown timer (TVAL) over
to the comparator (CVAL).

The programming model is slightly different, as we now need to
read the current counter value to have an absolute deadline
instead of a relative one.

There is a small overhead to this change, which we will address
in the following patches.

Reviewed-by: Oliver Upton <oupton@google.com>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Tested-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20211017124225.3018098-5-maz@kernel.org
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: hongrongxuan <hongrongxuan@huawei.com>
2024-06-12 13:16:38 +08:00
Marc Zyngier c68edf22e2 clocksource/drivers/arm_arch_timer: Extend write side of timer register accessors to u64
The various accessors for the timer sysreg and MMIO registers are
currently hardwired to 32bit. However, we are about to introduce
the use of the CVAL registers, which require a 64bit access.

Upgrade the write side of the accessors to take a 64bit value
(the read side is left untouched as we don't plan to ever read
back any of these registers).

No functional change expected.

Reviewed-by: Oliver Upton <oupton@google.com>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Tested-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20211017124225.3018098-4-maz@kernel.org
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: hongrongxuan <hongrongxuan@huawei.com>
2024-06-12 13:16:38 +08:00
Marc Zyngier 75a5a259c0 clocksource/drivers/arm_arch_timer: Drop CNT*_TVAL read accessors
The arch timer driver never reads the various TVAL registers, only
writes to them. It is thus pointless to provide accessors
for them and to implement errata workarounds.

Drop these read-side accessors, and add a couple of BUG() statements
for the time being. These statements will be removed further down
the line.

Reviewed-by: Oliver Upton <oupton@google.com>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Tested-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20211017124225.3018098-3-maz@kernel.org
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: hongrongxuan <hongrongxuan@huawei.com>
2024-06-12 13:16:38 +08:00
Marc Zyngier ea9b4217be clocksource/arm_arch_timer: Add build-time guards for unhandled register accesses
As we are about to change the registers that are used by the driver,
start by adding build-time checks to ensure that we always handle
all registers and access modes.

Suggested-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20211017124225.3018098-2-maz@kernel.org
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: hongrongxuan <hongrongxuan@huawei.com>
2024-06-12 13:16:37 +08:00
Huang Cun 4427b501ef Revert "clocksource/drivers/arm_arch_timer: Advertise 56bit timer to the core code"
This reverts commit 5de2e163fc7488991029a2f44283c43034863b6d.

On AmpereOne cpu, the ping latency will reach 1s. so revert it.

Signed-off-by: Huang Cun <cunhuang@tencent.com>
2024-06-12 13:16:37 +08:00
Huang Cun 4c1193fc6c config: disable CONFIG_PATA_LEGACY
AmpereOne will panic if enable PATA_LEGACY:
this is the panic log:
Unable to handle kernel paging request at virtual address ffffffdffec001f2
Mem abort info:
  ESR = 0x96000007
  EC = 0x25: DABT (current EL), IL = 32 bits
  SET = 0, FnV = 0
  EA = 0, S1PTW = 0
Data abort info:
  ISV = 0, ISS = 0x00000007
  CM = 0, WnR = 0
swapper pgtable: 64k pages, 48-bit VAs, pgdp=0000000011920000
[ffffffdffec001f2] pgd=0000000011f70003, pud=0000000011f70003, pmd=0000000011f80003, pte=0000000000000000
Internal error: Oops: 96000007 [#1] SMP
Modules linked in:
CPU: 146 PID: 1 Comm: swapper/0 Tainted: G        W         5.4.241-1-tlinux4-0017-AmpereOne.772ee6bd72 #1
Hardware name: Tencent RC221/TC2-YHMB-A, BIOS 0.37.00 03/12/2024
nvme nvme0: 135/0/0 default/read/poll queues
pstate: 60800089 (nZCv daIf -PAN +UAO)
pc : inb+0x10/0x30
lr : probe_chip_type+0xe8/0x224
......
Call trace:
 inb+0x10/0x30
 legacy_init+0x2b4/0x32c
 do_one_initcall+0x48/0x250
 kernel_init_freeable+0x1cc/0x268
 kernel_init+0x18/0x118
 ret_from_fork+0x10/0x18
Code: d2bfd801 f2dffbe1 f2ffffe1 8b010000 (39400000)
---[ end trace 7cb152e9319d8ed3 ]---
Kernel panic - not syncing: Fatal exception
SMP: stopping secondary CPUs
Kernel Offset: disabled
CPU features: 0x50157,1a008a28
Memory Limit: none
---[ end Kernel panic - not syncing: Fatal exception ]---

Signed-off-by: Huang Cun <cunhuang@tencent.com>
2024-06-12 13:16:36 +08:00
Jianping Liu 0c30a8fddc Kconfig: disable BT_SCHED and ZRAM_MEMCG
Disable BT_SCHED and ZRAM_MEMCG in "make allmodconfig" and "make allyesconfig".

Signed-off-by: Jianping Liu <frankjpliu@tencent.com>
2024-06-12 13:16:36 +08:00
Jianping Liu ed46a5009f mm/Makefile: fix make rpm-pkg fail
Fix make clean error as below:
scripts/Makefile.clean:15: mm/damon/Makefile: No such file or directory
make[4]: *** No rule to make target 'mm/damon/Makefile'.
make[4]: Failed to remake makefile 'mm/damon/Makefile'.
make[3]: *** [scripts/Makefile.clean:67: mm/damon] Error 2
make[3]: Target '__clean' not remade because of errors.
make[2]: *** [Makefile:1783: _clean_mm] Error 2
make[2]: Target 'clean' not remade because of errors.
make[1]: *** [scripts/Makefile.package:56: rpm-pkg] Error 2
make: *** [Makefile:1511: rpm-pkg] Error 2

Signed-off-by: Jianping Liu <frankjpliu@tencent.com>
2024-06-12 13:16:36 +08:00
Jianping Liu 1ed2f4729e dist: provide kernel version info in kernel*core*.rpm
Other software, such as anaconda, need kernel*core*.rpm provide kernel
version info.

Signed-off-by: Jianping Liu <frankjpliu@tencent.com>
Reviewed-by: Yongliang Gao <leonylgao@tencent.com>
2024-06-12 13:16:35 +08:00
Jianping Liu 3154060704 tkernel: sync code to the same with tk4 pub/lts/0017-kabi
Sync code to the same with tk4 pub/lts/0017-kabi, except deleted rue
and wujing. Partners can submit pull requests to this branch, and we
can pick the commits to tk4 pub/lts/0017-kabi easly.

Signed-off-by: Jianping Liu <frankjpliu@tencent.com>
2024-06-12 13:13:20 +08:00
Jianping Liu c62d6b571d ock: sync codes to ock 5.4.119-20.0009.21
Gitee limit the repo's size to 3GB, to reduce the size of the code,
sync codes to ock 5.4.119-20.0009.21 in one commit.

Signed-off-by: Jianping Liu <frankjpliu@tencent.com>
2024-06-11 20:27:38 +08:00
Jianping Liu be16237b31 tkernel: add base tlinux kernel interfaces
Sync kernel codes to the same with 590eaf1fec ("Init Repo base on
linux 5.4.32 long term, and add base tlinux kernel interfaces."), which
is from tk4, and it is the base of tk4.

Signed-off-by: Jianping Liu <frankjpliu@tencent.com>
2024-06-11 20:09:33 +08:00
Linus Torvalds 219d54332a Linux 5.4 2019-11-24 16:32:01 -08:00
Linus Torvalds b8387f6f34 Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs
Pull cramfs fix from Al Viro:
 "Regression fix, fallen through the cracks"

* 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs:
  cramfs: fix usage on non-MTD device
2019-11-24 12:36:39 -08:00
Maxime Bizon 3e5aeec0e2 cramfs: fix usage on non-MTD device
When both CONFIG_CRAMFS_MTD and CONFIG_CRAMFS_BLOCKDEV are enabled, if
we fail to mount on MTD, we don't try on block device.

Note: this relies upon cramfs_mtd_fill_super() leaving no side
effects on fc state in case of failure; in general, failing
get_tree_...() does *not* mean "fine to try again"; e.g. parsed
options might've been consumed by fill_super callback and freed
on failure.

Fixes: 74f78fc5ef ("vfs: Convert cramfs to use the new mount API")

Signed-off-by: Maxime Bizon <mbizon@freebox.fr>
Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2019-11-23 21:44:49 -05:00
Linus Torvalds 6b8a794678 virtio: last minute bugfixes
Minor bugfixes all over the place.
 
 Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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Merge tag 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost

Pull last minute virtio bugfixes from Michael Tsirkin:
 "Minor bugfixes all over the place"

* tag 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost:
  virtio_balloon: fix shrinker count
  virtio_balloon: fix shrinker scan number of pages
  virtio_console: allocate inbufs in add_port() only if it is needed
  virtio_ring: fix return code on DMA mapping fails
2019-11-23 13:02:18 -08:00
Linus Torvalds 2027cabe6a Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
Pull input fix from Dmitry Torokhov:
 "Just a single revert as RMI mode should not have been enabled for this
  model [yet?]"

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input:
  Revert "Input: synaptics - enable RMI mode for X1 Extreme 2nd Generation"
2019-11-22 16:57:26 -08:00