Commit Graph

14 Commits

Author SHA1 Message Date
Thierry Reding 87904c3e82 drm/tegra: dsi: Enhance runtime power management
The MIPI DSI output on Tegra SoCs requires some external logic to
calibrate the MIPI pads before a video signal can be transmitted. This
MIPI calibration logic requires to be powered on while the MIPI pads are
being used, which is currently done as part of the DSI driver's probe
implementation.

This is suboptimal because it will leave the MIPI calibration logic
powered up even if the DSI output is never used.

On Tegra114 and earlier this behaviour also causes the driver to hang
while trying to power up the MIPI calibration logic because the power
partition that contains the MIPI calibration logic will be powered on
by the display controller at output pipeline configuration time. Thus
the power up sequence for the MIPI calibration logic happens before
it's power partition is guaranteed to be enabled.

Fix this by splitting up the API into a request/free pair of functions
that manage the runtime dependency between the DSI and the calibration
modules (no registers are accessed) and a set of enable, calibrate and
disable functions that program the MIPI calibration logic at points in
time where the power partition is really enabled.

While at it, make sure that the runtime power management also works in
ganged mode, which is currently also broken.

Reported-by: Jonathan Hunter <jonathanh@nvidia.com>
Tested-by: Jonathan Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-08-24 15:58:57 +02:00
Thierry Reding 15372d4be7 gpu: host1x: mipi: Power down regulators when unused
Keep track of the number of users of DSI and CSI pads and power down the
regulators that supply the bricks when all users are gone.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13 13:47:21 +02:00
Thierry Reding 5e7752436e gpu: host1x: mipi: Add Tegra210 support
Some changes are needed to the configuration settings for some lanes. In
addition, the clock lanes for the CSI pads can no longer be calibrated.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13 13:47:20 +02:00
Thierry Reding 7fd3ecad3f gpu: host1x: mipi: Add Tegra132 support
While Tegra132 has the same pads as Tegra124, some configuration values
need to be programmed slightly differently.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13 13:47:19 +02:00
Thierry Reding c22fb79099 gpu: host1x: mipi: Constify OF match table
This table is never modified and can therefore reside in read-only
memory.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13 13:47:18 +02:00
Thierry Reding 2ed264bf91 gpu: host1x: mipi: Clear calibration status
Before starting a new calibration cycle, make sure to clear the current
status by writing a 1 to the various "calibration done" bits.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13 13:47:17 +02:00
Thierry Reding 8ed5c06232 gpu: host1x: mipi: Fix clock lane register for DSI
Use more consistent names for the clock lane configuration registers and
fix the offset of the upper clock lane configuration register for the
first DSI pad.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13 13:47:16 +02:00
Thierry Reding 83a3c223cc gpu: host1x: mipi: Parameterize to support future SoCs
Parameterize more of the register programming to accomodate for changes
required by future SoC generations.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13 13:47:15 +02:00
Sean Paul b298e98ef6 gpu: host1x: mipi: Set MIPI_CAL_BIAS_PAD_CFG1 register
During calibration, sets the "internal reference level for drive pull-
down" to the value specified in the Tegra TRM.

Signed-off-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-11-13 16:11:57 +01:00
Sean Paul 08a15cc34d gpu: host1x: mipi: Calibrate clock lanes
Include the clock lanes when calibrating the MIPI PHY on Tegra124
compatible devices.

Signed-off-by: Sean Paul <seanpaul@chromium.org>
[treding@nvidia.com: bikeshedding]
Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-11-13 16:11:54 +01:00
Sean Paul 26f7a92a3a gpu: host1x: mipi: Preserve the contents of MIPI_CAL_CTRL
By paving the CTRL reg value, the current code changes MIPI_CAL_PRESCALE
("Auto-cal calibration step prescale") from 1us to 0.1us (val=0). In the
description for PHY's noise filter (MIPI_CAL_NOISE_FLT), the TRM states
that if the value of the prescale is 0 (or 0.1us), the filter should be
set between 2-5. However, the current code sets it to 0.

For now, let's keep the prescale and filter values as-is, which is most
likely the power-on-reset values of 0x2 and 0xa, respectively.

Signed-off-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-11-13 16:11:51 +01:00
Thierry Reding 57b17ae71f gpu: host1x: mipi: Registers are 32 bits wide
On 64-bit platforms an unsigned long would be 64 bit and cause
unnecessary casting when being passed to writel() or returned from
readl(). Make register values 32 bits wide to avoid that.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-11-13 16:11:48 +01:00
Thierry Reding aef03d3fa5 gpu: host1x: Fix more sparse warnings
Include the linux/host1x.h and dev.h headers so that function prototypes
are visible to keep sparse from suggesting that their implementations be
made static.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-12-19 09:29:51 +01:00
Thierry Reding 4de6a2d6ac gpu: host1x: Add MIPI pad calibration support
This driver adds support to perform calibration of the MIPI pads for CSI
and DSI.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-12-19 09:29:43 +01:00