Commit Graph

5 Commits

Author SHA1 Message Date
Nicolas Pitre 3ed9c82437 tegra/clk-divider: fix wrong do_div() usage
do_div() is meant to be used with an unsigned dividend.

Signed-off-by: Nicolas Pitre <nico@linaro.org>
2015-11-16 12:37:55 -05:00
Stephen Boyd 584ac4e935 clk: tegra: Properly include clk.h
Clock provider drivers generally shouldn't include clk.h because
it's the consumer API. Only include clk.h in files that are using
it. Also add in a clkdev.h include that was missing in a file
using clkdev APIs.

Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-20 11:11:17 -07:00
Thierry Reding 4f4f85fa0b clk: tegra: Implement memory-controller clock
The memory controller clock runs either at half or the same frequency as
the EMC clock.

Reviewed-By: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-11-26 09:43:23 +01:00
Andrew Bresticker 3de5bdfb4c clk: tegra: use max divider if divider overflows
When requesting a rate less than the minimum clock rate for a divider,
use the maximum divider value instead of bailing out with an error.
This matches the behavior of the generic clock divider.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
2014-02-17 16:18:34 +02:00
Prashant Gaikwad 8f8f484bf3 clk: tegra: add Tegra specific clocks
Add Tegra specific clocks, pll, pll_out, peripheral, frac_divider, super.

Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
[swarren: alloc sizeof(*foo) not sizeof(struct foo), add comments re:
storing pointers to stack variables, make a timeout loop more idiomatic,
use _clk_pll_disable() not clk_disable_pll() from _program_pll() to
avoid redundant lock operations, unified tegra_clk_periph() and
tegra_clk_periph_nodiv(), unified tegra_clk_pll{,e}, rename all clock
registration functions so they don't have the same name as the clock
structs, return -EINVAL from clk_plle_enable when matching table rate
not found, pass ops to _tegra_clk_register_pll rather than a bool.]
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-28 11:19:07 -07:00