Ideally this and similar common properties will be inherited so you
won't need to paste them in every pinctrl binding.
Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>
Reviewed-by: Caleb Connolly <caleb@connolly.tech>
Link: https://lore.kernel.org/r/20220903174150.3566935-5-iskren.chernev@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
PINCTRL_IMX depends on OF, however the dependency is missed when selected
by PINCTRL_IMX8M* (it does not follow the indirect 'select' statements),
select it explicitly.
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Linus Walleij <linus.walleij@linaro.org>
Reported-by: kernel test robot <lkp@intel.com>
Link: https://lore.kernel.org/all/202209050605.fezJUgFH-lkp@intel.com/
Fixes: 87c2a29a6b ("pinctrl: imx8m: kconfig: Depends on SOC_IMX8M")
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Link: https://lore.kernel.org/r/20220905224408.346425-1-francesco.dolcini@toradex.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
In a few comments the style is not aligned with the rest.
Correct them.
While at it, drop unneeded blank lines and deduplicate 'Author'.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Link: https://lore.kernel.org/r/20220902182650.83098-17-andriy.shevchenko@linux.intel.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Make use of the GENMASK() (far less error-prone, far more concise).
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Link: https://lore.kernel.org/r/20220902182650.83098-16-andriy.shevchenko@linux.intel.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
ACPI table on Intel Galileo Gen 1 has wrong pin number for IRQ resource
of the I²C GPIO expander. Since we know what that number is and luckily
have GPIO bases fixed for SoC's controllers, we may use a simple DMI quirk
to match the platform and retrieve GpioInt() pin on it for the expander in
question.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Link: https://lore.kernel.org/r/20220902182650.83098-15-andriy.shevchenko@linux.intel.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add support of the expander found on Intel Galileo Gen1 board.
The platform information comes from ACPI.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Link: https://lore.kernel.org/r/20220902182650.83098-14-andriy.shevchenko@linux.intel.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Convert the module to be property provider agnostic and allow
it to be used on non-OF platforms.
Add mod_devicetable.h include.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Link: https://lore.kernel.org/r/20220902182650.83098-13-andriy.shevchenko@linux.intel.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The introduced callback ->pin_dbg_show() is useful for debugging.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Link: https://lore.kernel.org/r/20220902182650.83098-12-andriy.shevchenko@linux.intel.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Move the default values to the 'default' case in the switches.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Link: https://lore.kernel.org/r/20220902182650.83098-11-andriy.shevchenko@linux.intel.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Since we have pin configuration getter and setter provided,
there is no need to duplicate that in the custom ->set_config().
Instead, switch to gpiochip_generic_config().
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Link: https://lore.kernel.org/r/20220902182650.83098-10-andriy.shevchenko@linux.intel.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The pin control framework checks pin boundaries before calling
the respective driver's callbacks. Hence no need to check for
pin boundaries, the respective conditionals won't be ever true.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Link: https://lore.kernel.org/r/20220902182650.83098-9-andriy.shevchenko@linux.intel.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The Cypress CY8C95x0 chips have an internal EEPROM that defines
initial configuration. It might be that bootloader or other
entity wrote the platform related setup into it. Don't override
it in the driver.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Link: https://lore.kernel.org/r/20220902182650.83098-8-andriy.shevchenko@linux.intel.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Since it's a pin control, GPIO counterpart needs to know the mapping
between pin numbering and GPIO numbering. Enable this by calling
gpiochip_add_pin_range() at the chip addition time.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Link: https://lore.kernel.org/r/20220902182650.83098-7-andriy.shevchenko@linux.intel.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The npins field is assigned twice. Remove the first occurrence.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Link: https://lore.kernel.org/r/20220902182650.83098-6-andriy.shevchenko@linux.intel.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The Cypress GPIO expander is an I²C discrete component. Hence
the platform may contain more than one of a such. Currently
this has limitations in the driver due to same name used for
all chips of a type. Replace this with device instance specific
name.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Link: https://lore.kernel.org/r/20220902182650.83098-5-andriy.shevchenko@linux.intel.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
It's an obvious typo in never tested piece of code that
successful detection shouldn't fail. Fix that.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Link: https://lore.kernel.org/r/20220902182650.83098-4-andriy.shevchenko@linux.intel.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
No need to assign first line number for IRQ chip.
Let IRQ core to decide.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Link: https://lore.kernel.org/r/20220902182650.83098-2-andriy.shevchenko@linux.intel.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Since recently, the kernel is nagging about mutable irq_chips:
"not an immutable chip, please consider fixing it!"
Drop the unneeded copy, flag it as IRQCHIP_IMMUTABLE, add the new
helper functions and call the appropriate gpiolib functions.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Link: https://lore.kernel.org/r/20220902182650.83098-1-andriy.shevchenko@linux.intel.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Use dev_dbg() instead of printk(KERN_DEBUG) to avoid the following
checkpatch.pl warning:
"Prefer [subsystem eg: netdev]_dbg([subsystem]dev, ... then
dev_dbg(dev, ... then pr_debug(... to printk(KERN_DEBUG ...".
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220831135636.3176406-4-claudiu.beznea@microchip.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Move gpio suspend/resume execution local to driver and let it execute as
close as possible to the moment the machine specific PM code is executed
(by setting it to .noirq member of dev_pm_ops). With this the
at91_pinctrl_gpio_suspend()/at91_pinctrl_gpio_resume() calls were removed
from arch/arm/mach-at91/pm.c and also a header has been removed.
The patch has been checked on sama5d3_xplained, sam9x60ek,
sama5d2_xplained, sama7g5ek boards.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220831135636.3176406-3-claudiu.beznea@microchip.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
- Document pin control support for the RZ/Five SoC.
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Merge tag 'renesas-pinctrl-for-v6.1-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
pinctrl: renesas: Updates for v6.1
- Document pin control support for the RZ/Five SoC.
Change PINCTRL_IMX8M* dependency from just ARCH_MXC to SOC_IMX8M,
likewise is done for other PINCTRL_IMX* kconfig. This avoid polluting
the config when SOC_IMX8M is not enabled.
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Link: https://lore.kernel.org/r/20220830142727.313080-1-francesco.dolcini@toradex.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
When the driver want to disable the signal of the function, it doesn't
need to query the state of the mux function's signal on a pin. The
condition below will miss the disable of the signal:
Ball | Default | P0 Signal | P0 Expression | Other
-----+---------+-----------+-----------------------------+----------
E21 GPIOG0 SD2CLK SCU4B4[16]=1 & SCU450[1]=1 GPIOG0
-----+---------+-----------+-----------------------------+----------
B22 GPIOG1 SD2CMD SCU4B4[17]=1 & SCU450[1]=1 GPIOG1
-----+---------+-----------+-----------------------------+----------
Assume the register status like below:
SCU4B4[16] == 1 & SCU4B4[17] == 1 & SCU450[1]==1
After the driver set the Ball E21 to the GPIOG0:
SCU4B4[16] == 0 & SCU4B4[17] == 1 & SCU450[1]==0
When the driver want to set the Ball B22 to the GPIOG1, the condition of
the SD2CMD will be false causing SCU4B4[17] not to be cleared.
Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
Acked-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20220818101839.28860-1-billy_tsai@aspeedtech.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
In order to ensure only documented properties are present, node schemas
must have unevaluatedProperties or additionalProperties set to false
(typically).
Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220823145649.3118479-6-robh@kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Feedback from Kent had showed some better selections for symbols to
use for pinctrl-amd debugfs output. Adopt some of those instead.
Fixes: e8129a076a ("pinctrl: amd: Use unicode for debugfs output")
Suggested-by: Kent Gibson <warthog618@gmail.com>
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Link: https://lore.kernel.org/r/20220823230753.14799-1-mario.limonciello@amd.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The mt8186 contains 8 GPIO physical address bases that correspond to
the 'reg-names' of the pinctrl driver. The 'reg-names' entries in
bindings are ordered incorrectly, though. The system crashes due of an
erroneous address when the regulator initializes.
We fix the 'reg-names' for the pinctrl nodes and the pinctrl-mt8186
example in bindings.
Fixes: 338e953f1b ("dt-bindings: pinctrl: mt8186: add pinctrl file and binding document")
Co-developed-by: Guodong Liu <guodong.liu@mediatek.com>
Signed-off-by: Guodong Liu <guodong.liu@mediatek.com>
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Link: https://lore.kernel.org/r/20220819120649.21523-1-allen-kh.cheng@mediatek.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add pinctrl driver support for MediaTek SoC mt8188.
Signed-off-by: Hui.Liu <hui.liu@mediatek.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Link: https://lore.kernel.org/r/20220818075012.20880-3-hui.liu@mediatek.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add the pinctrl header file on MediaTek mt8188.
Add the new binding document for pinctrl on MediaTek mt8188.
Signed-off-by: Hui.Liu <hui.liu@mediatek.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Link: https://lore.kernel.org/r/20220818075012.20880-2-hui.liu@mediatek.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add pinctrl driver to support pin configuration for LPASS
(Low Power Audio SubSystem) LPI (Low Power Island) pinctrl
on SC8280XP.
This IP is an additional pin control block for Audio Pins on top the
existing SoC Top level pin-controller.
Hardware setup looks like:
TLMM GPIO[189 - 207] --> LPASS LPI GPIO [0 - 18]
This pin controller has some similarities compared to Top level
msm SoC Pin controller like 'each pin belongs to a single group'
and so on. However this one is intended to control only audio
pins in particular, which can not be configured/touched by the
Top level SoC pin controller except setting them as gpios.
Apart from this, slew rate is also available in this block for
certain pins which are connected to SLIMbus or SoundWire Bus.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Link: https://lore.kernel.org/r/20220817113747.9111-3-srinivas.kandagatla@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add pinctrl driver to support pin configuration for LPASS
(Low Power Audio SubSystem) LPI (Low Power Island) pinctrl
on SM8450.
This IP is an additional pin control block for Audio Pins on top the
existing SoC Top level pin-controller.
Hardware setup looks like:
TLMM GPIO[165 - 187] --> LPASS LPI GPIO [0 - 22]
This pin controller has some similarities compared to Top level
msm SoC Pin controller like 'each pin belongs to a single group'
and so on. However this one is intended to control only audio
pins in particular, which can not be configured/touched by the
Top level SoC pin controller except setting them as gpios.
Apart from this, slew rate is also available in this block for
certain pins which are connected to SLIMbus or SoundWire Bus.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Link: https://lore.kernel.org/r/20220817113833.9625-3-srinivas.kandagatla@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The pin control header provides struct pingroup and PINCTRL_PINGROUP() macro.
Utilize them instead of open coded variants in the driver.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20220621112904.65674-1-andriy.shevchenko@linux.intel.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The pin control header provides struct pingroup and PINCTRL_PINGROUP() macro.
Utilize them instead of open coded variants in the driver.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20220620165053.74170-1-andriy.shevchenko@linux.intel.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add support for cypress I2C GPIO expanders cy8c9520, cy8c9540 and
cy8c9560. The GPIO expanders feature a PWM mode, thus add it as
pinctrl driver.
The chip features multiple drive modes for each pin when configured
as output and multiple bias settings when configured as input.
Tested all three components and verified that all functionality
is fully working.
Datasheet: https://www.cypress.com/file/37971/download
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Link: https://lore.kernel.org/r/20220816054917.7893-3-patrick.rudolph@9elements.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The aspeed pinctrl parent node (SCU) in the examples is missing various
properties. Add the properties in preparation for the SCU schema.
Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220810161635.73936-2-robh@kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Now when all MPP pins are properly defined and every MPP pin has GPIO
function, always checks for errors in armada_37xx_gpio_request_enable()
function when calling armada_37xx_pmx_set_by_name(). Function
armada_37xx_pmx_set_by_name() should not return "not supported" error
anymore for any GPIO pin when requesting GPIO mode.
Fixes: 87466ccd94 ("pinctrl: armada-37xx: Add pin controller support for Armada 37xx")
Signed-off-by: Pali Rohár <pali@kernel.org>
Link: https://lore.kernel.org/r/20220805122202.23174-3-pali@kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
All 3 MPP pins (20, 21 and 22) can be configured individually and also can
be configured to GPIO functions. Fix definitions for these MPP pins in
existing pin groups. After this change GPIO function can be enabled just
for one of these 3 pins.
Fixes: 87466ccd94 ("pinctrl: armada-37xx: Add pin controller support for Armada 37xx")
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lore.kernel.org/r/20220805122202.23174-2-pali@kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
gpio1_5 and gpio2_2 are GPIO-only pins. Add them into MPP groups table
so they are properly exported as valid pin numbers.
Fixes: 87466ccd94 ("pinctrl: armada-37xx: Add pin controller support for Armada 37xx")
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lore.kernel.org/r/20220805122202.23174-1-pali@kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Andy Shevchenko