Commit Graph

221576 Commits

Author SHA1 Message Date
Jesper Juhl 520efd1ace mac80211: fix failure to check kmalloc return value in key_key_read
I noticed two small issues in mac80211/debugfs_key.c::key_key_read while
reading through the code. Patch below.

The key_key_read() function returns ssize_t and the value that's actually
returned is the return value of simple_read_from_buffer() which also
returns ssize_t, so let's hold the return value in a ssize_t local
variable rather than a int one.

Also, memory is allocated dynamically with kmalloc() which can fail, but
the return value of kmalloc() is not checked, so we may end up operating
on a null pointer further on. So check for a NULL return and bail out with
-ENOMEM in that case.

Signed-off-by: Jesper Juhl <jj@chaosbits.net>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2010-10-29 14:33:26 -04:00
Paul Fox 731b203499 libertas: Fix sd8686 firmware reload
For the SD8686, we cannot rely on the scratch register to read the firmware
load status, because the same register is used for storing RX packet length.
Broaden the check to account for this.

The module can now be unloaded/reloaded successfully.

Based on the implementation from libertas_tf.

Signed-off-by: Daniel Drake <dsd@laptop.org>
Acked-by: Dan Williams <dcbw@redhat.com>
Signed-off-by: Steve deRosier <steve@cozybit.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2010-10-29 14:33:25 -04:00
Mohammed Shafi Shajakhan 4fc4fbd1d9 ath9k: Fix incorrect access of rate flags in RC
The index variable to access the rate flags should be obtained from the
inner loop counter which corresponds to the rate table structure.This
fixes the invalid rate selection i.e when the supported basic rate is
invalid on a particular band and also the following warning message.
Thanks to Raj for finding this out.

Call Trace:

 [<ffffffff8104ee4a>] warn_slowpath_common+0x7a/0xb0

 [<ffffffff8104ee95>] warn_slowpath_null+0x15/0x20

 [<ffffffffa0583c45>] ath_get_rate+0x595/0x5b0 [ath9k]

 [<ffffffff811a0636>] ? cpumask_next_and+0x36/0x50

 [<ffffffffa0405186>] rate_control_get_rate+0x86/0x160 [mac80211]

 [<ffffffffa040dfac>] invoke_tx_handlers+0x81c/0x12d0 [mac80211]

 [<ffffffffa040eae9>] ieee80211_tx+0x89/0x2b0 [mac80211]

 [<ffffffff812891bc>] ? pskb_expand_head+0x1cc/0x1f0

 [<ffffffffa040edc5>] ieee80211_xmit+0xb5/0x1c0 [mac80211]

 [<ffffffffa041026f>] ieee80211_tx_skb+0x4f/0x60 [mac80211]

 [<ffffffffa03fe016>] ieee80211_send_nullfunc+0x46/0x60 [mac80211]

 [<ffffffffa03f91d7>] ieee80211_offchannel_stop_station+0x107/0x150
[mac80211]

 [<ffffffff812891bc>] ? pskb_expand_head+0x1cc/0x1f0

 [<ffffffffa040edc5>] ieee80211_xmit+0xb5/0x1c0 [mac80211]

 [<ffffffffa041026f>] ieee80211_tx_skb+0x4f/0x60 [mac80211]

 [<ffffffffa03fe016>] ieee80211_send_nullfunc+0x46/0x60 [mac80211]

 [<ffffffffa03f91d7>] ieee80211_offchannel_stop_station+0x107/0x150
[mac80211]

 [<ffffffffa03f8896>] ieee80211_scan_work+0x146/0x600 [mac80211]

 [<ffffffff8133a375>] ? schedule+0x2f5/0x8e0

 [<ffffffffa03f8750>] ? ieee80211_scan_work+0x0/0x600 [mac80211]

 [<ffffffff81064fcf>] process_one_work+0x10f/0x380

 [<ffffffff81066bc2>] worker_thread+0x162/0x340

 [<ffffffff81066a60>] ? worker_thread+0x0/0x340

Cc: stable@kernel.org
Signed-off-by: Mohammed Shafi Shajakhan <mshajakhan@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2010-10-29 14:33:25 -04:00
Dongdong Deng ff10b88b5a kgdb,ppc: Individual register get/set for ppc
commit 534af1082329392bc29f6badf815e69ae2ae0f4c(kgdb,kdb: individual
register set and and get API) introduce dbg_get_reg/dbg_set_reg API
for individual register get and set.

This patch implement those APIs for ppc.

Signed-off-by: Dongdong Deng <dongdong.deng@windriver.com>
Signed-off-by: Jason Wessel <jason.wessel@windriver.com>
2010-10-29 13:14:42 -05:00
Dongdong Deng 4dacd5c073 kgdbts: prevent re-entry to kgdbts before it unregisters
The "kgdb_connected" variable of debug_core just indicates whether or
not kgdbts is connected to the debug_core.  It does not completely
prevent a script from trying invoke kgdbts again and possibly crashing
the system (see Call Trace below).

The configured variable in kgtbts can be used instead of
kgdb_connected instead of kgdb_connected. The cleanup_kgdbts() can
also be removed because there is no possible way to build kgdbts as a
kernel module that you could unload with rmmod.

Call Trace:
-----------------------------------------------------------------
root:/$ echo kgdbts=V1S1000 > /sys/module/kgdbts/parameters/kgdbts
kgdb: Unregistered I/O driver kgdbts, debugger disabled.
------------[ cut here ]------------
WARNING: at kernel/debug/debug_core.c:1002
kgdb_unregister_io_module+0xec/0x100()
Hardware name: Moon Creek platform
Modules linked in:
Pid: 664, comm: sh Not tainted 2.6.34.1-WR4.0.0.0_standard #58
Call Trace:
 [<c103b1ed>] warn_slowpath_common+0x6d/0xa0
 [<c1079fdc>] ? kgdb_unregister_io_module+0xec/0x100
 [<c1079fdc>] ? kgdb_unregister_io_module+0xec/0x100
 [<c10544e0>] ? param_attr_store+0x0/0x20
 [<c103b235>] warn_slowpath_null+0x15/0x20
 [<c1079fdc>] kgdb_unregister_io_module+0xec/0x100
 [<c124e4ea>] cleanup_kgdbts+0x1a/0x20
 [<c124eced>] param_set_kgdbts_var+0x6d/0xb0
 [<c124ec80>] ? param_set_kgdbts_var+0x0/0xb0
 [<c10544f7>] param_attr_store+0x17/0x20
 [<c105457c>] module_attr_store+0x2c/0x40
 [<c111fe84>] sysfs_write_file+0x94/0xf0
 [<c10d42f6>] vfs_write+0x96/0x130
 [<c111fdf0>] ? sysfs_write_file+0x0/0xf0
 [<c10d44d6>] sys_write+0x46/0xd0
 [<c13bf329>] system_call_done+0x0/0x4
---[ end trace 4eb028c6ee43154c ]---
kgdb: Unregistered I/O driver kgdbts, debugger disabled.
-----------------------------------------------------------------

[jason.wessel@windriver.com: remove cleanup_kgdbts() ]
Signed-off-by: Dongdong Deng <dongdong.deng@windriver.com>
Signed-off-by: Jason Wessel <jason.wessel@windriver.com>
2010-10-29 13:14:41 -05:00
Dongdong Deng d7ba979d45 debug_core,x86,blackfin: Clean up hw debug disable API
The kgdb_disable_hw_debug() was an architecture specific function for
disabling all hardware breakpoints on a per cpu basis when entering
the debug core.

This patch will remove the weak function kdbg_disable_hw_debug() and
change it into a call back which lives with the rest of hw breakpoint
call backs in struct kgdb_arch.

Signed-off-by: Dongdong Deng <dongdong.deng@windriver.com>
Signed-off-by: Jason Wessel <jason.wessel@windriver.com>
2010-10-29 13:14:41 -05:00
Jason Wessel 578bd4dfcd kdb: Fix early debugging crash regression
The kdb_current legally be equal to NULL in the early boot of the x86
arch.  The problem pcan be observed by booting with the kernel arguments:

    earlyprintk=vga ekgdboc=kbd kgdbwait

The kdb shell will oops on entry and recursively fault because it
cannot get past the final stage of shell initialization.

Signed-off-by: Jason Wessel <jason.wessel@windriver.com>
2010-10-29 13:14:41 -05:00
Rabin Vincent 834b2964b7 kgdb,arm: fix register dump
DBG_MAX_REG_NUM incorrectly had the number of indices in the GDB regs
array rather than the number of registers, leading to an oops when the
"rd" command is used in KDB.

Cc: stable@kernel.org
Signed-off-by: Rabin Vincent <rabin@rab.in>
Signed-off-by: Jason Wessel <jason.wessel@windriver.com>
2010-10-29 13:14:40 -05:00
Jason Wessel 931ea24819 kdb: fix per_cpu command to remove supress mask
Rusty pointed out that the per_cpu command uses up lots of space on
the stack and the cpu supress mask is probably not needed.

This patch removes the need for the supress mask as well as fixing up
the following problems with the kdb per_cpu command:
  * The per_cpu command should allow an address as an argument
  * When you have more data than can be displayed on one screen allow
    the user to break out of the print loop.

Reported-by: Rusty Russell <rusty@rustcorp.com.au>
Signed-off-by: Jason Wessel <jason.wessel@windriver.com>
2010-10-29 13:14:40 -05:00
Jason Wessel 4aad8f51d0 kdb: Add kdb kernel module sample
Add an example of how to add a dynamic kdb shell command via a kernel
module.

Signed-off-by: Jason Wessel <jason.wessel@windriver.com>
2010-10-29 13:14:39 -05:00
Linus Torvalds b77d643ced Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://git.linux-mips.org/pub/scm/upstream-linus: (46 commits)
  ftrace/MIPS: Enable C Version of recordmcount
  ftrace/MIPS: Add module support for C version of recordmcount
  ftrace/MIPS: Add MIPS64 support for C version of recordmcount
  MIPS: Make TASK_SIZE reflect proper size for both 32 and 64 bit processes.
  MIPS: Allow UserLocal on MIPS_R1 processors
  MIPS: Honor L2 bypass bit
  MIPS: Add BMIPS CP0 register definitions
  MIPS: Add BMIPS processor types to Kconfig
  MIPS: Decouple BMIPS CPU support from bcm47xx/bcm63xx SoC code
  MIPS: Add support for hardware performance events (mipsxx)
  MIPS: Perf-events: Add callchain support
  MIPS: add support for hardware performance events (skeleton)
  MIPS: add support for software performance events
  MIPS: define local_xchg from xchg_local to atomic_long_xchg
  MIPS: AR7: Add support for Titan (TNETV10xx) SoC variant
  MIPS: AR7: Initialize GPIO earlier
  MIPS: Add platform device and Kconfig for Octeon USB EHCI / OHCI
  USB: Add EHCI and OHCH glue for OCTEON II SOCs.
  MIPS: Octeon: Add register definitions for EHCI / OHCI USB glue logic.
  MIPS: Octeon: Apply CN63XXP1 errata workarounds.
  ...
2010-10-29 11:13:10 -07:00
Wu Zhangjin 64575f918f ftrace/MIPS: Enable C Version of recordmcount
Selects HAVE_C_RECORDMCOUNT to use the C version of the recordmcount
intead of the old Perl Version of recordmcount.

Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com>
LKML-Reference: <bb99009a9ac79d3f55a8c8bf1c8bd2bc0e1f160e.1288176026.git.wuzhangjin@gmail.com>
Signed-off-by: Steven Rostedt <rostedt@goodmis.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-29 19:08:56 +01:00
Wu Zhangjin 412910cd04 ftrace/MIPS: Add module support for C version of recordmcount
Since MIPS modules' address space differs from the core kernel space, to access
the _mcount in the core kernel, the kernel functions in modules must use long
call (-mlong-calls): load the _mcount address into one register and jump to the
address stored by the register:

 c:  3c030000        lui     v1,0x0  <-------->  b label
           c: R_MIPS_HI16  _mcount
           c: R_MIPS_NONE  *ABS*
           c: R_MIPS_NONE  *ABS*
10:  64630000        daddiu  v1,v1,0
          10: R_MIPS_LO16 _mcount
          10: R_MIPS_NONE *ABS*
          10: R_MIPS_NONE *ABS*
14:	03e0082d 	move	at,ra
18:	0060f809 	jalr	v1
label:

In the old Perl version of recordmcount, we only need to record the position of
the 1st R_MIPS_HI16 type of _mcount, and later, in ftrace_make_nop(), replace
the instruction in this position by a "b label" and in ftrace_make_call(),
replace it back.

But, the default C version of recordmcount records all of the _mcount symbols,
so, we must filter the 2nd _mcount like the Perl version of recordmcount does.

The C version of recordmcount copes with the symbols before they are linked, So
It doesn't know the type of the symbols and therefore can not filter the
symbols as the Perl version of recordmcount does. But as we can see above, the
2nd _mcount symbols of the long call alawys follows the 1st _mcount symbol of
the same long call, which means the offset from the 1st to the 2nd is fixed, it
is 0x10-0xc = 4 here, 4 is the length of the 1st load instruciton, for MIPS has
fixed length of instructions, this offset is always 4.

And as we know, the _mcount is inserted into the entry of every kernel
function, the offset between the other _mcount's is expected to be always
bigger than 4. So, to filter the 2ns _mcount symbol of the long call, we can
simply check the offset between two _mcount symbols, If it is 4, then, filter
the 2nd _mcount symbol.

To avoid touching too much code, an 'empty' function fn_is_fake_mcount() is
added for all of the archs, and the specific archs can override it via chaning
the function pointer: is_fake_mcount in do_file() with the e_machine. e.g. This
patch adds MIPS_is_fake_mcount() to override the default fn_is_fake_mcount()
pointed by is_fake_mcount.

This fn_is_fake_mcount() checks if the _mcount symbol is fake, e.g. the 2nd
_mcount symbol of the long call is fake, for there are 2 _mcount symbols mapped
to one real mcount call, so, one of them is fake and must be filtered.

This fn_is_fake_mcount() is called in sift_rel_mcount() after finding the
_mcount symbols and before adding the _mcount symbol into mrelp, so, it can
prevent the fake mcount symbol going into the last __mcount_loc table.

Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com>
LKML-Reference: <b866f0138224340a132d31861fa3f9300dee30ac.1288176026.git.wuzhangjin@gmail.com>
Signed-off-by: Steven Rostedt <rostedt@goodmis.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-29 19:08:55 +01:00
John Reiser a2d49358ba ftrace/MIPS: Add MIPS64 support for C version of recordmcount
MIPS64 has 'weird' Elf64_Rel.r_info[1,2], which must be used instead of
the generic Elf64_Rel.r_info, otherwise, the C version of recordmcount
will not work for "segmentation fault".

Usage of "union mips_r_info" and the functions MIPS64_r_sym() and
MIPS64_r_info() written by Maciej W. Rozycki <macro@linux-mips.org>

----
[1] http://techpubs.sgi.com/library/manuals/4000/007-4658-001/pdf/007-4658-001.pdf
[2] arch/mips/include/asm/module.h

Tested-by: Wu Zhangjin <wuzhangjin@gmail.com>
Signed-off-by: John Reiser <jreiser@BitWagon.com>
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
LKML-Reference: <AANLkTinwXjLAYACUfhLYaocHD_vBbiErLN3NjwN8JqSy@mail.gmail.com>
LKML-Reference: <910dc2d5ae1ed042df4f96815fe4a433078d1c2a.1288176026.git.wuzhangjin@gmail.com>
Signed-off-by: Steven Rostedt <rostedt@goodmis.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-29 19:08:54 +01:00
David Daney 949e51bea3 MIPS: Make TASK_SIZE reflect proper size for both 32 and 64 bit processes.
The TASK_SIZE macro should reflect the size of a user process virtual
address space.  Previously for 64-bit kernels, this was not the case.
The immediate cause of pain was in
hugetlbfs/inode.c:hugetlb_get_unmapped_area() where 32-bit processes
trying to mmap a huge page would be served a page with an address
outside of the 32-bit address range.  But there are other uses of
TASK_SIZE in the kernel as well that would like an accurate value.

The new definition is nice because it now makes TASK_SIZE and
TASK_SIZE_OF() yield the same value for any given process.

For 32-bit kernels there should be no change, although I did factor
out some code in asm/processor.h that became identical for the 32-bit and
64-bit cases.

__UA_LIMIT is now set to ~((1 << SEGBITS) - 1) for 64-bit kernels.
This should eliminate the possibility of getting a
AddressErrorException in the kernel for addresses that pass the
access_ok() test.

With the patch applied, I can still run o32, n32 and n64 processes,
and have an o32 shell fork/exec both n32 and n64 processes.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1701/
2010-10-29 19:08:53 +01:00
Kevin Cernekee 18d693b359 MIPS: Allow UserLocal on MIPS_R1 processors
Some MIPS32R1 processors implement UserLocal (RDHWR $29) to accelerate
programs that make extensive use of thread-local storage.  Therefore,
setting up the HWRENA register should not depend on cpu_has_mips_r2.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
2010-10-29 19:08:53 +01:00
Kevin Cernekee ea31a6b203 MIPS: Honor L2 bypass bit
On many of the newer MIPS32 cores, CP0 CONFIG2 bit 12 (L2B) indicates
that the L2 cache is disabled and therefore Linux should not attempt
to use it.

[Ralf: Moved the code added by Kevin's original patch into a separate
function that can easily be replaced for platforms that need more a
different probe.]

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: linux-mips@linux-mips.org>
Cc: <linux-kernel@vger.kernel.org>
Patchwork: https://patchwork.linux-mips.org/patch/1723/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-29 19:08:52 +01:00
Kevin Cernekee af23117263 MIPS: Add BMIPS CP0 register definitions
Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: mbizon@freebox.fr
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Tested-by: Florian Fainelli <ffainelli@freebox.fr>
Patchwork: https://patchwork.linux-mips.org/patch/1708/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org
2010-10-29 19:08:52 +01:00
Kevin Cernekee c1c0c461c6 MIPS: Add BMIPS processor types to Kconfig
[v2: add "VIPER" marketing name for BMIPS4350]

Add processor feature definitions for BMIPS3300, BMIPS4350, BMIPS4380,
and BMIPS5000.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: mbizon@freebox.fr
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Tested-by: Florian Fainelli <ffainelli@freebox.fr>
Patchwork: https://patchwork.linux-mips.org/patch/1716/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org
2010-10-29 19:08:51 +01:00
Kevin Cernekee 602977b0d6 MIPS: Decouple BMIPS CPU support from bcm47xx/bcm63xx SoC code
BMIPS processor cores are used in 50+ different chipsets spread across
5+ product lines.  In many cases the chipsets do not share the same
peripheral register layouts, the same register blocks, the same
interrupt controllers, the same memory maps, or much of anything else.

But, across radically different SoCs that share nothing more than the
same BMIPS CPU, a few things are still mostly constant:

SMP operations
Access to performance counters
DMA cache coherency quirks
Cache and memory bus configuration

So, it makes sense to treat each BMIPS processor type as a generic
"building block," rather than tying it to a specific SoC.  This makes it
easier to support a large number of BMIPS-based chipsets without
unnecessary duplication of code, and provides the infrastructure needed
to support BMIPS-proprietary features.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: mbizon@freebox.fr
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Tested-by: Florian Fainelli <ffainelli@freebox.fr>
Patchwork: https://patchwork.linux-mips.org/patch/1706/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org
2010-10-29 19:08:50 +01:00
Deng-Cheng Zhu 3a9ab99e03 MIPS: Add support for hardware performance events (mipsxx)
This patch adds the mipsxx Perf-events support based on the skeleton.
Generic hardware events and cache events are now fully implemented for
the 24K/34K/74K/1004K cores. To support other cores in mipsxx (such as
R10000/SB1), the generic hardware event tables and cache event tables
need to be filled out. To support other CPUs which have different PMU
than mipsxx, such as RM9000 and LOONGSON2, the additional files
perf_event_$cpu.c need to be created.

Raw event is an important part of Perf-events. It helps the user collect
performance data for events that are not listed as the generic hardware
events and cache events but ARE supported by the CPU's PMU.

This patch also adds this feature for mipsxx 24K/34K/74K/1004K. For how to
use it, please refer to processor core software user's manual and the
comments for mipsxx_pmu_map_raw_event() for more details.

Please note that this is a "precise" implementation, which means the
kernel will check whether the requested raw events are supported by this
CPU and which hardware counters can be assigned for them.

To test the functionality of Perf-event, you may want to compile the tool
"perf" for your MIPS platform. You can refer to the following URL:
http://www.linux-mips.org/archives/linux-mips/2010-10/msg00126.html

You also need to customize the CFLAGS and LDFLAGS in tools/perf/Makefile
for your libs, includes, etc.

In case you encounter the boot failure in SMVP kernel on multi-threading
CPUs, you may take a look at:
http://www.linux-mips.org/git?p=linux-mti.git;a=commitdiff;h=5460815027d802697b879644c74f0e8365254020

Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@gmail.com>
To: linux-mips@linux-mips.org
Cc: a.p.zijlstra@chello.nl
Cc: paulus@samba.org
Cc: mingo@elte.hu
Cc: acme@redhat.com
Cc: jamie.iles@picochip.com
Cc: ddaney@caviumnetworks.com
Cc: matt@console-pimps.org
Patchwork: https://patchwork.linux-mips.org/patch/1689/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

 create mode 100644 arch/mips/kernel/perf_event_mipsxx.c
2010-10-29 19:08:49 +01:00
Deng-Cheng Zhu 7e788d967c MIPS: Perf-events: Add callchain support
Adds callchain support for MIPS Perf-events. For more info on this feature,
please refer to tools/perf/Documentation/perf-report.txt and
tools/perf/design.txt.

Currently userspace callchain data is not recorded, because we do not have
a safe way to do this.

Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@gmail.com>
Acked-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Cc: a.p.zijlstra@chello.nl
Cc: paulus@samba.org
Cc: mingo@elte.hu
Cc: acme@redhat.com
Cc: jamie.iles@picochip.com
Cc: matt@console-pimps.org
Patchwork: https://patchwork.linux-mips.org/patch/1690/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-29 19:08:49 +01:00
Deng-Cheng Zhu 14f7001284 MIPS: add support for hardware performance events (skeleton)
This patch provides the skeleton of the HW perf event support. To enable
this feature, we can not choose the SMTC kernel; Oprofile should be
disabled; kernel performance events be selected. Then we can enable it in
Kernel type menu.

Oprofile for MIPS platforms initializes irq at arch init time. Currently
we do not change this logic to allow PMU reservation.

If a platform has EIC, we can use the irq base and perf counter irq offset
defines for the interrupt controller in specific init_hw_perf_events().

Based on this skeleton patch, the 3 different kinds of MIPS PMU, namely,
mipsxx/loongson2/rm9000, can be supported by adding corresponding lower
level C files at the bottom. The suggested names of these files are
perf_event_mipsxx.c/perf_event_loongson2.c/perf_event_rm9000.c. So, for
example, we can do this by adding "#include perf_event_mipsxx.c" at the
bottom of perf_event.c.

In addition, PMUs with 64bit counters are also considered in this patch.

Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@gmail.com>
To: linux-mips@linux-mips.org
Cc: a.p.zijlstra@chello.nl
Cc: paulus@samba.org
Cc: mingo@elte.hu
Cc: acme@redhat.com
Cc: jamie.iles@picochip.com
Cc: ddaney@caviumnetworks.com
Cc: matt@console-pimps.org
Patchwork: https://patchwork.linux-mips.org/patch/1688/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-29 19:08:48 +01:00
Deng-Cheng Zhu 7f788d2d53 MIPS: add support for software performance events
Software events are required as part of the measurable stuff by the
Linux performance counter subsystem. Here is the list of events added by
this patch:
PERF_COUNT_SW_PAGE_FAULTS
PERF_COUNT_SW_PAGE_FAULTS_MIN
PERF_COUNT_SW_PAGE_FAULTS_MAJ
PERF_COUNT_SW_ALIGNMENT_FAULTS
PERF_COUNT_SW_EMULATION_FAULTS

Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@gmail.com>
To: linux-mips@linux-mips.org
Cc: a.p.zijlstra@chello.nl
Cc: paulus@samba.org
Cc: mingo@elte.hu
Cc: acme@redhat.com
Cc: jamie.iles@picochip.com
Acked-by: David Daney <ddaney@caviumnetworks.com>
Reviewed-by: Matt Fleming <matt@console-pimps.org>
Patchwork: https://patchwork.linux-mips.org/patch/1686/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-29 19:08:48 +01:00
Deng-Cheng Zhu 6dbd972850 MIPS: define local_xchg from xchg_local to atomic_long_xchg
Perf-events is now using local_t helper functions internally. There is a
use of local_xchg(). On MIPS, this is defined to xchg_local() which is
missing in asm/system.h. This patch re-defines local_xchg() in asm/local.h
to atomic_long_xchg(). Then Perf-events can pass the build.

Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@gmail.com>
To: linux-mips@linux-mips.org
Cc: a.p.zijlstra@chello.nl
Cc: paulus@samba.org
Cc: mingo@elte.hu
Cc: acme@redhat.com
Cc: jamie.iles@picochip.com
Cc: ddaney@caviumnetworks.com
Cc: matt@console-pimps.org
Patchwork: https://patchwork.linux-mips.org/patch/1687/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-29 19:08:47 +01:00
Florian Fainelli 238dd317f7 MIPS: AR7: Add support for Titan (TNETV10xx) SoC variant
Add support for Titan TNETV1050,1055,1056,1060 variants. This SoC is almost
completely identical to AR7 except on a few points:
- a second bank of gpios is available
- vlynq0 on titan is vlynq1 on ar7
- different PHY addresses for cpmac0

This SoC can be found on commercial products like the Linksys WRTP54G

Original patch by Xin with improvments by Florian.

Signed-off-by: Xin Zhen <xlonestar2000@aim.com>
Signed-off-by: Florian Fainelli <florian@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/1563/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

---
2010-10-29 19:08:46 +01:00
Florian Fainelli 3bc6968adc MIPS: AR7: Initialize GPIO earlier
In order to detect the Titan variant, we must initialize GPIOs earlier since
detection relies on some GPIO values to be set.

Signed-off-by: Florian Fainelli <florian@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/1562/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

---
2010-10-29 19:08:46 +01:00
David Daney 340fbb8b12 MIPS: Add platform device and Kconfig for Octeon USB EHCI / OHCI
Declare that OCTEON reference boards have both OHCI and EHCI.

Add platform devices for the corresponding hardware.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-usb@vger.kernel.org
To: dbrownell@users.sourceforge.net
Patchwork: http://patchwork.linux-mips.org/patch/1676/
Acked-by: Greg Kroah-Hartman <gregkh@suse.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-29 19:08:45 +01:00
David Daney 1643accdaa USB: Add EHCI and OHCH glue for OCTEON II SOCs.
The OCTEON II SOC has USB EHCI and OHCI controllers connected directly
to the internal I/O bus.  This patch adds the necessary 'glue' logic
to allow ehci-hcd and ohci-hcd drivers to work on OCTEON II.

The OCTEON normally runs big-endian, and the ehci/ohci internal
registers have host endianness, so we need to select
USB_EHCI_BIG_ENDIAN_MMIO.

The ehci and ohci blocks share a common clocking and PHY
infrastructure.  Initialization of the host controller and PHY clocks
is common between the two and is factored out into the
octeon2-common.c file.

Setting of USB_ARCH_HAS_OHCI and USB_ARCH_HAS_EHCI is done in
arch/mips/Kconfig in a following patch.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-usb@vger.kernel.org
To: dbrownell@users.sourceforge.net
Patchwork: http://patchwork.linux-mips.org/patch/1675/
Acked-by: Greg Kroah-Hartman <gregkh@suse.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-29 19:08:44 +01:00
David Daney 4169b86324 MIPS: Octeon: Add register definitions for EHCI / OHCI USB glue logic.
The EHCI and OHCI blocks connection to the I/O bus is controlled by
these registers.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-usb@vger.kernel.org
To: dbrownell@users.sourceforge.net
Patchwork: http://patchwork.linux-mips.org/patch/1674/
Acked-by: Greg Kroah-Hartman <gregkh@suse.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

 create mode 100644 arch/mips/include/asm/octeon/cvmx-uctlx-defs.h
2010-10-29 19:08:43 +01:00
David Daney c9941158fd MIPS: Octeon: Apply CN63XXP1 errata workarounds.
The CN63XXP1 needs a couple of workarounds to ensure memory is not written
in unexpected ways.

All PREF with hints in the range 0-4,6-24 are replaced with PREF 28.  We
pass a flag to the assembler to cover compiler generated code, and patch
uasm for the dynamically generated code.

The write buffer threshold is reduced to 4.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Patchwork: http://patchwork.linux-mips.org/patch/1672/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-29 19:08:43 +01:00
David Daney 468ffde46d WATCHDOG: octeon-wdt: Use I/O clock rate for timing calculations.
The creation of the I/O clock domain requires some adjustments.  Since
the watchdog counters are clocked by the I/O clock, use its rate for
timing calculations.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Cc: Wim Van Sebroeck <wim@iguana.be>
Cc: linux-watchdog@vger.kernel.org
Patchwork: http://patchwork.linux-mips.org/patch/1659/
Acked-by: Wim Van Sebroeck <wim@iguana.be>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-29 19:08:42 +01:00
David Daney 1fa25ab2ca ATA: pata_octeon_cf: Use I/O clock rate for timing calculations.
The creation of the I/O clock domain requires some adjustments.  Since the
CF bus timing logic is clocked by the I/O clock, use its rate for delay
calculations.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Cc: Jeff Garzik <jgarzik@pobox.com>
Cc: linux-ide@vger.kernel.org
Patchwork: http://patchwork.linux-mips.org/patch/1660/
Acked-by: Jeff Garzik <jgarzik@redhat.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-29 19:08:41 +01:00
David Daney 4b8bca7028 MIPS: Octeon: Use I/O clock rate for calculations.
The I2C and UARTS are clocked by the I/O clock, use its rate for these
devices.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Patchwork: http://patchwork.linux-mips.org/patch/1670/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-29 19:08:41 +01:00
David Daney e195aa3039 MIPS: Octeon: Add octeon_get_io_clock_rate() for cn63xx
Starting with cn63xx Octeon I/O blocks are clocked at a different rate
than the CPU.  Add a new function octeon_get_io_clock_rate() that
yields the I/O clock rate.

Also rearrange octeon_get_clock_rate() to get the value from the saved
sysinfo structure.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Patchwork: http://patchwork.linux-mips.org/patch/1671/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-29 19:08:40 +01:00
David Daney 3b29dadff9 MIPS: Octeon: Remove bogus code from octeon_get_clock_rate()
We can run with any simulator clock rate.  Get rid of the code
overriding it to 6MHz.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Patchwork: http://patchwork.linux-mips.org/patch/1669/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-29 19:08:39 +01:00
David Daney 54954a6d6b MIPS: Octeon: Scale Octeon2 clocks in octeon_init_cvmcount()
The per-CPU clocks are synchronized from IPD_CLK_COUNT, on cn63XX it must
be scaled by the clock frequency ratio.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Patchwork: http://patchwork.linux-mips.org/patch/1667/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-29 19:08:38 +01:00
David Daney f92a6b0875 MIPS: Octeon: Enable Read Inhibit / eXecute Inhibit on Octeon II.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Patchwork: http://patchwork.linux-mips.org/patch/1666/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-29 19:08:38 +01:00
David Daney 0e56b3852b MIPS: Octeon: Probe for Octeon II CPUs.
The OCTEON II ISA extends the original OCTEON ISA, so give it its own
__elf_platform string so optimized libraries can be selected in
userspace.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Patchwork: http://patchwork.linux-mips.org/patch/1665/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-29 19:08:37 +01:00
David Daney f8bf7e688c MIPS: Octeon: Handle Octeon II caches.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Patchwork: http://patchwork.linux-mips.org/patch/1664/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-29 19:08:36 +01:00
David Daney 1584d7f2d5 MIPS: Add identifiers for Octeon II CPUs.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Patchwork: http://patchwork.linux-mips.org/patch/1662/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-29 19:08:35 +01:00
David Daney b8db85b5b5 MIPS: Octeon: Update L2 Cache code for CN63XX
The CN63XX has a different L2 cache architecture.  Update the helper
functions to reflect this.

Some joining of split lines was also done to improve readability, as
well as reformatting of comments.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Patchwork: http://patchwork.linux-mips.org/patch/1663/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-29 19:08:35 +01:00
David Daney a70b13a9f0 MIPS: Octeon: Add cn63XX to Octeon chip detection macros.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Patchwork: http://patchwork.linux-mips.org/patch/1661/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-29 19:08:34 +01:00
David Daney aa32a955ae MIPS: Octeon: Update register definitions for CN63XX chips
The CN63XX is a new 6-CPU SOC based on the new OCTEON II CPU cores.

Join some lines back together.  This makes some of them exceed 80
columns, but they are uninteresting and this unclutters things.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Patchwork: http://patchwork.linux-mips.org/patch/1668/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-29 19:08:33 +01:00
David Daney b93b2abce4 MIPS: Octeon: Rewrite DMA mapping functions.
All Octeon chips can support more than 4GB of RAM.  Also due to how Octeon
PCI is setup, even some configurations with less than 4GB of RAM will have
portions that are not accessible from 32-bit devices.

Enable the swiotlb code to handle the cases where a device cannot directly
do DMA.  This is a complete rewrite of the Octeon DMA mapping code.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Patchwork: http://patchwork.linux-mips.org/patch/1639/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-29 19:08:32 +01:00
David Daney ee71b7d2f8 MIPS: Add a platform hook for swiotlb setup.
This allows platforms that are using the swiotlb to initialize it.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Patchwork: http://patchwork.linux-mips.org/patch/1638/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-29 19:08:32 +01:00
David Daney 48e1fd5a81 MIPS: Convert DMA to use dma-mapping-common.h
Use asm-generic/dma-mapping-common.h to handle all DMA mapping operations
and establish a default get_dma_ops() that forwards all operations to the
existing code.

Augment dev_archdata to carry a pointer to the struct dma_map_ops, allowing
DMA operations to be overridden on a per device basis.  Currently this is
never filled in, so the default dma_map_ops are used.  A follow-on patch
sets this for Octeon PCI devices.

Also initialize the dma_debug system as it is now used if it is configured.

Includes fixes by Kevin Cernekee <cernekee@gmail.com>.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Patchwork: http://patchwork.linux-mips.org/patch/1637/
Patchwork: http://patchwork.linux-mips.org/patch/1678/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-29 19:08:31 +01:00
David Daney 43e4f7ae4b MIPS: ip32, ip27, jazz: Make static functions in dma-coherence.h inline.
Any function defined in a header file should be inline.  This helps us
avoid 'unused' compiler warnings when we include the files in more
places in subsequent patches.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Patchwork: http://patchwork.linux-mips.org/patch/1636/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-29 19:08:30 +01:00
David Daney f00e001e9c MIPS: Octeon: Select ZONE_DMA32
Give us a nice place to allocate coherent DMA memory for 32-bit devices.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Patchwork: http://patchwork.linux-mips.org/patch/1635/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-29 19:08:30 +01:00
David Daney 57575b5c81 MIPS: Octeon: Adjust top of DMA32 zone.
On OCTEON, we reserve the last 256MB of 32-bit PCI address space, mapping
the RAM in this region at a high DMA address.  This makes memory in this
region unavailable for 32-bit DMA.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Patchwork: http://patchwork.linux-mips.org/patch/1634/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-29 19:08:29 +01:00