Commit Graph

4564 Commits

Author SHA1 Message Date
Geert Uytterhoeven 1d0f9e1e1e pinctrl: sh-pfc: Make legacy function GPIO handling less fragile
If there are no function GPIOs, sh_pfc_register_gpiochip() returns early
with a success indicator.  This is fragile, as new code may be added
after the #ifdef block, which won't be executed in case of early return.

Invert the logic, so the code always continues until the end of the
function on success.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/20191113101809.28600-1-geert+renesas@glider.be
2019-12-09 09:43:02 +01:00
Linus Torvalds b22bfea7f1 Merge branch 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull irq updates from Ingo Molnar:
 "Most of the IRQ subsystem changes in this cycle were irq-chip driver
  updates:

   - Qualcomm PDC wakeup interrupt support

   - Layerscape external IRQ support

   - Broadcom bcm7038 PM and wakeup support

   - Ingenic driver cleanup and modernization

   - GICv3 ITS preparation for GICv4.1 updates

   - GICv4 fixes

  There's also the series from Frederic Weisbecker that fixes memory
  ordering bugs for the irq-work logic, whose primary fix is to turn
  work->irq_work.flags into an atomic variable and then convert the
  complex (and buggy) atomic_cmpxchg() loop in irq_work_claim() into a
  much simpler atomic_fetch_or() call.

  There are also various smaller cleanups"

* 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (44 commits)
  pinctrl/sdm845: Add PDC wakeup interrupt map for GPIOs
  pinctrl/msm: Setup GPIO chip in hierarchy
  irqchip/qcom-pdc: Add irqchip set/get state calls
  irqchip/qcom-pdc: Add irqdomain for wakeup capable GPIOs
  irqchip/qcom-pdc: Do not toggle IRQ_ENABLE during mask/unmask
  irqchip/qcom-pdc: Update max PDC interrupts
  of/irq: Document properties for wakeup interrupt parent
  genirq: Introduce irq_chip_get/set_parent_state calls
  irqdomain: Add bus token DOMAIN_BUS_WAKEUP
  genirq: Fix function documentation of __irq_alloc_descs()
  irq_work: Fix IRQ_WORK_BUSY bit clearing
  irqchip/ti-sci-inta: Use ERR_CAST inlined function instead of ERR_PTR(PTR_ERR(...))
  irq_work: Slightly simplify IRQ_WORK_PENDING clearing
  irq_work: Fix irq_work_claim() memory ordering
  irq_work: Convert flags to atomic_t
  irqchip: Ingenic: Add process for more than one irq at the same time.
  irqchip: ingenic: Alloc generic chips from IRQ domain
  irqchip: ingenic: Get virq number from IRQ domain
  irqchip: ingenic: Error out if IRQ domain creation failed
  irqchip: ingenic: Drop redundant irq_suspend / irq_resume functions
  ...
2019-12-03 09:29:50 -08:00
Rahul Tanwar 6d29032c2c pinctrl: Fix warning by adding missing MODULE_LICENSE
Fix below build warning

   WARNING: modpost: missing MODULE_LICENSE() in
   drivers/pinctrl/pinctrl-equilibrium.o

Introduced by commit

   1948d5c51d ("pinctrl: Add pinmux & GPIO controller driver for a new SoC")

by adding missing MODULE_LICENSE.

Signed-off-by: Rahul Tanwar <rahul.tanwar@linux.intel.com>
Link: https://lore.kernel.org/r/20191128080832.13529-2-rahul.tanwar@linux.intel.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-11-28 09:12:43 +01:00
Linus Torvalds dc5fa46568 This is the bulk of pin control changes for the v5.5 kernel
series:
 
 Core changes:
 
 - Avoid taking direct references to device tree-supplied
   device names: these may changed at runtime under certain
   circumstances to kstrdup them.
 
 GPIO related:
 
 - Work is ongoing to move to passing the irqchip along as a
   templated struct gpio_irq_chip when adding a standard
   gpiolib-based irqchip to a GPIO controller, a few patches
   in this cycle switches a few pin control drivers over to
   using this method.
 
 New hardware support:
 
 - Intel Lightning Mountain SoC pin controller and GPIO
   support, a first Intel platform to use device tree rather
   than ACPI to configure the system. News reports says that
   this SoC is a network processor.
 
 - Qualcomm MSM8976 and MSM8956
 
 - Qualcomm PMIC GPIO now also supports PM6150 and PM6150L
 
 - Qualcomm SPMI MPP and SPMI GPIO for PM8950 and PMI8950
 
 - Rockchip RK3308
 
 - Renesas R8A77961
 
 - Allwinner Meson-A1
 
 Driver improvements:
 
 - get_multiple and set_multiple support for the AT91-PIO4 driver.
 
 - Convert Qualcomm SSBI GPIO to use the hierarchical IRQ helpers
   in the GPIOlib irqchip.
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Merge tag 'pinctrl-v5.5-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij:
 "This is the bulk of pin control changes for v5.5.

  It is pretty much business as usual, the most interesting thing I
  think is the pin controller for a new Intel chip called Lightning
  Mountain, which is according to news reports some kind of embedded
  network processor and what is surprising about it is that Intel have
  decided to use device tree to describe the system rather than ACPI
  that they have traditionally favored.

  Core changes:

   - Avoid taking direct references to device tree-supplied device
     names: these may changed at runtime under certain circumstances to
     kstrdup them.

  GPIO related:

   - Work is ongoing to move to passing the irqchip along as a templated
     struct gpio_irq_chip when adding a standard gpiolib-based irqchip
     to a GPIO controller, a few patches in this cycle switches a few
     pin control drivers over to using this method.

  New hardware support:

   - Intel Lightning Mountain SoC pin controller and GPIO support, a
     first Intel platform to use device tree rather than ACPI to
     configure the system. News reports says that this SoC is a network
     processor.

   - Qualcomm MSM8976 and MSM8956

   - Qualcomm PMIC GPIO now also supports PM6150 and PM6150L

   - Qualcomm SPMI MPP and SPMI GPIO for PM8950 and PMI8950

   - Rockchip RK3308

   - Renesas R8A77961

   - Allwinner Meson-A1

  Driver improvements:

   - get_multiple and set_multiple support for the AT91-PIO4 driver.

   - Convert Qualcomm SSBI GPIO to use the hierarchical IRQ helpers in
     the GPIOlib irqchip"

* tag 'pinctrl-v5.5-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (93 commits)
  pinctrl: ingenic: Add OTG VBUS pin for the JZ4770
  pinctrl: ingenic: Handle PIN_CONFIG_OUTPUT config
  pinctrl: Fix Kconfig indentation
  pinctrl: lewisburg: Update pin list according to v1.1v6
  MAINTAINERS: Replace my email by one @kernel.org
  pinctrl: armada-37xx: Fix irq mask access in armada_37xx_irq_set_type()
  dt-bindings: pinctrl: intel: Add for new SoC
  pinctrl: Add pinmux & GPIO controller driver for a new SoC
  pinctrl: rza1: remove unnecessary static inline function
  pinctrl: meson: add pinctrl driver support for Meson-A1 SoC
  pinctrl: meson: add a new callback for SoCs fixup
  pinctrl: nomadik: db8500: Add mc0_a_2 pin group without direction control
  dt-bindings: pinctrl: Convert generic pin mux and config properties to schema
  pinctrl: cherryview: Missed type change to unsigned int
  pinctrl: intel: Missed type change to unsigned int
  pinctrl: use devm_platform_ioremap_resource() to simplify code
  pinctrl: just return if no valid maps
  dt-bindings: pinctrl: qcom-pmic-mpp: Add support for PM/PMI8950
  pinctrl: qcom: spmi-mpp: Add PM/PMI8950 compatible strings
  dt-bindings: pinctrl: qcom-pmic-gpio: Add support for PM/PMI8950
  ...
2019-11-27 10:00:33 -08:00
Paul Cercueil ae75b53e08 pinctrl: ingenic: Add OTG VBUS pin for the JZ4770
Add pin mux configuration for the OTG VBUS pin of the JZ4770.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20191119155211.102527-2-paul@crapouillou.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-11-21 15:10:36 +01:00
Paul Cercueil 7009d046a6 pinctrl: ingenic: Handle PIN_CONFIG_OUTPUT config
This makes the driver support the 'output-low' and 'output-high'
devicetree properties in gpio-hog sub-nodes.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20191119155211.102527-1-paul@crapouillou.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-11-21 15:09:47 +01:00
Krzysztof Kozlowski 2635adb48b pinctrl: Fix Kconfig indentation
Adjust indentation from spaces to tab (+optional two spaces) as in
coding style with command like:
	$ sed -e 's/^        /\t/' -i */Kconfig

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>

Link: https://lore.kernel.org/r/1574306382-32516-1-git-send-email-krzk@kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-11-21 15:06:07 +01:00
Andy Shevchenko e66ff71fd0 pinctrl: lewisburg: Update pin list according to v1.1v6
Version 1.1v6 of pin list has some changes in pin names for Intel Lewisburg.

Update the driver accordingly.

Note, it reveals the bug in the driver that misses two pins in GPP_L and
has rather two extra ones. That's why the ordering of some groups is changed.

Fixes: e480b74538 ("pinctrl: intel: Add Intel Lewisburg GPIO support")
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20191120133739.54332-1-andriy.shevchenko@linux.intel.com
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-11-21 15:04:16 +01:00
Gregory CLEMENT 04fb02757a pinctrl: armada-37xx: Fix irq mask access in armada_37xx_irq_set_type()
As explained in the following commit a9a1a48336 ("pinctrl:
armada-37xx: Fix gpio interrupt setup") the armada_37xx_irq_set_type()
function can be called before the initialization of the mask field.

That means that we can't use this field in this function and need to
workaround it using hwirq.

Fixes: 30ac0d3b07 ("pinctrl: armada-37xx: Add edge both type gpio irq support")
Cc: stable@vger.kernel.org
Reported-by: Russell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Link: https://lore.kernel.org/r/20191115155752.2562-1-gregory.clement@bootlin.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-11-21 14:54:49 +01:00
Rahul Tanwar 1948d5c51d pinctrl: Add pinmux & GPIO controller driver for a new SoC
Intel Lightning Mountain SoC has a pinmux controller & GPIO controller IP which
controls pin multiplexing & configuration including GPIO functions selection &
GPIO attributes configuration.

This IP is not based on & does not have anything in common with Chassis
specification. The pinctrl drivers under pinctrl/intel/* are all based upon
Chassis spec compliant pinctrl IPs. So this driver doesn't fit & can not use
pinctrl framework under pinctrl/intel/* and it requires a separate new driver.

Add a new GPIO & pin control framework based driver for this IP.

Signed-off-by: Rahul Tanwar <rahul.tanwar@linux.intel.com>
Link: https://lore.kernel.org/r/33e649758b70490f01724a887c490d5008c7656d.1573797249.git.rahul.tanwar@linux.intel.com
Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-11-21 14:47:44 +01:00
Matti Vaittinen 54787d7c14 pinctrl: rza1: remove unnecessary static inline function
Having static inline oneliner does not benefit too much when it is
only called from another oneliner function. Remove some of the
'onion'. This simplifies also the coming usage of the gpiolib
defines. We can do conversion from chip bits to gpiolib direction
defines as last step in the get_direction callback. Drivers can
use chip specific values in driver internal functions and do
conversion only once.

Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20191113071045.GA22110@localhost.localdomain
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-11-21 14:33:33 +01:00
Thomas Gleixner 407e62f52a irqchip updates for Linux 5.5
- Qualcomm PDC wakeup interrupt support
 - Layerscape external IRQ support
 - Broadcom bcm7038 PM and wakeup support
 - Ingenic driver cleanup and modernization
 - GICv3 ITS preparation for GICv4.1 updates
 - GICv4 fixes
 - Various cleanups
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Merge tag 'irqchip-5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/core

Pull irqchip updates from Marc Zyngier:

 - Qualcomm PDC wakeup interrupt support
 - Layerscape external IRQ support
 - Broadcom bcm7038 PM and wakeup support
 - Ingenic driver cleanup and modernization
 - GICv3 ITS preparation for GICv4.1 updates
 - GICv4 fixes
 - Various cleanups
2019-11-20 14:16:34 +01:00
Qianggui Song dabad1ff85 pinctrl: meson: add pinctrl driver support for Meson-A1 SoC
Meson A1 SoC share the same register layout of pinmux with previous
Meson-G12A, however there is difference for gpio and pin config register
in A1. The main difference is that registers before A1 are grouped by
function while those of A1 are by bank. The new register layout is as
below:

/* first bank */              /* addr */
- P_PADCTRL_GPIOP_I         base + 0x00 << 2
- P_PADCTRL_GPIOP_O         base + 0x01 << 2
- P_PADCTRL_GPIOP_OEN       base + 0x02 << 2
- P_PADCTRL_GPIOP_PULL_EN   base + 0x03 << 2
- P_PADCTRL_GPIOP_PULL_UP   base + 0x04 << 2
- P_PADCTRL_GPIOP_DS        base + 0x05 << 2

/* second bank */
- P_PADCTRL_GPIOB_I         base + 0x10 << 2
- P_PADCTRL_GPIOB_O         base + 0x11 << 2
- P_PADCTRL_GPIOB_OEN       base + 0x12 << 2
- P_PADCTRL_GPIOB_PULL_EN   base + 0x13 << 2
- P_PADCTRL_GPIOB_PULL_UP   base + 0x14 << 2
- P_PADCTRL_GPIOB_DS        base + 0x15 << 2

Each bank contains at least 6 registers to be configured, if one bank
has more than 16 gpios, an extra P_PADCTRL_GPIO[X]_DS_EXT is included.
Between two adjacent P_PADCTRL_GPIO[X]_I, there is an offset 0x10, that
is to say, for third bank, the offsets will be 0x20,0x21,0x22,0x23,0x24
,0x25 according to above register layout. For previous chips, registers
are grouped according to their functions while registers of A1 are
according to bank.Also note that there is no AO bank any more in A1.

Current Meson pinctrl driver can cover such change by using base address
of GPIO as that of drive-strength. While simply giving reg_ds = reg_pullen
make wrong value to reg_ds for Socs that do not support drive-strength
like AXG.To make things simple, add an extra dt parser function for
a1 and remain the old dt parser function for only reg parsing.

Signed-off-by: Qianggui Song <qianggui.song@amlogic.com>
Link: https://lore.kernel.org/r/1573819429-6937-3-git-send-email-qianggui.song@amlogic.com
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-11-19 15:55:26 +01:00
Qianggui Song fd42296407 pinctrl: meson: add a new callback for SoCs fixup
In meson_pinctrl_parse_dt, it contains two parts: reg parsing and
SoC relative fixup for AO. Several fixups in the same code make it hard
to maintain, so move all fixups to each SoC's callback and make
meson_pinctrl_parse_dt just do the reg parsing, separate these two
parts.Overview of all current Meson SoCs fixup is as below:

+------+--------------------------------------+--------------------------+
|      |                                      |                          |
| SoC  |                EE domain             |        AO domain         |
+------+--------------------------------------+--------------------------+
|m8    | parse regs:                          | parse regs:              |
|m8b   |   gpio,mux,pull,pull-enable(skip ds) |    gpio,mux,pull(skip ds)|
|gxl   | fixup:                               | fixup:                   |
|gxbb  |   no                                 |     pull-enable = pull;  |
|axg   |                                      |                          |
+------+--------------------------------------+--------------------------+
|g12a  | parse regs:                          | parse regs:              |
|sm1   |   gpio,mux,pull,pull-enable,ds       |   gpio,mux,ds            |
|      | fixup:                               | fixup:                   |
|      |   no                                 |   pull = gpio;           |
|      |                                      |   pull-enable = gpio;    |
+------+--------------------------------------+--------------------------+
|a1 or | parse regs:                                                     |
|later |  gpio/mux (without ao domain)                                   |
|SoCs  | fixup:                                                          |
|      |  pull = gpio; pull-enable = gpio; ds = gpio;                    |
+------+-----------------------------------------------------------------+
Since m8-axg share the same ao fixup, make a common function
meson8_aobus_parse_dt_extra to do the job.

Signed-off-by: Qianggui Song <qianggui.song@amlogic.com>
Link: https://lore.kernel.org/r/1573819429-6937-2-git-send-email-qianggui.song@amlogic.com
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-11-19 15:53:58 +01:00
Stephan Gerhold 58afa801ef pinctrl: nomadik: db8500: Add mc0_a_2 pin group without direction control
Some devices do not make use of the CMD0/DAT0/DAT2 direction control
pins of the MMC/SD card 0 interface. In this case we should leave
those pins unconfigured.

A similar case already exists for "mc1_a_1" vs "mc1_a_2"
when the MC1_FBCLK pin is not used.

Add a new "mc0_a_2" pin group which is equal to "mc0_a_1" except
with the MC0_CMDDIR, MC0_DAT0DIR and MC0_DAT2DIR pins removed.

Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20191117205439.239211-1-stephan@gerhold.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-11-19 15:49:22 +01:00
Lina Iyer 585d1183ff pinctrl/sdm845: Add PDC wakeup interrupt map for GPIOs
Add interrupt parents for wakeup capable GPIOs for Qualcomm SDM845 SoC.

Signed-off-by: Lina Iyer <ilina@codeaurora.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/1573855915-9841-10-git-send-email-ilina@codeaurora.org
2019-11-16 10:23:48 +00:00
Lina Iyer e35a6ae0eb pinctrl/msm: Setup GPIO chip in hierarchy
Some GPIOs are marked as wakeup capable and are routed to another
interrupt controller that is an always-domain and can detect interrupts
even when most of the SoC is powered off. The wakeup interrupt
controller wakes up the GIC and replays the interrupt at the GIC.

Setup the TLMM irqchip in hierarchy with the wakeup interrupt controller
and ensure the wakeup GPIOs are handled correctly.

Co-developed-by: Maulik Shah <mkshah@codeaurora.org>

Signed-off-by: Lina Iyer <ilina@codeaurora.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/1573855915-9841-9-git-send-email-ilina@codeaurora.org

----
Changes in v2:
	- Address review comments
	- Fix Co-developed-by tag
Changes in v1:
	- Address minor review comments
	- Remove redundant call to set irq handler
	- Move irq_domain_qcom_handle_wakeup() to this patch
Changes in RFC v2:
	- Rebase on top of GPIO hierarchy support in linux-next
	- Set the chained irq handler for summary line
2019-11-16 10:23:15 +00:00
Linus Walleij 08a96e43e3 intel-pinctrl for v5.5-1
* Intel Tigerlake pin controller support has been added.
 * Miscellaneous fixes to the main and Cherryview drivers.
 * Refactoring of the context restoring in the main driver.
 
 The following is an automated git shortlog grouped by driver:
 
 cherryview:
  -  Missed type change to unsigned int
  -  Allocate IRQ chip dynamic
  -  Fix spelling mistake in the comment
  -  Fix irq_valid_mask calculation
 
 intel:
  -  Missed type change to unsigned int
  -  Add Intel Tiger Lake pin controller support
  -  Use helper to restore register values on ->resume()
  -  Drop level from warning to debug in intel_restore_hostown()
  -  Introduce intel_restore_intmask() helper
  -  Introduce intel_restore_hostown() helper
  -  Introduce intel_restore_padcfg() helper
  -  Avoid potential glitches if pin is in GPIO mode
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Merge tag 'intel-pinctrl-v5.5-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into devel

intel-pinctrl for v5.5-1

* Intel Tigerlake pin controller support has been added.
* Miscellaneous fixes to the main and Cherryview drivers.
* Refactoring of the context restoring in the main driver.

The following is an automated git shortlog grouped by driver:

cherryview:
 -  Missed type change to unsigned int
 -  Allocate IRQ chip dynamic
 -  Fix spelling mistake in the comment
 -  Fix irq_valid_mask calculation

intel:
 -  Missed type change to unsigned int
 -  Add Intel Tiger Lake pin controller support
 -  Use helper to restore register values on ->resume()
 -  Drop level from warning to debug in intel_restore_hostown()
 -  Introduce intel_restore_intmask() helper
 -  Introduce intel_restore_hostown() helper
 -  Introduce intel_restore_padcfg() helper
 -  Avoid potential glitches if pin is in GPIO mode
2019-11-13 23:11:09 +01:00
Linus Walleij 1566a6a30b Linux 5.4-rc5
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Merge tag 'v5.4-rc5' into devel

Linux 5.4-rc5
2019-11-13 23:10:52 +01:00
Andy Shevchenko 8ae93b5ed9 pinctrl: cherryview: Missed type change to unsigned int
We converted 'unsigned' type to be 'unsigned int' in the driver,
but there are couple of leftovers. So, finish the task now.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-11-07 11:12:10 +02:00
Andy Shevchenko 11b389cc05 pinctrl: intel: Missed type change to unsigned int
We converted 'unsigned' type to be 'unsigned int' in the driver,
but there are couple of leftovers. So, finish the task now.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-11-07 11:10:02 +02:00
Amelie Delaunay 63e006c107 pinctrl: stmfx: fix valid_mask init sequence
With stmfx_pinctrl_gpio_init_valid_mask callback, gpio_valid_mask was used
to initialize gpiochip valid_mask for gpiolib. But gpio_valid_mask was not
yet initialized. gpio_valid_mask required gpio-ranges to be registered,
this is the case after gpiochip_add_data call. But init_valid_mask
callback is also called under gpiochip_add_data. gpio_valid_mask
initialization cannot be moved before gpiochip_add_data because
gpio-ranges are not registered.
So, it is not possible to use init_valid_mask callback.
To avoid this issue, get rid of valid_mask and rely on ranges.

Fixes: da9b142ab2 ("pinctrl: stmfx: Use the callback to populate valid_mask")
Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
Link: https://lore.kernel.org/r/20191104100908.10880-1-amelie.delaunay@st.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-11-07 10:06:46 +01:00
Linus Walleij 6fbd92a833 Samsung pinctrl drivers changes for v5.5
Fix several device node refcnt leaks (missing of_node_put()) in several
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Merge tag 'samsung-pinctrl-5.5' of https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung into devel

Samsung pinctrl drivers changes for v5.5

Fix several device node refcnt leaks (missing of_node_put()) in several
drivers.
2019-11-05 15:40:53 +01:00
YueHaibing 4b024225c4 pinctrl: use devm_platform_ioremap_resource() to simplify code
devm_platform_ioremap_resource() internally have platform_get_resource()
and devm_ioremap_resource() in it. So instead of calling them separately
use devm_platform_ioremap_resource() directly.

Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Acked-by: Jesper Nilsson <jesper.nilsson@axis.com>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20191104142654.39256-1-yuehaibing@huawei.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-11-05 15:33:40 +01:00
lijiazi 6e4f3db8df pinctrl: just return if no valid maps
If there is a problem with a pinctrl node of a device,
for example, config child node do not have prop specified in
dt_params, num_maps maybe 0. On this condition, no need remember
this map.

Signed-off-by: lijiazi <lijiazi@xiaomi.com>
Link: https://lore.kernel.org/r/29421e7720443a2454830963186f00583c76ce1e.1572588550.git.lijiazi@xiaomi.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-11-05 11:25:39 +01:00
AngeloGioacchino Del Regno 90dc30f9ba pinctrl: qcom: spmi-mpp: Add PM/PMI8950 compatible strings
PM8950 and PMI8950 have four MPPs and this driver is compatible.

Signed-off-by: AngeloGioacchino Del Regno <kholk11@gmail.com>
Link: https://lore.kernel.org/r/20191031103507.30678-4-kholk11@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-11-05 11:18:30 +01:00
AngeloGioacchino Del Regno ba5b9c857b pinctrl: qcom: spmi-gpio: Add PM/PMI8950 compatibility
The PM8950 features 8 GPIOs with hole in 3 and PMI8950 has
only two; these PMICs are totally compatible with this driver.

Signed-off-by: AngeloGioacchino Del Regno <kholk11@gmail.com>
Link: https://lore.kernel.org/r/20191031103507.30678-2-kholk11@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-11-05 11:17:44 +01:00
Chris Packham 574dce894b pinctrl: bcm: nsp: implement get_direction
The get_direction api is strongly recommended to be implemented. In fact
if it is not implemented gpio-hogs will not get the correct direction.
Add an implementation of get_direction for the nsp-gpio driver.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Link: https://lore.kernel.org/r/20191104001819.2300-3-chris.packham@alliedtelesis.co.nz
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-11-04 16:20:38 +01:00
Chris Packham 8298d18a49 pinctrl: bcm: nsp: use gpiolib infrastructure for interrupts
Use more of the gpiolib infrastructure for handling interrupts. The
root interrupt still needs to be handled manually as it is shared with
other peripherals on the SoC.

This will allow multiple instances of this driver to be supported and
will clean up gracefully on failure thanks to the device managed APIs.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Link: https://lore.kernel.org/r/20191104001819.2300-2-chris.packham@alliedtelesis.co.nz
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-11-04 16:19:44 +01:00
Ben Dooks (Codethink) 10ff58aa3c pinctrl: amd: fix __iomem annotation in amd_gpio_irq_handler()
The regs pointer in amd_gpio_irq_handler() should have __iomem
on it, so add that to fix the following sparse warnings:

drivers/pinctrl/pinctrl-amd.c:555:14: warning: incorrect type in assignment (different address spaces)
drivers/pinctrl/pinctrl-amd.c:555:14:    expected unsigned int [usertype] *regs
drivers/pinctrl/pinctrl-amd.c:555:14:    got void [noderef] <asn:2> *base
drivers/pinctrl/pinctrl-amd.c:563:34: warning: incorrect type in argument 1 (different address spaces)
drivers/pinctrl/pinctrl-amd.c:563:34:    expected void const volatile [noderef] <asn:2> *addr
drivers/pinctrl/pinctrl-amd.c:563:34:    got unsigned int [usertype] *
drivers/pinctrl/pinctrl-amd.c:580:34: warning: incorrect type in argument 1 (different address spaces)
drivers/pinctrl/pinctrl-amd.c:580:34:    expected void const volatile [noderef] <asn:2> *addr
drivers/pinctrl/pinctrl-amd.c:580:34:    got unsigned int [usertype] *
drivers/pinctrl/pinctrl-amd.c:587:25: warning: incorrect type in argument 2 (different address spaces)
drivers/pinctrl/pinctrl-amd.c:587:25:    expected void volatile [noderef] <asn:2> *addr
drivers/pinctrl/pinctrl-amd.c:587:25:    got unsigned int [usertype] *

Signed-off-by: Ben Dooks (Codethink) <ben.dooks@codethink.co.uk>
Link: https://lore.kernel.org/r/20191022151154.5986-1-ben.dooks@codethink.co.uk
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-11-04 16:08:07 +01:00
Rajendra Nayak 81898a44f2 pinctrl: qcom: sc7180: Add missing tile info in SDC_QDSD_PINGROUP/UFS_RESET
The SDC_QDSD_PINGROUP/UFS_RESET macros are missing the .tile info needed to
calculate the right register offsets. Adding them here and also
adjusting the offsets accordingly.

Fixes: f2ae04c45b ("pinctrl: qcom: Add SC7180 pinctrl driver")

Reported-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Link: https://lore.kernel.org/r/20191021141507.24066-1-rnayak@codeaurora.org
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-11-04 16:03:50 +01:00
Codrin Ciubotariu 0b32928528 pinctrl: at91: Enable slewrate by default on SAM9X60
On SAM9X60, slewrate should be enabled on pins with a switching frequency
below 50Mhz. Since most of our pins do not exceed this value, we enable
slewrate by default. Pins with a switching value that exceeds 50Mhz will
have to explicitly disable slewrate.

This patch changes the ABI. However, the slewrate macros are only used
by SAM9X60 and, at this moment, there are no device-tree files available
for this platform.

Suggested-by: Ludovic Desroches <ludovic.desroches@microchip.com>
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
Link: https://lore.kernel.org/r/20191101092031.24896-1-codrin.ciubotariu@microchip.com
Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-11-03 23:34:47 +01:00
Linus Walleij aa5f2af535 pinctrl: sh-pfc: Updates for v5.5 (take two)
- Add support for the new R-Car M3-W+ (r8a77961) SoC,
   - Small fixes and cleanups.
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Merge tag 'sh-pfc-for-v5.5-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel

pinctrl: sh-pfc: Updates for v5.5 (take two)

  - Add support for the new R-Car M3-W+ (r8a77961) SoC,
  - Small fixes and cleanups.
2019-11-03 23:16:40 +01:00
Geert Uytterhoeven 884caadad1 pinctrl: sh-pfc: sh7734: Fix duplicate TCLK1_B
The definitions for bit field [19:18] of the Peripheral Function Select
Register 3 were accidentally copied from bit field [20], leading to
duplicates for the TCLK1_B function, and missing TCLK0, CAN_CLK_B, and
ET0_ETXD4 functions.

Fix this by adding the missing GPIO_FN_CAN_CLK_B and GPIO_FN_ET0_ETXD4
enum values, and correcting the functions.

Reported-by: Ben Dooks <ben.dooks@codethink.co.uk>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20191024131308.16659-1-geert+renesas@glider.be
2019-11-01 13:42:52 +01:00
Geert Uytterhoeven 708c69e9ea pinctrl: sh-pfc: r8a7796: Add R8A77961 PFC support
Add support for the Pin Function Controller in the R-Car M3-W+
(R8A77961) SoC.

R-Car M3-W+ is pin compatible with R-Car M3-W (R8A77960), which allows
for both SoCs to share a driver.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20191023122955.12420-4-geert+renesas@glider.be
2019-11-01 13:42:52 +01:00
Geert Uytterhoeven d15ca3a321 pinctrl: sh-pfc: Rename PINCTRL_PFC_R8A7796 to PINCTRL_PFC_R8A77960
Rename CONFIG_PINCTRL_PFC_R8A7796 for R-Car M3-W (R8A77960) to
CONFIG_PINCTRL_PFC_R8A77960, to avoid confusion with R-Car M3-W+
(R8A77961), which will use CONFIG_PINCTRL_PFC_R8A77961.

Extend the dependency of CONFIG_PINCTRL_PFC_R8A77960 from
CONFIG_ARCH_R8A7796 to CONFIG_ARCH_R8A77960, to relax dependencies for a
future rename of the SoC configuration symbol.

Rename r8a7796_pinmux_info to r8a77960_pinmux_info, as it contains an
r8a77960-based name.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20191023122955.12420-3-geert+renesas@glider.be
2019-11-01 13:42:52 +01:00
Geert Uytterhoeven ad7fe1a1a3 pinctrl: sh-pfc: Do not use platform_get_irq() to count interrupts
As platform_get_irq() now prints an error when the interrupt does not
exist, counting interrupts by looping until failure causes the printing
of scary messages like:

    sh-pfc e6060000.pin-controller: IRQ index 0 not found

Fix this by using the platform_irq_count() helper instead.

Fixes: 7723f4c5ec ("driver core: platform: Add an error message to platform_get_irq*()")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20191016142601.28255-1-geert+renesas@glider.be
2019-11-01 13:42:51 +01:00
Andy Shevchenko c9ccf71fc8 pinctrl: intel: Add Intel Tiger Lake pin controller support
This driver adds pinctrl/GPIO support for Intel Tiger Lake SoC. The
GPIO controller is based on the next generation GPIO hardware but still
compatible with the one supported by the Intel core pinctrl/GPIO driver.

Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-10-30 16:05:18 +02:00
Andy Shevchenko 942c5ea49f pinctrl: intel: Use helper to restore register values on ->resume()
We can restore only values that had been changed and do not spam kernel log
with unnecessary messages. Convert intel_gpio_update_pad_mode() to a helper
function that will be used across few callers.

Suggested-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-10-30 16:05:18 +02:00
Andy Shevchenko 764cfe3351 pinctrl: intel: Drop level from warning to debug in intel_restore_hostown()
Since we didn't get any new reports from users about wrong settings
of pad ownership, there is no point to spam kernel log with it. Thus,
drop level from warning to debug.

Also, modify format to be in align with the rest restore helpers.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-10-30 16:05:18 +02:00
Andy Shevchenko 471dd9a9c7 pinctrl: intel: Introduce intel_restore_intmask() helper
Refactor restoring GPI_IE registers by using an introduced helper.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-10-30 16:05:18 +02:00
Andy Shevchenko 7101e02252 pinctrl: intel: Introduce intel_restore_hostown() helper
Refactor restoring HOSTSW_OWN registers by using an introduced helper.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-10-30 16:05:18 +02:00
Andy Shevchenko f78f152a1a pinctrl: intel: Introduce intel_restore_padcfg() helper
Deduplicate restoring PADCFGx registers by using a common helper.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-10-30 16:05:18 +02:00
Andy Shevchenko e58e177392 pinctrl: cherryview: Allocate IRQ chip dynamic
Keeping the IRQ chip definition static shares it with multiple instances
of the GPIO chip in the system. This is bad and now we get this warning
from GPIO library:

"detected irqchip that is shared with multiple gpiochips: please fix the driver."

Hence, move the IRQ chip definition from being driver static into the struct
intel_pinctrl. So a unique IRQ chip is used for each GPIO chip instance.

This patch is heavily based on the attachment to the bug by Christoph Marz.

BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=202543
Fixes: 6e08d6bbeb ("pinctrl: Add Intel Cherryview/Braswell pin controller support")
Depends-on: 83b9dc1131 ("pinctrl: cherryview: Associate IRQ descriptors to irqdomain")
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-10-30 16:05:18 +02:00
Andy Shevchenko 17d49c6258 pinctrl: cherryview: Fix spelling mistake in the comment
One spelling mistake is being fixed: benerate -> generate.
It is a complimentary fix to the commit 505485a83c ("pinctrl:
cherryview fixed typo in comment").

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-10-30 16:05:18 +02:00
Hans de Goede 3739898576 pinctrl: cherryview: Fix irq_valid_mask calculation
Commit 03c4749dd6 ("gpio / ACPI: Drop unnecessary ACPI GPIO to Linux
GPIO translation") has made the cherryview gpio numbers sparse, to get
a 1:1 mapping between ACPI pin numbers and gpio numbers in Linux.

This has greatly simplified things, but the code setting the
irq_valid_mask was not updated for this, so the valid mask is still in
the old "compressed" numbering with the gaps in the pin numbers skipped,
which is wrong as irq_valid_mask needs to be expressed in gpio numbers.

This results in the following error on devices using pin 24 (0x0018) on
the north GPIO controller as an ACPI event source:

[    0.422452] cherryview-pinctrl INT33FF:01: Failed to translate GPIO to IRQ

This has been reported (by email) to be happening on a Caterpillar CAT T20
tablet and I've reproduced this myself on a Medion Akoya e2215t 2-in-1.

This commit uses the pin number instead of the compressed index into
community->pins to clear the correct bits in irq_valid_mask for GPIOs
using GPEs for interrupts, fixing these errors and in case of the
Medion Akoya e2215t also fixing the LID switch not working.

Cc: stable@vger.kernel.org
Fixes: 03c4749dd6 ("gpio / ACPI: Drop unnecessary ACPI GPIO to Linux GPIO translation")
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-10-30 16:05:18 +02:00
Andy Shevchenko 4973ddc842 pinctrl: intel: Avoid potential glitches if pin is in GPIO mode
When consumer requests a pin, in order to be on the safest side,
we switch it first to GPIO mode followed by immediate transition
to the input state. Due to posted writes it's luckily to be a single
I/O transaction.

However, if firmware or boot loader already configures the pin
to the GPIO mode, user expects no glitches for the requested pin.
We may check if the pin is pre-configured and leave it as is
till the actual consumer toggles its state to avoid glitches.

Fixes: 7981c0015a ("pinctrl: intel: Add Intel Sunrisepoint pin controller and GPIO support")
Depends-on: f5a26acf01 ("pinctrl: intel: Initialize GPIO properly when used through irqchip")
Cc: stable@vger.kernel.org
Cc: fei.yang@intel.com
Reported-by: Oliver Barta <oliver.barta@aptiv.com>
Reported-by: Malin Jonsson <malin.jonsson@ericsson.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-10-30 16:05:18 +02:00
Linus Walleij 451a59bd1f intel-pinctrl fixes for v5.4 part 2
A couple more fixes for Intel pinctrl drivers:
 
   - Try to avoid glitches when pin is in GPIO mode
   - Fix cherryview irq_valid_mask calculation
   - Allocate cherryview IRQ chip dynamically to avoid triggering warning
     from GPIO core
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Merge tag 'intel-pinctrl-fixes-v5.4-2' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into fixes

intel-pinctrl fixes for v5.4 part 2

A couple more fixes for Intel pinctrl drivers:

  - Try to avoid glitches when pin is in GPIO mode
  - Fix cherryview irq_valid_mask calculation
  - Allocate cherryview IRQ chip dynamically to avoid triggering warning
    from GPIO core
2019-10-30 10:32:55 +01:00
Andy Shevchenko 67d33aecd0 pinctrl: cherryview: Allocate IRQ chip dynamic
Keeping the IRQ chip definition static shares it with multiple instances
of the GPIO chip in the system. This is bad and now we get this warning
from GPIO library:

"detected irqchip that is shared with multiple gpiochips: please fix the driver."

Hence, move the IRQ chip definition from being driver static into the struct
intel_pinctrl. So a unique IRQ chip is used for each GPIO chip instance.

This patch is heavily based on the attachment to the bug by Christoph Marz.

BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=202543
Fixes: 6e08d6bbeb ("pinctrl: Add Intel Cherryview/Braswell pin controller support")
Depends-on: 83b9dc1131 ("pinctrl: cherryview: Associate IRQ descriptors to irqdomain")
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-10-25 12:54:10 +03:00
Linus Walleij 66ee197360 pinctrl: sh-pfc: Updates for v5.5
- Add support for the new RZ/G2N (r8a774b1) SoC,
   - Small fixes and cleanups.
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Merge tag 'sh-pfc-for-v5.5-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel

pinctrl: sh-pfc: Updates for v5.5

  - Add support for the new RZ/G2N (r8a774b1) SoC,
  - Small fixes and cleanups.
2019-10-25 08:21:05 +02:00
YueHaibing fa679767ad pinctrl: mvebu: use devm_platform_ioremap_resource() to simplify code
Use devm_platform_ioremap_resource() to simplify the code a bit.
This is detected by coccinelle.

Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Link: https://lore.kernel.org/r/20191016141217.21520-1-yuehaibing@huawei.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-10-24 14:04:13 +02:00
YueHaibing 6571317713 pinctrl: mediatek: use devm_platform_ioremap_resource() to simplify code
Use devm_platform_ioremap_resource() to simplify the code a bit.
This is detected by coccinelle.

Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Link: https://lore.kernel.org/r/20191016141053.23740-1-yuehaibing@huawei.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-10-24 14:03:27 +02:00
Hans de Goede 63bdef6cd6 pinctrl: cherryview: Fix irq_valid_mask calculation
Commit 03c4749dd6 ("gpio / ACPI: Drop unnecessary ACPI GPIO to Linux
GPIO translation") has made the cherryview gpio numbers sparse, to get
a 1:1 mapping between ACPI pin numbers and gpio numbers in Linux.

This has greatly simplified things, but the code setting the
irq_valid_mask was not updated for this, so the valid mask is still in
the old "compressed" numbering with the gaps in the pin numbers skipped,
which is wrong as irq_valid_mask needs to be expressed in gpio numbers.

This results in the following error on devices using pin 24 (0x0018) on
the north GPIO controller as an ACPI event source:

[    0.422452] cherryview-pinctrl INT33FF:01: Failed to translate GPIO to IRQ

This has been reported (by email) to be happening on a Caterpillar CAT T20
tablet and I've reproduced this myself on a Medion Akoya e2215t 2-in-1.

This commit uses the pin number instead of the compressed index into
community->pins to clear the correct bits in irq_valid_mask for GPIOs
using GPEs for interrupts, fixing these errors and in case of the
Medion Akoya e2215t also fixing the LID switch not working.

Cc: stable@vger.kernel.org
Fixes: 03c4749dd6 ("gpio / ACPI: Drop unnecessary ACPI GPIO to Linux GPIO translation")
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-10-21 16:57:47 +03:00
Andy Shevchenko 29c2c6aa32 pinctrl: intel: Avoid potential glitches if pin is in GPIO mode
When consumer requests a pin, in order to be on the safest side,
we switch it first to GPIO mode followed by immediate transition
to the input state. Due to posted writes it's luckily to be a single
I/O transaction.

However, if firmware or boot loader already configures the pin
to the GPIO mode, user expects no glitches for the requested pin.
We may check if the pin is pre-configured and leave it as is
till the actual consumer toggles its state to avoid glitches.

Fixes: 7981c0015a ("pinctrl: intel: Add Intel Sunrisepoint pin controller and GPIO support")
Depends-on: f5a26acf01 ("pinctrl: intel: Initialize GPIO properly when used through irqchip")
Cc: stable@vger.kernel.org
Cc: fei.yang@intel.com
Reported-by: Oliver Barta <oliver.barta@aptiv.com>
Reported-by: Malin Jonsson <malin.jonsson@ericsson.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-10-21 15:41:19 +03:00
Bruce Chen e543b3f5bb pinctrl: sprd: Add CM4 sleep mode support
For the new Spreadtrum pin controller, it expands 6bits to describe the
pin sleep mode with adding one CM4_SLEEP mode, which means the pin sleep
related configuration will be loaded automatically by hardware when the
CM4 system goes into deep sleep mode.

Signed-off-by: Bruce Chen <bruce.chen@unisoc.com>
Signed-off-by: Baolin Wang <baolin.wang@linaro.org>
Link: https://lore.kernel.org/r/8ae52263b0625c416461821c457e6789b67170b6.1571228451.git.baolin.wang@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-10-16 16:01:24 +02:00
Johnny Huang d6e7a1a511 pinctrl: aspeed-g6: Rename SD3 to EMMC and rework pin groups
AST2600 EMMC support 3 types DAT bus sizes (1, 4 and 8-bit),
corresponding to 3 groups: EMMCG1, EMMCG4 and EMMCG8

Fixes: 58dc52ad00a0 ("pinctrl: aspeed: Add AST2600 pinmux support")
Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com>
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20191008044153.12734-8-andrew@aj.id.au
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-10-16 15:58:27 +02:00
Johnny Huang 1550583432 pinctrl: aspeed-g6: Fix UART13 group pinmux
When UART13G1 is set the pinmux configuration in SCU4B8 for UART13G0
should be cleared.

Fixes: 58dc52ad00a0 ("pinctrl: aspeed: Add AST2600 pinmux support")
Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com>
[AJ: Tweak commit message]
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20191008044153.12734-7-andrew@aj.id.au
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-10-16 15:58:15 +02:00
Andrew Jeffery c136d4c71f pinctrl: aspeed-g6: Make SIG_DESC_CLEAR() behave intuitively
Signal descriptors can represent multi-bit bitfields and so have
explicit "enable" and "disable" states. However many descriptor
instances only describe a single bit, and so the SIG_DESC_SET() macro is
provides an abstraction for the single-bit cases: Its expansion
configures the "enable" state to set the bit and "disable" to clear.

SIG_DESC_CLEAR() was introduced to provide a similar single-bit
abstraction for for descriptors to clear the bit of interest. However
its behaviour was defined as the literal inverse of SIG_DESC_SET() - the
impact is the bit of interest is set in the disable path. This behaviour
isn't intuitive and doesn't align with how we want to use the macro in
practice, so make it clear the bit for both the enable and disable
paths.

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20191008044153.12734-6-andrew@aj.id.au
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-10-16 15:58:09 +02:00
Johnny Huang 9979346f55 pinctrl: aspeed-g6: Fix I3C3/I3C4 pinmux configuration
The documentation to configure I3C3/FSI1 and I3C4/FSI2 was initially
unclear.

Fixes: 58dc52ad00a0 ("pinctrl: aspeed: Add AST2600 pinmux support")
Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com>
[AJ: Tweak commit message, resolve rebase conflicts]
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20191008044153.12734-5-andrew@aj.id.au
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-10-16 15:57:49 +02:00
Andrew Jeffery b178f91f44 pinctrl: aspeed-g6: Fix I2C14 SDA description
The I2C function the pin participated in was incorrectly named SDA14
which lead to a failure to mux:

[    6.884344] No function I2C14 found on pin 7 (7). Found signal(s) MACLINK4, SDA14, GPIOA7 for function(s) MACLINK4, SDA14, GPIOA7

Fixes: 58dc52ad00a0 ("pinctrl: aspeed: Add AST2600 pinmux support")
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20191008044153.12734-4-andrew@aj.id.au
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-10-16 15:57:42 +02:00
Andrew Jeffery 377dfcdcc0 pinctrl: aspeed-g6: Sort pins for sanity
Some pins crept in that weren't ordered in the list.

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20191008044153.12734-3-andrew@aj.id.au
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-10-16 15:57:25 +02:00
Linus Walleij 22406b3efc pinctrl: nomadik: Simplify interrupt handler
The inner interrupt handler was for the latent IRQ handling,
and that will never be used, inline the unnecessary function.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20191014111154.9731-3-linus.walleij@linaro.org
2019-10-16 15:56:19 +02:00
Linus Walleij 2da7852e54 pinctrl: nomadik: Pass irqchip when adding gpiochip
We need to convert all old gpio irqchips to pass the irqchip
setup along when adding the gpio_chip. For more info see
drivers/gpio/TODO.

For chained irqchips this is a pretty straight-forward
conversion.

Cc: Thierry Reding <thierry.reding@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20191014111154.9731-2-linus.walleij@linaro.org
2019-10-16 15:56:19 +02:00
Linus Walleij b95e0bd23e pinctrl: nomadik: Drop support for latent IRQ
The latent IRQs are IRQs that have occurred when the system
was down in deep sleep and the GPIO block was powered off.
The PRCMU (power reset and control unit) knows which GPIO
line offset fired an IRQ to wake the system up (if so
desired) and this second IRQ was used to replay the action
when the system came back online after suspend().

This is now known to be the wrong approach to solve this
problem: in a patch series Lina Iyer has suggested to
instead make it possible to model the IRQs as hierarchical
with double parents.

Also the current device trees do not contain the right
information to make this code work, the latent IRQ is not
specified nowadays giving noise like this in the console:

[    0.612168] gpio 8012e000.gpio: IRQ index 1 not found
[    0.622523] gpio 8012e080.gpio: IRQ index 1 not found

Let's delete the latent IRQ code and reimplement it properly
when we need it.

Cc: Ulf Hansson <ulf.hansson@linaro.org>
Cc: Lina Iyer <ilina@codeaurora.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20191014111154.9731-1-linus.walleij@linaro.org
2019-10-16 15:56:19 +02:00
Jianqun Xu 7825aeb7b2 pinctrl: rockchip: add rk3308 SoC support
This patch do support pinctrl for RK3308 SoCs.

Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Link: https://lore.kernel.org/r/20191015091708.7934-3-jay.xu@rock-chips.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-10-16 15:56:19 +02:00
Baolin Wang f8b05fe41b pinctrl: sprd: Add PIN_CONFIG_BIAS_DISABLE configuration support
Add PIN_CONFIG_BIAS_DISABLE configuration support for Spreadtrum pin
controller.

Signed-off-by: Baolin Wang <baolin.wang@linaro.org>
Link: https://lore.kernel.org/r/66d373ddee61e8be2fcef49aac5e80bd58f14915.1570596606.git.baolin.wang@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-10-16 15:56:19 +02:00
Amelie Delaunay f086d1fe06 pinctrl: stmfx: add irq_request/release_resources callbacks
When an STMFX IO is used as interrupt through the interrupt-controller
binding, the STMFX driver should configure this IO as input. Default
value of STMFX IO direction is input, but if the IO is used as output
before the interrupt use, it will not work without these callbacks.

Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
Link: https://lore.kernel.org/r/20191009091606.17283-1-amelie.delaunay@st.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-10-16 15:56:18 +02:00
AngeloGioacchino Del Regno bcd11493f0 pinctrl: qcom: Add a pinctrl driver for MSM8976 and 8956
Add the pinctrl driver to support pin configuration with the
pinctrl framework on MSM8976, MSM8956, APQ8056, APQ8076.

Signed-off-by: AngeloGioacchino Del Regno <kholk11@gmail.com>
Link: https://lore.kernel.org/r/20191005105936.31216-2-kholk11@gmail.com
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-10-16 15:56:18 +02:00
Linus Walleij 142b876750 pinctrl: ingenic: Pass irqchip when adding gpiochip
We need to convert all old gpio irqchips to pass the irqchip
setup along when adding the gpio_chip. For more info see
drivers/gpio/TODO.

For chained irqchips this is a pretty straight-forward
conversion.

Cc: Thierry Reding <thierry.reding@gmail.com>
Acked-by: Zhou Yanjie <zhouyanjie@zoho.com>
Acked-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20191001133209.17164-1-linus.walleij@linaro.org
2019-10-16 15:56:18 +02:00
Kiran Gunda b587c30a5f dt-bindings: pinctrl: qcom-pmic-gpio: Add support for pm6150/pm6150l
Add support for the PM6150 and PM6150L GPIO support to the
Qualcomm PMIC GPIO binding.

Signed-off-by: Kiran Gunda <kgunda@codeaurora.org>
Link: https://lore.kernel.org/r/1570188039-22122-1-git-send-email-kgunda@codeaurora.org
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-10-16 15:56:07 +02:00
Linus Walleij b475764dda pinctrl: pistachio: Pass irqchip when adding gpiochip
We need to convert all old gpio irqchips to pass the irqchip
setup along when adding the gpio_chip. For more info see
drivers/gpio/TODO.

For chained irqchips this is a pretty straight-forward
conversion.

Cc: Andrew Bresticker <abrestic@chromium.org>
Cc: Thierry Reding <thierry.reding@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: James Hartley <james.hartley@sondrel.com>
Link: https://lore.kernel.org/r/20191001214536.18477-1-linus.walleij@linaro.org
2019-10-16 15:03:59 +02:00
Linus Walleij 2851ef521d pinctrl: armada-37xx: Pass irqchip when adding gpiochip
We need to convert all old gpio irqchips to pass the irqchip
setup along when adding the gpio_chip. For more info see
drivers/gpio/TODO.

For chained irqchips this is a pretty straight-forward
conversion.

Cc: Miquel Raynal <miquel.raynal@bootlin.com>
Cc: Gregory CLEMENT <gregory.clement@bootlin.com>
Cc: Marek Behún <marek.behun@nic.cz>
Cc: Thierry Reding <thierry.reding@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20191002121550.16104-1-linus.walleij@linaro.org
2019-10-16 15:03:59 +02:00
Linus Walleij d874beca9f pinctrl: ocelot: Pass irqchip when adding gpiochip
We need to convert all old gpio irqchips to pass the irqchip
setup along when adding the gpio_chip. For more info see
drivers/gpio/TODO.

For chained irqchips this is a pretty straight-forward
conversion.

Cc: Thierry Reding <thierry.reding@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Link: https://lore.kernel.org/r/20191002114454.9684-1-linus.walleij@linaro.org
2019-10-16 15:03:40 +02:00
Jisheng Zhang 8f1c9dffe3 pinctrl: berlin: as370: fix a typo s/spififib/spdifib
The function should be spdifib, fix this typo.

Fixes: 423ddc580b ("pinctrl: berlin: add the as370 SoC pinctrl driver")
Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
Link: https://lore.kernel.org/r/20191011154321.44f08f9a@xhacker.debian
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-10-16 14:12:55 +02:00
Linus Walleij 3aec5006c2 pinctrl: oxnas: Pass irqchip when adding gpiochip
We need to convert all old gpio irqchips to pass the irqchip
setup along when adding the gpio_chip. For more info see
drivers/gpio/TODO.

For chained irqchips this is a pretty straight-forward
conversion.

Cc: Neil Armstrong <narmstrong@baylibre.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20191002113819.4927-1-linus.walleij@linaro.org
2019-10-16 13:45:27 +02:00
Linus Walleij c77a4de2bb pinctrl: st: Pass irqchip when adding gpiochip
We need to convert all old gpio irqchips to pass the irqchip
setup along when adding the gpio_chip. For more info see
drivers/gpio/TODO.

For chained irqchips this is a pretty straight-forward
conversion: the ST pin controller errors out of adding a
irqchip if the interrupt is invalid or missing or if the
irqmux is not present: the irqchip should not be added
if either of these errors happen, so rewrite the code to
deal with that. Keep the exit path where the gpio_chip
is added no matter what the status of the irq is.

Cc: Benjamin Gaignard <benjamin.gaignard@st.com>
Cc: Amelie Delaunay <amelie.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20191001135147.29416-1-linus.walleij@linaro.org
2019-10-16 13:45:27 +02:00
Linus Walleij 35dea5d746 pinctrl: at91: Pass irqchip when adding gpiochip
We need to convert all old gpio irqchips to pass the irqchip
setup along when adding the gpio_chip. For more info see
drivers/gpio/TODO.

For chained irqchips this is a pretty straight-forward
conversion: at91 is a little bit special since it registers
up to 3 gpio_chips with the same parent handler, but just
passing girq->parent_handler and the parent on the first
of them should cut it.

Cc: Nicolas Ferre <nicolas.ferre@microchip.com>
Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com>
Link: https://lore.kernel.org/r/20191001130645.8350-1-linus.walleij@linaro.org
2019-10-16 13:45:08 +02:00
Keiya Nobuta f846d1e704 pinctrl: sh-pfc: pfc-r8a77965: Fix typo in pinmux macro for SCL3
SCL3 is assigned to GPSR2 bit7 referred by IP1_23_20 macro.

Signed-off-by: Keiya Nobuta <nobuta.keiya@fujitsu.com>
Link: https://lore.kernel.org/r/20191008060619.30237-4-nobuta.keiya@fujitsu.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-10-14 12:11:12 +02:00
Keiya Nobuta 971029d1e0 pinctrl: sh-pfc: pfc-r8a7796: Fix typo in pinmux macro for SCL3
SCL3 is assigned to GPSR2 bit7 referred by IP1_23_20 macro.

Signed-off-by: Keiya Nobuta <nobuta.keiya@fujitsu.com>
Link: https://lore.kernel.org/r/20191008060619.30237-3-nobuta.keiya@fujitsu.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-10-14 12:11:12 +02:00
Keiya Nobuta dcfdaa92a4 pinctrl: sh-pfc: pfc-r8a7795-es1: Fix typo in pinmux macro for SCL3
SCL3 is assigned to GPSR2 bit7 referred by IP1_23_20 macro.

Signed-off-by: Keiya Nobuta <nobuta.keiya@fujitsu.com>
Link: https://lore.kernel.org/r/20191008060619.30237-2-nobuta.keiya@fujitsu.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-10-14 12:11:12 +02:00
Keiya Nobuta 772f9daf33 pinctrl: sh-pfc: pfc-r8a7795: Fix typo in pinmux macro for SCL3
SCL3 is assigned to GPSR2 bit7 referred by IP1_23_20 macro.

Signed-off-by: Keiya Nobuta <nobuta.keiya@fujitsu.com>
Link: https://lore.kernel.org/r/20191008060619.30237-1-nobuta.keiya@fujitsu.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-10-14 12:11:12 +02:00
Keiya Nobuta d30710b8cc pinctrl: sh-pfc: Fix PINMUX_IPSR_PHYS() to set GPSR
This patch allows PINMUX_IPSR_PHYS() to set bits in GPSR.
When assigning function to pin, GPSR should be set to peripheral
function.
For example when using SCL3, GPSR2 bit7 (PWM1_A pin) should be set to
peripheral function.

Signed-off-by: Keiya Nobuta <nobuta.keiya@fujitsu.com>
Link: https://lore.kernel.org/r/20191008060112.29819-1-nobuta.keiya@fujitsu.com
Fixes: 50d1ba1764 ("pinctrl: sh-pfc: Add physical pin multiplexing helper macros")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-10-14 12:11:12 +02:00
Colin Ian King 126c9cb999 pinctrl: rzn1: Make array reg_drive static, makes object smaller
Don't populate the array reg_drive on the stack but instead make it
static. Makes the object code smaller by 32 bytes.

Before:
   text	   data	    bss	    dec	    hex	filename
  31991	  15696	      0	  47687	   ba47	drivers/pinctrl/pinctrl-rzn1.o

After:
   text	   data	    bss	    dec	    hex	filename
  31863	  15792	      0	  47655	   ba27	drivers/pinctrl/pinctrl-rzn1.o

(gcc version 9.2.1, amd64)

Signed-off-by: Colin Ian King <colin.king@canonical.com>
Link: https://lore.kernel.org/r/20191007140559.11840-1-colin.king@canonical.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-10-14 12:11:12 +02:00
Linus Walleij d2fe76ddda intel-pinctrl fixes for v5.4
This includes two fixes for Intel pinctrl drivers:
 
   - Fix warning about shared irqchip
   - Restore Strago DMI workaround for all versions
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Merge tag 'intel-pinctrl-fixes-v5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into fixes

intel-pinctrl fixes for v5.4

This includes two fixes for Intel pinctrl drivers:

  - Fix warning about shared irqchip
  - Restore Strago DMI workaround for all versions
2019-10-11 01:22:57 +02:00
Patrick Williams b835d69530 pinctrl: armada-37xx: swap polarity on LED group
The configuration registers for the LED group have inverted
polarity, which puts the GPIO into open-drain state when used in
GPIO mode.  Switch to '0' for GPIO and '1' for LED modes.

Fixes: 87466ccd94 ("pinctrl: armada-37xx: Add pin controller support for Armada 37xx")
Signed-off-by: Patrick Williams <alpawi@amazon.com>
Cc: <stable@vger.kernel.org>
Link: https://lore.kernel.org/r/20191001155154.99710-1-alpawi@amazon.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-10-09 10:00:58 +02:00
Chris Brandt 930d3a4907 pinctrl: rza2: Fix gpio name typos
Fix apparent copy/paste errors that were overlooked in the original driver.
  "P0_4" -> "PF_4"
  "P0_3" -> "PG_3"

Fixes: b59d0e7827 ("pinctrl: Add RZ/A2 pin and gpio controller")
Cc: <stable@vger.kernel.org>
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Link: https://lore.kernel.org/r/20190930145804.30497-1-chris.brandt@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-10-07 14:33:03 +02:00
Amelie Delaunay 2fd215b8fd pinctrl: stmfx: fix null pointer on remove
dev_get_platdata(&pdev->dev) returns a pointer on struct stmfx_pinctrl,
not on struct stmfx (platform_set_drvdata(pdev, pctl); in probe).
Pointer on struct stmfx is stored in driver data of pdev parent (in probe:
struct stmfx *stmfx = dev_get_drvdata(pdev->dev.parent);).

Fixes: 1490d9f841 ("pinctrl: Add STMFX GPIO expander Pinctrl/GPIO driver")
Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
Link: https://lore.kernel.org/r/20191004122342.22018-1-amelie.delaunay@st.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-10-05 18:39:09 +02:00
Chris Packham 48659227e0 pinctrl: iproc: allow for error from platform_get_irq()
platform_get_irq() can return an error code. Allow for this when getting
the irq.

Fixes: 6f265e5d4d ("pinctrl: bcm-iproc: Pass irqchip when adding gpiochip")
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Link: https://lore.kernel.org/r/20191003000310.17099-2-chris.packham@alliedtelesis.co.nz
Acked-by: Scott Branden <scott.branden@broadcom.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-10-05 18:36:57 +02:00
Chris Packham 74033d99b6 pinctrl: iproc: use unique name for irq chip
Use the dev_name(dev) for the irqc->name so that we get unique names
when we have multiple instances of this driver.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Link: https://lore.kernel.org/r/20191003000310.17099-3-chris.packham@alliedtelesis.co.nz
Acked-by: Scott Branden <scott.branden@broadcom.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-10-05 18:36:30 +02:00
Dan Carpenter 39b65fbb81 pinctrl: ns2: Fix off by one bugs in ns2_pinmux_enable()
The pinctrl->functions[] array has pinctrl->num_functions elements and
the pinctrl->groups[] array is the same way.  These are set in
ns2_pinmux_probe().  So the > comparisons should be >= so that we don't
read one element beyond the end of the array.

Fixes: b5aa1006e4 ("pinctrl: ns2: add pinmux driver support for Broadcom NS2 SoC")
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Link: https://lore.kernel.org/r/20190926081426.GB2332@mwanda
Acked-by: Scott Branden <scott.branden@broadcom.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-10-05 00:13:25 +02:00
Linus Walleij f876dbff85 pinctrl: bcm-iproc: Use SPDX header
This convert the BCM IPROC driver to use the SPDX header
for indicating GPL v2.0 only licensing.

Cc: Pramod Kumar <pramodku@broadcom.com>
Cc: Ray Jui <rjui@broadcom.com>
Cc: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Scott Branden <scott.branden@broadcom.com>
Link: https://lore.kernel.org/r/20191002130217.4491-1-linus.walleij@linaro.org
2019-10-05 00:09:39 +02:00
Patrick Williams 20504fa1d2 pinctrl: armada-37xx: fix control of pins 32 and up
The 37xx configuration registers are only 32 bits long, so
pins 32-35 spill over into the next register.  The calculation
for the register address was done, but the bitmask was not, so
any configuration to pin 32 or above resulted in a bitmask that
overflowed and performed no action.

Fix the register / offset calculation to also adjust the offset.

Fixes: 5715092a45 ("pinctrl: armada-37xx: Add gpio support")
Signed-off-by: Patrick Williams <alpawi@amazon.com>
Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Cc: <stable@vger.kernel.org>
Link: https://lore.kernel.org/r/20191001154634.96165-1-alpawi@amazon.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-10-04 23:53:23 +02:00
Rasmus Villemoes 037699139e pinctrl: devicetree.c: remove orphan pinctrl_dt_has_hogs()
The helper pinctrl_dt_has_hogs() was introduced in
99e4f67508 (pinctrl: core: Use delayed work for hogs), but the sole
use then got removed shortly after in 950b0d91dc (pinctrl: core: Fix
regression caused by delayed work for hogs).

Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
Link: https://lore.kernel.org/r/20190923142005.5632-1-linux@rasmusvillemoes.dk
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-10-04 23:26:23 +02:00
Thierry Reding 9978339ae4 pinctrl: tegra: xusb: Add note about legacy status
Add a comment about why the call to of_match_node() cannot be replaced
by of_device_get_match_data(). This will hopefully prevent people from
attempting to clean this up in the future.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Link: https://lore.kernel.org/r/20190923095400.GA11084@ulmo
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-10-04 23:20:04 +02:00
Colin Ian King 5ff8aca906 pinctl: ti: iodelay: fix error checking on pinctrl_count_index_with_args call
The call to pinctrl_count_index_with_args checks for a -EINVAL return
however this function calls pinctrl_get_list_and_count and this can
return -ENOENT. Rather than check for a specific error, fix this by
checking for any error return to catch the -ENOENT case.

Addresses-Coverity: ("Improper use of negative")
Fixes: 003910ebc8 ("pinctrl: Introduce TI IOdelay configuration driver")
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Link: https://lore.kernel.org/r/20190920122030.14340-1-colin.king@canonical.com
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-10-04 23:08:47 +02:00
Brian Masney ae436fe810 pinctrl: ssbi-gpio: convert to hierarchical IRQ helpers in gpio core
Now that the GPIO core has support for hierarchical IRQ chips, convert
Qualcomm's ssbi-gpio over to use these new helpers to reduce duplicated
code across drivers.

Signed-off-by: Brian Masney <masneyb@onstation.org>
Link: https://lore.kernel.org/r/20190914111010.24384-1-masneyb@onstation.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-10-03 15:02:40 +02:00
Will Deacon be4c60b563 pinctrl: devicetree: Avoid taking direct reference to device name string
When populating the pinctrl mapping table entries for a device, the
'dev_name' field for each entry is initialised to point directly at the
string returned by 'dev_name()' for the device and subsequently used by
'create_pinctrl()' when looking up the mappings for the device being
probed.

This is unreliable in the presence of calls to 'dev_set_name()', which may
reallocate the device name string leaving the pinctrl mappings with a
dangling reference. This then leads to a use-after-free every time the
name is dereferenced by a device probe:

  | BUG: KASAN: invalid-access in strcmp+0x20/0x64
  | Read of size 1 at addr 13ffffc153494b00 by task modprobe/590
  | Pointer tag: [13], memory tag: [fe]
  |
  | Call trace:
  |  __kasan_report+0x16c/0x1dc
  |  kasan_report+0x10/0x18
  |  check_memory_region
  |  __hwasan_load1_noabort+0x4c/0x54
  |  strcmp+0x20/0x64
  |  create_pinctrl+0x18c/0x7f4
  |  pinctrl_get+0x90/0x114
  |  devm_pinctrl_get+0x44/0x98
  |  pinctrl_bind_pins+0x5c/0x450
  |  really_probe+0x1c8/0x9a4
  |  driver_probe_device+0x120/0x1d8

Follow the example of sysfs, and duplicate the device name string before
stashing it away in the pinctrl mapping entries.

Cc: Linus Walleij <linus.walleij@linaro.org>
Reported-by: Elena Petrova <lenaptr@google.com>
Tested-by: Elena Petrova <lenaptr@google.com>
Signed-off-by: Will Deacon <will@kernel.org>
Link: https://lore.kernel.org/r/20191002124206.22928-1-will@kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-10-03 14:50:16 +02:00
Alexandre Belloni 09107a51b0 pinctrl: at91-pio4: implement .get_multiple and .set_multiple
Implement .get_multiple and .set_multiple to allow reading or setting
multiple pins simultaneously. Pins in the same bank will all be switched at
the same time, improving synchronization and performances.

Keep the driver future proof by allowing its use on 64bits platforms if
they ever appear with this IP and we end up with a mismatch between
ATMEL_PIO_NPINS_PER_BANK and BITS_PER_LONG.

Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com>
Link: https://lore.kernel.org/r/20190918113657.25998-1-alexandre.belloni@bootlin.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-10-03 10:10:20 +02:00
Krzysztof Kozlowski a322b3377f pinctrl: samsung: Fix device node refcount leaks in init code
Several functions use for_each_child_of_node() loop with a break to find
a matching child node.  Although each iteration of
for_each_child_of_node puts the previous node, but early exit from loop
misses it.  This leads to leak of device node.

Cc: <stable@vger.kernel.org>
Fixes: 9a2c1c3b91 ("pinctrl: samsung: Allow grouping multiple pinmux/pinconf nodes")
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2019-10-01 20:22:04 +02:00
Krzysztof Kozlowski 7f028caadf pinctrl: samsung: Fix device node refcount leaks in S3C64xx wakeup controller init
In s3c64xx_eint_eint0_init() the for_each_child_of_node() loop is used
with a break to find a matching child node.  Although each iteration of
for_each_child_of_node puts the previous node, but early exit from loop
misses it.  This leads to leak of device node.

Cc: <stable@vger.kernel.org>
Fixes: 61dd726131 ("pinctrl: Add pinctrl-s3c64xx driver")
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2019-10-01 20:22:04 +02:00
Krzysztof Kozlowski 6fbbcb0508 pinctrl: samsung: Fix device node refcount leaks in S3C24xx wakeup controller init
In s3c24xx_eint_init() the for_each_child_of_node() loop is used with a
break to find a matching child node.  Although each iteration of
for_each_child_of_node puts the previous node, but early exit from loop
misses it.  This leads to leak of device node.

Cc: <stable@vger.kernel.org>
Fixes: af99a75074 ("pinctrl: Add pinctrl-s3c24xx driver")
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2019-10-01 20:22:04 +02:00
Krzysztof Kozlowski 5c7f48dd14 pinctrl: samsung: Fix device node refcount leaks in Exynos wakeup controller init
In exynos_eint_wkup_init() the for_each_child_of_node() loop is used
with a break to find a matching child node.  Although each iteration of
for_each_child_of_node puts the previous node, but early exit from loop
misses it.  This leads to leak of device node.

Cc: <stable@vger.kernel.org>
Fixes: 43b169db18 ("pinctrl: add exynos4210 specific extensions for samsung pinctrl driver")
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2019-10-01 20:22:04 +02:00
Nishka Dasgupta 3d2557ab75 pinctrl: samsung: Add of_node_put() before return in error path
Each iteration of for_each_child_of_node puts the previous node, but in
the case of a return from the middle of the loop, there is no put, thus
causing a memory leak. Hence add an of_node_put before the return of
exynos_eint_wkup_init() error path.
Issue found with Coccinelle.

Signed-off-by: Nishka Dasgupta <nishkadg.linux@gmail.com>
Cc: <stable@vger.kernel.org>
Fixes: 14c255d35b ("pinctrl: exynos: Add irq_chip instance for Exynos7 wakeup interrupts")
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2019-10-01 20:22:04 +02:00
Dmitry Torokhov 260996c30f pinctrl: cherryview: restore Strago DMI workaround for all versions
This is essentially a revert of:

e3f72b749d pinctrl: cherryview: fix Strago DMI workaround
86c5dd6860 pinctrl: cherryview: limit Strago DMI workarounds to version 1.0

because even with 1.1 versions of BIOS there are some pins that are
configured as interrupts but not claimed by any driver, and they
sometimes fire up and result in interrupt storms that cause touchpad
stop functioning and other issues.

Given that we are unlikely to qualify another firmware version for a
while it is better to keep the workaround active on all Strago boards.

Reported-by: Alex Levin <levinale@chromium.org>
Fixes: 86c5dd6860 ("pinctrl: cherryview: limit Strago DMI workarounds to version 1.0")
Cc: stable@vger.kernel.org
Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Tested-by: Alex Levin <levinale@chromium.org>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-10-01 17:36:40 +03:00
Andy Shevchenko 57ff2df1b9 pinctrl: intel: Allocate IRQ chip dynamic
Keeping the IRQ chip definition static shares it with multiple instances of
the GPIO chip in the system. This is bad and now we get this warning from
GPIO library:

"detected irqchip that is shared with multiple gpiochips: please fix the driver."

Hence, move the IRQ chip definition from being driver static into the struct
intel_pinctrl. So a unique IRQ chip is used for each GPIO chip instance.

Fixes: ee1a6ca43d ("pinctrl: intel: Add Intel Broxton pin controller support")
Depends-on: 5ff56b015e ("pinctrl: intel: Disable GPIO pin interrupts in suspend")
Reported-by: Federico Ricchiuto <fed.ricchiuto@gmail.com>
Suggested-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-10-01 17:36:07 +03:00
Biju Das 271ff378a3 pinctrl: sh-pfc: r8a77965: Add R8A774B1 PFC support
Renesas RZ/G2N (r8a774b1) is pin compatible with R-Car M3-N (r8a77965),
however it doesn't have several automotive specific peripherals. Add
a r8a77965 specific pin groups/functions along with common pin
groups/functions for supporting both r8a77965 and r8a774b1 SoC.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Link: https://lore.kernel.org/r/1568881036-4404-9-git-send-email-biju.das@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-10-01 09:52:52 +02:00
Geert Uytterhoeven 7666dfd533 Revert "pinctrl: sh-pfc: r8a77990: Fix MOD_SEL1 bit31 when using SIM0_D"
This reverts commit e167d723e1.

According to the R-Car Gen3 Hardware Manual Errata for Rev 1.00 of Aug
24, 2018, the SEL_SIMCARD_{0,1} definition was to be deleted.  However,
this errata merely fixed an accidental double definition in the Hardware
User's Manual Rev. 1.00.  The real definition is still present in later
revisions of the manual (Rev. 1.50 and Rev. 2.00).

Hence revert the commit to recover the definition.

Based on a patch in the BSP by Takeshi Kihara
<takeshi.kihara.df@renesas.com>.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Link: https://lore.kernel.org/r/20190904121658.2617-4-geert+renesas@glider.be
2019-10-01 09:52:52 +02:00
Geert Uytterhoeven 3672bc7093 Revert "pinctrl: sh-pfc: r8a77990: Fix MOD_SEL1 bit30 when using SSI_SCK2 and SSI_WS2"
This reverts commit e87882eb9b.

According to the R-Car Gen3 Hardware Manual Errata for Rev 1.00 of Aug
24, 2018, the SEL_SSI2_{0,1} definition was to be deleted.  However,
this errata merely fixed an accidental double definition in the Hardware
User's Manual Rev. 1.00.  The real definition is still present in later
revisions of the manual (Rev. 1.50 and Rev. 2.00).

Hence revert the commit to recover the definition.

Based on a patch in the BSP by Takeshi Kihara
<takeshi.kihara.df@renesas.com>.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Link: https://lore.kernel.org/r/20190904121658.2617-3-geert+renesas@glider.be
2019-10-01 09:52:52 +02:00
Takeshi Kihara 05f841d2a9 pinctrl: sh-pfc: r8a77990: Rename AVB_AVTP_{MATCH,CAPTURE} pin functions
The Hardware Manual Errata for Rev. 1.50 of April 10, 2019 renamed IPSR2
register bit[23:20] value H'3 and register bit[27:24] value H'3 from
AVB_AVTP_MATCH_A resp. AVB_AVTP_CAPTURE_A to AVB_AVTP_MATCH resp.
AVB_AVTP_CAPTURE.

Update the R-Car E3 pin control driver to reflect this.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[geert: Reword, reference errata]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Link: https://lore.kernel.org/r/20190904121658.2617-2-geert+renesas@glider.be
2019-10-01 09:52:52 +02:00
Linus Walleij 0074a66c11 pinctrl: sirf/atlas7: Pass irqchip when adding gpiochip
We need to convert all old gpio irqchips to pass the irqchip
setup along when adding the gpio_chip. For more info see
drivers/gpio/TODO.

For chained irqchips this is a pretty straight-forward
conversion.

Cc: Barry Song <baohua@kernel.org>
Cc: Yuping Luo <yuping.luo@csr.com>
Cc: Rongjun Ying <rongjun.ying@csr.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20190913113530.5536-6-linus.walleij@linaro.org
2019-09-30 23:13:08 +02:00
Linus Walleij aead399140 pinctrl: sirf: Pass irqchip when adding gpiochip
We need to convert all old gpio irqchips to pass the irqchip
setup along when adding the gpio_chip. For more info see
drivers/gpio/TODO.

For chained irqchips this is a pretty straight-forward
conversion.

Cc: Barry Song <baohua@kernel.org>
Cc: Yuping Luo <yuping.luo@csr.com>
Cc: Rongjun Ying <rongjun.ying@csr.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20190913113530.5536-5-linus.walleij@linaro.org
2019-09-30 23:13:08 +02:00
Linus Walleij de0221f620 pinctrl: nuvoton: npcm7xx: Pass irqchip when adding gpiochip
We need to convert all old gpio irqchips to pass the irqchip
setup along when adding the gpio_chip. For more info see
drivers/gpio/TODO.

For chained irqchips this is a pretty straight-forward
conversion.

Cc: Tomer Maimon <tmaimon77@gmail.com>
Cc: Kun Yi <kunyi@google.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20190913113530.5536-4-linus.walleij@linaro.org
2019-09-30 23:13:08 +02:00
Linus Walleij face7c04b0 pinctrl: spear/plgpio: Pass irqchip when adding gpiochip
We need to convert all old gpio irqchips to pass the irqchip
setup along when adding the gpio_chip. For more info see
drivers/gpio/TODO.

For chained irqchips this is a pretty straight-forward
conversion.

Cc: Shiraz Hashim <shiraz.linux.kernel@gmail.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Link: https://lore.kernel.org/r/20190913113530.5536-3-linus.walleij@linaro.org
2019-09-30 23:12:43 +02:00
Linus Walleij 835513b0fb pinctrl: pic32: Pass irqchip when adding gpiochip
We need to convert all old gpio irqchips to pass the irqchip
setup along when adding the gpio_chip. For more info see
drivers/gpio/TODO.

For chained irqchips this is a pretty straight-forward
conversion.

Cc: Joshua Henderson <joshua.henderson@microchip.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20190913113530.5536-2-linus.walleij@linaro.org
2019-09-30 23:10:41 +02:00
Linus Walleij ef039827bf pinctrl: coh901: Pass irqchip when adding gpiochip
We need to convert all old gpio irqchips to pass the irqchip
setup along when adding the gpio_chip. For more info see
drivers/gpio/TODO.

For chained irqchips this is a pretty straight-forward
conversion.

Cc: Thierry Reding <thierry.reding@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20190913113530.5536-1-linus.walleij@linaro.org
2019-09-30 23:10:01 +02:00
Linus Torvalds 3c2edc36a7 This is the bulk of pin control changes for the v5.4 kernel
cycle:
 
 Core changes:
 
 - Fix errors in example code in the documentation.
 
 New drivers:
 
 - Add support for JZ4760, JZ4760B, X1000, X1000E and X1500 to
   the Ingenic driver.
 
 - Support Cirrus Logic Madera CS47L92 and CS47L15.
 
 - Support Allwinner Sunxi V3S.
 
 - Support Aspeed 2600 BMC.
 
 - Support Qualcomm SC7180.
 
 - Support Marvell MVEBU CS115.
 
 Driver improvements:
 
 - Clean up a few drivers to use the devm_platform_ioremap_resource()
   helper.
 
 - Pass the irqchip when registering the gpio_chip in some pin
   controllers that are also GPIO controllers.
 
 - Support suspend/resume in the Tegra driver.
 
 - Support pull-up on the Broadcom BCM2711.
 
 - The Intel driver can now request locked pads.
 
 - Fix the UFS reset pin in the Qualcomm SDM845 driver.
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Merge tag 'pinctrl-v5.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij:
 "This is the bulk of pin control changes for the v5.4 kernel cycle:

  Core changes:

   - Fix errors in example code in the documentation.

  New drivers:

   - Add support for JZ4760, JZ4760B, X1000, X1000E and X1500 to the
     Ingenic driver.

   - Support Cirrus Logic Madera CS47L92 and CS47L15.

   - Support Allwinner Sunxi V3S.

   - Support Aspeed 2600 BMC.

   - Support Qualcomm SC7180.

   - Support Marvell MVEBU CS115.

  Driver improvements:

   - Clean up a few drivers to use the devm_platform_ioremap_resource()
     helper.

   - Pass the irqchip when registering the gpio_chip in some pin
     controllers that are also GPIO controllers.

   - Support suspend/resume in the Tegra driver.

   - Support pull-up on the Broadcom BCM2711.

   - The Intel driver can now request locked pads.

   - Fix the UFS reset pin in the Qualcomm SDM845 driver"

* tag 'pinctrl-v5.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (112 commits)
  pinctrl: meson-gxbb: Fix wrong pinning definition for uart_c
  pinctrl: sh-pfc: Unlock on error in sh_pfc_func_set_mux()
  pinctrl: bcm: remove redundant assignment to pointer log
  pinctrl: iproc: Add 'get_direction' support
  pinctrl: iproc-gpio: Handle interrupts for multiple instances
  pinctrl: iproc-gpio: Fix incorrect pinconf configurations
  pinctrl: intel: mark intel_pin_to_gpio __maybe_unused
  pinctrl: qcom: sdm845: Fix UFS_RESET pin
  pinctrl: mvebu: add additional variant for standalone CP115
  pinctrl: mvebu: Add CP110 missing pin functionality
  dt-bindings: cp110: document the new CP115 pinctrl compatible
  pinctrl: bcm2835: Pass irqchip when adding gpiochip
  pinctrl: meson: meson: Add of_node_put() before return
  pinctrl/gpio: Take MUX usage into account
  dt-bindings: pinctrl: qcom-pmic-gpio: Add pm8150l support
  dt-bindings: pinctrl: qcom-pmic-gpio: Add pm8150b support
  dt-bindings: pinctrl: qcom-pmic-gpio: Add pm8150 support
  pinctrl: amd: disable spurious-firing GPIO IRQs
  pinctrl: rza2: Include the appropriate headers
  pinctrl: rza2: Drop driver use of consumer flags
  ...
2019-09-19 14:19:33 -07:00
Linus Torvalds bbfe0d6b8b This is the bulk of changes in the GPIO subsystem for the
v5.4 kernel cycle.
 
 Core changes:
 
 - Support hierarchical GPIO irqchips. We now have three
   consumers that can use this: Intel IXP4xx, ThunderX and
   Qualcomm SPMI GPIO (in the pinctrl subsystem). The support
   code has been long in the making and hashed out so it should
   be easily adaptable for all hierarchical irqchip parents.
   The code only gets compiled in if hierarchical irqchip
   is used at the topmost irq controller at least, as the
   hierarchical irqchip requires strict hierarchy all the
   way up in the system.
 
 - Determine the need for a "valid_mask" for GPIO lines on the
   gpio_chip and conversely for the "valid_mask" for the GPIO
   interrupt chip interrupt lines by looking for a
   .init_valid_mask() callback in the main chip or GPIO interrupt
   chip respectively. Allocate it with bitmap_alloc().
 
 - Isolate the device tree/open firmware GPIO description code
   out in its own file properly.
 
 - Isolate the ACPI GPIO description code out in its own file
   properly.
 
 - Drop a whole lot of #ifdef:s in the main includes: it does
   not hurt to keep the include items around, and we get
   quicker and clearer compile failures if the appropriate
   kernel symbols are not selected for drivers.
 
 New/deleted drivers:
 
 - New driver for Aspeed SGPIO.
 
 - The KS8695 driver is deleted as the platform gets deleted
   from arch/arm in this kernel cycle.
 
 - The Cirrus Logic Madera driver now supports CS47L92 and
   CS47L15.
 
 - The Freescale MPC8xxx now supports LS1028A and LS1088A.
 
 Driver improvements:
 
 - We pass the GPIO irqchip intialization by directly filling
   in the struct instead of using set-up functions (the new
   way) for Intel MID, Lynxpoint, Merrifield, XLP, HLWD, Aspeed,
   ZX, VF610, TQMX86, MT7621, Zynq and EP93xx.
 
 Out-of-band changes:
 
 - Fix a GPIO header inclusion in Unicore - no response from
   maintainer.
 
 - Drop FMC subsystem from MAINTAINERS - was deleted in the
   GPIO tree last cycle so let's mop up the shards.
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Merge tag 'gpio-v5.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio

Pull GPIO updates from Linus Walleij:
 "This is the bulk of changes in the GPIO subsystem for the v5.4 kernel
  cycle.

  Core changes:

   - Support hierarchical GPIO irqchips.

     We now have three consumers that can use this: Intel IXP4xx,
     ThunderX and Qualcomm SPMI GPIO (in the pinctrl subsystem).

     The support code has been long in the making and hashed out so it
     should be easily adaptable for all hierarchical irqchip parents.
     The code only gets compiled in if hierarchical irqchip is used at
     the topmost irq controller at least, as the hierarchical irqchip
     requires strict hierarchy all the way up in the system.

   - Determine the need for a "valid_mask" for GPIO lines on the
     gpio_chip and conversely for the "valid_mask" for the GPIO
     interrupt chip interrupt lines by looking for a .init_valid_mask()
     callback in the main chip or GPIO interrupt chip respectively.
     Allocate it with bitmap_alloc().

   - Isolate the device tree/open firmware GPIO description code out in
     its own file properly.

   - Isolate the ACPI GPIO description code out in its own file
     properly.

   - Drop a whole lot of #ifdef:s in the main includes: it does not hurt
     to keep the include items around, and we get quicker and clearer
     compile failures if the appropriate kernel symbols are not selected
     for drivers.

  New/deleted drivers:

   - New driver for Aspeed SGPIO.

   - The KS8695 driver is deleted as the platform gets deleted from
     arch/arm in this kernel cycle.

   - The Cirrus Logic Madera driver now supports CS47L92 and CS47L15.

   - The Freescale MPC8xxx now supports LS1028A and LS1088A.

  Driver improvements:

   - We pass the GPIO irqchip intialization by directly filling in the
     struct instead of using set-up functions (the new way) for Intel
     MID, Lynxpoint, Merrifield, XLP, HLWD, Aspeed, ZX, VF610, TQMX86,
     MT7621, Zynq and EP93xx.

  Out-of-band changes:

   - Fix a GPIO header inclusion in Unicore - no response from
     maintainer.

   - Drop FMC subsystem from MAINTAINERS - was deleted in the GPIO tree
     last cycle so let's mop up the shards"

* tag 'gpio-v5.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (82 commits)
  gpiolib: of: add a fallback for wlf,reset GPIO name
  gpio: htc-egpio: Remove unused exported htc_egpio_get_wakeup_irq()
  gpio: remove explicit comparison with 0
  gpio: creg-snps: use devm_platform_ioremap_resource() to simplify code
  gpio: devres: Switch to EXPORT_SYMBOL_GPL()
  gpio: of: Switch to EXPORT_SYMBOL_GPL()
  gpio: of: Make of_gpio_simple_xlate() private
  gpio: of: Make of_get_named_gpiod_flags() private
  gpio: aspeed: Add in ast2600 details to Aspeed driver
  gpio: aspeed: Use ngpio property from device tree if available
  gpio: aspeed: Setup irqchip dynamically
  gpio/aspeed: Fix incorrect number of banks
  gpio: aspeed: Update documentation with ast2600 controllers
  gpio: Initialize the irqchip valid_mask with a callback
  gpiolib: acpi: make acpi_can_fallback_to_crs() static
  gpio: Fix further merge errors
  gpio: Fix up merge collision in include file
  gpio: of: Normalize return code variable name
  gpio: gpiolib: Normalize return code variable name
  gpio: ep93xx: Pass irqchip when adding gpiochip
  ...
2019-09-16 14:06:50 -07:00
Otto Meier cb0438e443 pinctrl: meson-gxbb: Fix wrong pinning definition for uart_c
Hi i tried to use the uart_C of the the odroid-c2.

I enabled it in the dts file. During boot it crashed when the
the sdcard slot is addressed.

After long search in the net i found this:

https://forum.odroid.com/viewtopic.php?f=139&t=25371&p=194370&hilit=uart_C#p177856

After changing the pin definitions accordingly erverything works.
Uart_c is functioning and sdcard ist working.

Fixes: 6db0f3a8a0 ("pinctrl: amlogic: gxbb: add more UART pins")
Signed-off-by: Otto Meier <gf435@gmx.net>
Link: https://lore.kernel.org/r/1cc32a18-464d-5531-7a1c-084390e2ecb1@gmx.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-09-13 14:40:41 +02:00
Dan Carpenter a5ea8e9995 pinctrl: sh-pfc: Unlock on error in sh_pfc_func_set_mux()
We need to unlock and enable IRQs before we return on this error path.

Fixes: 8a0cc47ccc ("pinctrl: sh-pfc: Rollback to mux if required when the gpio is freed")
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Link: https://lore.kernel.org/r/20190827093927.GB8443@mwanda
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-09-12 12:59:43 +01:00
Linus Walleij 1aab2f9d39 intel-pinctrl for v5.4 part 2
Just a single fix for build warning introduced in the previous pull.
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Merge tag 'intel-pinctrl-v5.4-2' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into devel

intel-pinctrl for v5.4 part 2

Just a single fix for build warning introduced in the previous pull.
2019-09-12 12:58:18 +01:00
Colin Ian King 26098de168 pinctrl: bcm: remove redundant assignment to pointer log
The pointer log is being initialized with a value that is never read
and is being re-assigned a little later on. The assignment is
redundant and hence can be removed.

Addresses-Coverity: ("Unused value")
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Link: https://lore.kernel.org/r/20190905140919.29283-1-colin.king@canonical.com
Reviewed-by: Ray Jui <ray.jui@broadcom.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-09-12 10:25:53 +01:00
Rayagonda Kokatanur 0351827168 pinctrl: iproc: Add 'get_direction' support
Add 'get_direction' support to the iProc GPIO driver.

Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
Link: https://lore.kernel.org/r/1568178685-30738-1-git-send-email-rayagonda.kokatanur@broadcom.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-09-12 10:25:38 +01:00
Andrew Jeffery c1432423a1 pinctrl: aspeed: Fix spurious mux failures on the AST2500
Commit 674fa8daa8 ("pinctrl: aspeed-g5: Delay acquisition of regmaps")
was determined to be a partial fix to the problem of acquiring the LPC
Host Controller and GFX regmaps: The AST2500 pin controller may need to
fetch syscon regmaps during expression evaluation as well as when
setting mux state. For example, this case is hit by attempting to export
pins exposing the LPC Host Controller as GPIOs.

An optional eval() hook is added to the Aspeed pinmux operation struct
and called from aspeed_sig_expr_eval() if the pointer is set by the
SoC-specific driver. This enables the AST2500 to perform the custom
action of acquiring its regmap dependencies as required.

John Wang tested the fix on an Inspur FP5280G2 machine (AST2500-based)
where the issue was found, and I've booted the fix on Witherspoon
(AST2500) and Palmetto (AST2400) machines, and poked at relevant pins
under QEMU by forcing mux configurations via devmem before exporting
GPIOs to exercise the driver.

Fixes: 7d29ed88ac ("pinctrl: aspeed: Read and write bits in LPC and GFX controllers")
Fixes: 674fa8daa8 ("pinctrl: aspeed-g5: Delay acquisition of regmaps")
Reported-by: John Wang <wangzqbj@inspur.com>
Tested-by: John Wang <wangzqbj@inspur.com>
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>

Link: https://lore.kernel.org/r/20190829071738.2523-1-andrew@aj.id.au
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-09-12 00:08:27 +01:00
Rayagonda Kokatanur 547f073f07 pinctrl: iproc-gpio: Handle interrupts for multiple instances
When multiple instance of iproc-gpio chips are present, a fix up
message[1] is printed during the probe of second and later instances.

This issue is because driver sharing same irq_chip data structure
among multiple instances of driver.

Fix this by allocating irq_chip data structure per instance of
iproc-gpio.

[1] fix up message addressed by this patch
[  7.862208] gpio gpiochip2: (689d0000.gpio): detected irqchip that
   is shared with multiple gpiochips: please fix the driver.

Fixes: 616043d58a ("pinctrl: Rename gpio driver from cygnus to iproc")
Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
Link: https://lore.kernel.org/r/1567054348-19685-3-git-send-email-srinath.mannam@broadcom.com
[Rebased on top of new irq chip set-up code]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-09-11 10:43:04 +01:00
Li Jin 398a1f50e3 pinctrl: iproc-gpio: Fix incorrect pinconf configurations
Fix drive strength for AON/CRMU controller; fix pull-up/down setting
for CCM/CDRU controller.

Fixes: 616043d58a ("pinctrl: Rename gpio driver from cygnus to iproc")
Signed-off-by: Li Jin <li.jin@broadcom.com>
Link: https://lore.kernel.org/r/1567054348-19685-2-git-send-email-srinath.mannam@broadcom.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-09-11 10:33:48 +01:00
Linus Walleij 5fbe5b5883 gpio: Initialize the irqchip valid_mask with a callback
After changing the valid_mask for the struct gpio_chip
to detect the need and presence of a valid mask with the
presence of a .init_valid_mask() callback to fill it in,
we augment the gpio_irq_chip to use the same logic.

Switch all driver using the gpio_irq_chio valid_mask
over to this new method.

This makes sure the valid_mask for the gpio_irq_chip gets
filled in when we add the gpio_chip, which makes it a
little easier to switch over drivers using the old
way of setting up gpio_irq_chip over to the new method
of passing the gpio_irq_chip along with the gpio_chip.
(See drivers/gpio/TODO for details.)

Cc: Joel Stanley <joel@jms.id.au>
Cc: Thierry Reding <treding@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Tested-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Link: https://lore.kernel.org/r/20190904140104.32426-1-linus.walleij@linaro.org
2019-09-11 01:09:37 +01:00
Arnd Bergmann 55dac43747 pinctrl: intel: mark intel_pin_to_gpio __maybe_unused
The intel_pin_to_gpio() function is only called by the
PM support functions and causes a warning when those are disabled:

drivers/pinctrl/intel/pinctrl-intel.c:841:12: error: unused function 'intel_pin_to_gpio' [-Werror,-Wunused-function]

Mark it __maybe_unused to suppress the warning.

Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Chris Chiu <chiu@endlessm.com>
Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-09-09 13:11:42 +03:00
Linus Walleij 151a41014b Linux 5.3-rc7
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Merge tag 'v5.3-rc7' into devel

Linux 5.3-rc7
2019-09-05 11:40:54 +02:00
Stephen Boyd 1fdbc02ce1 pinctrl: qcom: sdm845: Fix UFS_RESET pin
The UFS_RESET pin is the magical pin #150 now, not 153 per the
sdm845_groups array declared in this file. Fix the order of pins so that
UFS_RESET is 150 and the SDC pins follow after.

Fixes: 53a5372ce3 ("pinctrl: qcom: sdm845: Expose ufs_reset as gpio")
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/20190830060227.12792-1-swboyd@chromium.org
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-09-04 15:23:22 +02:00
Linus Walleij bacada1c3f intel-pinctrl for v5.4
A collection of improvements and fixes for Intel pinctrl drivers
 including:
 
   - Converting drivers to use new devm_platform_ioremap_resource()
     helper function.
 
   - Make Interrupt Status (IS) register configurable.
 
   - Allow locked pins to be requested and used as long as they are not
     modified.
 
   - Fix intel_pinctrl_should_save() to translate pin number to GPIO
     number where needed. This fixes Asus X571GT touchpad
     unresponsiveness issue after suspend/resume cycle.
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Merge tag 'intel-pinctrl-v5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into devel

intel-pinctrl for v5.4

A collection of improvements and fixes for Intel pinctrl drivers
including:

  - Converting drivers to use new devm_platform_ioremap_resource()
    helper function.

  - Make Interrupt Status (IS) register configurable.

  - Allow locked pins to be requested and used as long as they are not
    modified.

  - Fix intel_pinctrl_should_save() to translate pin number to GPIO
    number where needed. This fixes Asus X571GT touchpad
    unresponsiveness issue after suspend/resume cycle.
2019-09-04 10:54:26 +02:00
Grzegorz Jaszczyk 501398b753 pinctrl: mvebu: add additional variant for standalone CP115
With CP115 standalone modules, all MPP configuration are
possible. Handle this new possibility thanks to the new
"marvell,cp115-standalone-pinctrl" compatible property.

Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
[<miquel.raynal@bootlin.com>: mention the new compatible in the
commit log]
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/r/20190805101607.29811-4-miquel.raynal@bootlin.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-27 09:49:22 +02:00
Konstantin Porotchkin 26cb47b8f3 pinctrl: mvebu: Add CP110 missing pin functionality
Add missing definition for function 0xe on CP-110 MPP-62.
The pin function is Data Strobe for SDIO interface.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/r/20190805101607.29811-2-miquel.raynal@bootlin.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-27 09:47:47 +02:00
Linus Walleij 73345a18d4 pinctrl: bcm2835: Pass irqchip when adding gpiochip
We need to convert all old gpio irqchips to pass the irqchip
setup along when adding the gpio_chip. For more info see
drivers/gpio/TODO.

For chained irqchips this is a pretty straight-forward
conversion. The BCM2835 has multiple parents so let's
exploit the new facility in the GPIO_IRQCHIP to actually
deal with multiple parents.

Cc: Eric Anholt <eric@anholt.net>
Cc: Thierry Reding <treding@nvidia.com>
[Rebased on changes in the pinctrl tree]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Tested-by: Stefan Wahren <stefan.wahren@i2se.com>
Link: https://lore.kernel.org/r/20190812062729.1892-1-linus.walleij@linaro.org
2019-08-26 13:21:53 +02:00
Linus Walleij 7c772bed43 pinctrl: sh-pfc: Updates for v5.4 (take two)
- Support switching between function and gpio at runtime,
   - Small fixes and cleanups.
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Merge tag 'sh-pfc-for-v5.4-tag2' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel

pinctrl: sh-pfc: Updates for v5.4 (take two)

  - Support switching between function and gpio at runtime,
  - Small fixes and cleanups.
2019-08-23 23:07:04 +02:00
Nishka Dasgupta 2ff110bbe9 pinctrl: meson: meson: Add of_node_put() before return
Each iteration of for_each_child_of_node puts the previous node, but in
the case of a return from the middle of the loop, there is no put, thus
causing a memory leak. Hence add an of_node_put before the return.
Issue found with Coccinelle.

Signed-off-by: Nishka Dasgupta <nishkadg.linux@gmail.com>
Link: https://lore.kernel.org/r/20190815060718.3286-1-nishkadg.linux@gmail.com
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-23 11:48:08 +02:00
Stefan Wahren 472a61e777 pinctrl/gpio: Take MUX usage into account
The user space like gpioinfo only see the GPIO usage but not the
MUX usage (e.g. I2C or SPI usage) of a pin. As a user we want
to know which pin is free/safe to use. So take the MUX usage of
strict pinmux controllers into account to get a more realistic
view for ioctl GPIO_GET_LINEINFO_IOCTL.

Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
Tested-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Ramon Fried <rfried.dev@gmail.com>
Link: https://lore.kernel.org/r/20190814110035.13451-1-ramon.fried@linux.intel.com
Acked-by: Stefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-23 11:09:41 +02:00
Vinod Koul 2dc889a884 dt-bindings: pinctrl: qcom-pmic-gpio: Add pm8150l support
Add support for the PM8150l GPIO support to the Qualcomm PMIC GPIO
binding.

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20190814123512.6017-3-vkoul@kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-23 09:59:55 +02:00
Vinod Koul 9bdacadd16 dt-bindings: pinctrl: qcom-pmic-gpio: Add pm8150b support
Add support for the PM8150b GPIO support to the Qualcomm PMIC GPIO
binding.

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20190814123512.6017-2-vkoul@kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-23 09:59:13 +02:00
Vinod Koul d67070c372 dt-bindings: pinctrl: qcom-pmic-gpio: Add pm8150 support
Add support for the PM8150 GPIO support to the Qualcomm PMIC GPIO
binding.

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20190814123512.6017-1-vkoul@kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-23 09:57:50 +02:00
Daniel Drake d21b8adbd4 pinctrl: amd: disable spurious-firing GPIO IRQs
When cold-booting Asus X434DA, GPIO 7 is found to be already configured
as an interrupt, and the GPIO level is found to be in a state that
causes the interrupt to fire.

As soon as pinctrl-amd probes, this interrupt fires and invokes
amd_gpio_irq_handler(). The IRQ is acked, but no GPIO-IRQ handler was
invoked, so the GPIO level being unchanged just causes another interrupt
to fire again immediately after.

This results in an interrupt storm causing this platform to hang
during boot, right after pinctrl-amd is probed.

Detect this situation and disable the GPIO interrupt when this happens.
This enables the affected platform to boot as normal. GPIO 7 actually is
the I2C touchpad interrupt line, and later on, i2c-multitouch loads and
re-enables this interrupt when it is ready to handle it.

Instead of this approach, I considered disabling all GPIO interrupts at
probe time, however that seems a little risky, and I also confirmed that
Windows does not seem to have this behaviour: the same 41 GPIO IRQs are
enabled under both Linux and Windows, which is a far larger collection
than the GPIOs referenced by the DSDT on this platform.

Signed-off-by: Daniel Drake <drake@endlessm.com>
Link: https://lore.kernel.org/r/20190814090540.7152-1-drake@endlessm.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-23 09:56:03 +02:00
Linus Walleij 0a6864274e pinctrl: rza2: Include the appropriate headers
This driver is implementing a GPIO driver so include
<linux/gpio/driver.h> and not the legacy API <linux/gpio.h>.
When testing it turns out it also relies on implicit
inclusion of <linux/io.h> (readw etc) so make sure to
include that as well.

Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-08-23 09:08:10 +02:00
Linus Walleij 5b1d96e029 pinctrl: rza2: Drop driver use of consumer flags
These flags are for consumers of GPIO lines, not for
drivers.

Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-08-23 09:08:10 +02:00
Nishka Dasgupta ab6366ee88 pinctrl: rza1: Add of_node_put() before return
Each iteration of for_each_child_of_node puts the previous node, but in
the case of a return from the middle of the loop, there is no put, thus
causing a memory leak. Hence add an of_node_put before the return in
three places.
Issue found with Coccinelle.

Signed-off-by: Nishka Dasgupta <nishkadg.linux@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-08-23 09:08:10 +02:00
Linus Walleij df62267dde pinctrl: sh-pfc: Include the right header
This is a GPIO driver, use the appropriate header
<linux/gpio/driver.h> rather than the legacy <linux/gpio.h>
header.

Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-08-23 09:08:10 +02:00
Yoshihiro Shimoda 8a0cc47ccc pinctrl: sh-pfc: Rollback to mux if required when the gpio is freed
Some drivers require switching between function and gpio at run-time.
Allow to roll back from gpio to mux when the gpio is freed.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-08-23 09:08:10 +02:00
Linus Walleij 880e4f93f9 Linux 5.3-rc5
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Merge tag 'v5.3-rc5' into devel

Linux 5.3-rc5
2019-08-21 13:35:16 +02:00
Nishka Dasgupta 19d17d935b pinctrl: st: Add of_node_put() before return
Each iteration of for_each_child_of_node puts the previous node, but in
the case of a return from the middle of the loop, there is no put, thus
causing a memory leak. Hence add an of_node_put before the return in
three places.
Issue found with Coccinelle.

Signed-off-by: Nishka Dasgupta <nishkadg.linux@gmail.com>
Link: https://lore.kernel.org/r/20190815060609.3056-1-nishkadg.linux@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-21 12:04:35 +02:00
Linus Walleij 954fc5d204 pinctrl: st: Include the right header
The ST pinctrl driver wants to provode a gpio_chip but is not
including the header for this, fix the inclusion to use the right
header. <linux/of_gpio.h> has to remain as the driver is calling
of_get_named_gpio().

Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Maxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20190820111135.10701-1-linus.walleij@linaro.org
2019-08-21 09:02:40 +02:00
Nishka Dasgupta 6e28aaab07 pinctrl: rk805: Make structures constant
Static structures rk805_pinctrl_desc and rk805_gpio_chip, of types
gpio_chip and pinctrl_desc respectively, are not used except to be
copied into the fields of a different variable. Hence make
rk805_pinctrl_desc and rk805_gpio_chip both constant to protect them
from unintended modification.
Issue found with Coccinelle.

Signed-off-by: Nishka Dasgupta <nishkadg.linux@gmail.com>
Link: https://lore.kernel.org/r/20190819075757.1753-1-nishkadg.linux@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-21 09:00:16 +02:00
Sowjanya Komatineni a4873accca pinctrl: tegra: Flush pinctrl writes during resume
This patch adds pinctrl register read to flush all the prior pinctrl
writes and then adds barrier for pinctrl register read to complete
during resume to make sure all pinctrl changes are effective.

Acked-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Link: https://lore.kernel.org/r/1565984527-5272-3-git-send-email-skomatineni@nvidia.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-21 09:00:16 +02:00
Sowjanya Komatineni c2cf351eba pinctrl: tegra: Fix write barrier placement in pmx_writel
pmx_writel uses writel which inserts write barrier before the
register write.

This patch has fix to replace writel with writel_relaxed followed
by a readback and memory barrier to ensure write operation is
completed for successful pinctrl change.

Acked-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Link: https://lore.kernel.org/r/1565984527-5272-2-git-send-email-skomatineni@nvidia.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-21 09:00:16 +02:00
Linus Walleij 6f265e5d4d pinctrl: bcm-iproc: Pass irqchip when adding gpiochip
We need to convert all old gpio irqchips to pass the irqchip
setup along when adding the gpio_chip. For more info see
drivers/gpio/TODO.

For chained irqchips this is a pretty straight-forward
conversion.

Cc: Pramod Kumar <pramodku@broadcom.com>
Cc: Ray Jui <rjui@broadcom.com>
Cc: Scott Branden <sbranden@broadcom.com>
Cc: Thierry Reding <treding@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20190812132554.18313-1-linus.walleij@linaro.org
Acked-by: Scott Branden <scott.branden@broadcom.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-21 09:00:16 +02:00
Linus Walleij eb1e8bd6e3 gpio: Use callback presence to determine need of valid_mask
After we switched the two drivers that have .need_valid_mask
set to use the callback for setting up the .valid_mask,
we can just use the presence of the .init_valid_mask()
callback (or the OF reserved ranges, nota bene) to determine
whether to allocate the mask or not and we can drop the
.need_valid_mask field altogether.

Cc: Benjamin Gaignard <benjamin.gaignard@st.com>
Cc: Amelie Delaunay <amelie.delaunay@st.com>
Cc: Stephen Boyd <swboyd@chromium.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20190819093058.10863-1-linus.walleij@linaro.org
2019-08-20 10:42:07 +02:00
Linus Walleij da9b142ab2 pinctrl: stmfx: Use the callback to populate valid_mask
This makes use of the existing callback to populate the
valid mask instead of iteratively setting it up during
probe.

Cc: Benjamin Gaignard <benjamin.gaignard@st.com>
Cc: Amelie Delaunay <amelie.delaunay@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20190819091140.622-1-linus.walleij@linaro.org
2019-08-20 10:42:07 +02:00
Linus Walleij c9fc5aff21 gpio: Pass mask and size with the init_valid_mask()
It is more helpful for drivers to have the affected fields
directly available when we use the callback to set up the
valid mask. Change this and switch over the only user
(MSM) to use the passed parameters. If we do this we can
also move the mask out of publicly visible struct fields.

Cc: Stephen Boyd <swboyd@chromium.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20190819084904.30027-1-linus.walleij@linaro.or
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-20 10:42:07 +02:00
Chris Chiu 6cb0880f08 pinctrl: intel: remap the pin number to gpio offset for irq enabled pin
On Asus X571GT, GPIO 297 is configured as an interrupt and serves
for the touchpad. The touchpad will report input events much less
than expected after S3 suspend/resume, which results in extremely
slow cursor movement. However, the number of interrupts observed
from /proc/interrupts increases much more than expected even no
touching touchpad.

This is due to the value of PADCFG0 of PIN 225 for the interrupt
has been changed from 0x80800102 to 0x80100102. The GPIROUTIOXAPIC
is toggled on which results in the spurious interrupts. The PADCFG0
of PIN 225 is expected to be saved during suspend, but the 297 is
saved instead because the gpiochip_line_is_irq() expect the GPIO
offset but what's really passed to it is PIN number. In this case,
the /sys/kernel/debug/pinctrl/INT3450:00/gpio-ranges shows

288: INT3450:00 GPIOS [436 - 459] PINS [216 - 239]

So gpiochip_line_is_irq() returns true for GPIO offset 297, the
suspend routine spuriously saves the content for PIN 297 which
we expect to save for PIN 225.

This commit maps the PIN number to GPIO offset first in the
intel_pinctrl_should_save() to make sure the values for the
specific PINs can be correctly saved and then restored.

Fixes: c538b94367 ("pinctrl: intel: Only restore pins that are used by the driver")
Signed-off-by: Chris Chiu <chiu@endlessm.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-08-19 12:41:44 +03:00
Andy Shevchenko 1bd231538c pinctrl: intel: Allow to request locked pads
Some firmwares would like to protect pads from being modified by OS
and at the same time provide them to OS as a resource. So, the driver
in such circumstances may request pad and may not change its state.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-08-18 20:57:50 +03:00
Brian Masney 821c76c4c3 qcom: spmi-gpio: convert to hierarchical IRQ helpers in gpio core
Now that the GPIO core has support for hierarchical IRQ chips, convert
Qualcomm's spmi-gpio over to use these new helpers to reduce duplicated
code across drivers.

This change was tested on a LG Nexus 5 (hammerhead) phone.

Signed-off-by: Brian Masney <masneyb@onstation.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20190808123242.5359-3-linus.walleij@linaro.org
2019-08-15 09:44:19 +02:00
Yoshihiro Shimoda b13431ed6e pinctrl: sh-pfc: Remove incomplete flag "cfg->type"
The old commit c58d9c1b26 ("sh-pfc: Implement generic pinconf
support") broke the cfg->type flag to PINMUX_TYPE_FUNCTION because
sh_pfc_pinconf_set() didn't call sh_pfc_reconfig_pin().
Now if we fix the cfg->type condition, it gets worse because:
 - Some drivers might be deferred so that .set_mux() will be called
   multiple times.
 - In such the case, the sh-pfc driver returns -EBUSY even if
   the group is the same, and then that driver fails to probe.

Since the pinctrl subsystem already has such conditions according
to @set_mux and @gpio_request_enable, this patch just remove
the incomplete flag from sh-pfc/pinctrl.c.

Fixes: c58d9c1b26 ("sh-pfc: Implement generic pinconf support")
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-08-12 15:55:26 +02:00
Yoshihiro Shimoda 1d4ba593d0 pinctrl: sh-pfc: Add new flags into struct sh_pfc_pin_config
To clean/modify the code up later, this patch just adds new flags
"mux_set" and "gpio_enabled" into the struct sh_pfc_pin_config.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-08-12 15:55:15 +02:00
Linus Walleij 76837e02a2 pinctrl: sh-pfc: Updates for v5.4
- Add missing of_node_put() calls on RZ/N1,
   - Small cleanups.
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Merge tag 'sh-pfc-for-v5.4-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel

pinctrl: sh-pfc: Updates for v5.4

  - Add missing of_node_put() calls on RZ/N1,
  - Small cleanups.
2019-08-10 10:31:01 +02:00
Nishka Dasgupta bf4b87b0d0 pinctrl: freescale: imx: Add of_node_put() before return
Each iteration of for_each_child_of_node() puts the previous node;
however, in the case of a return from the middle of the loop, there is no
put, thus causing a memory leak. Hence put of_node_put() statements as
required before two mid-loop return statements.
Issue found with Coccinelle.

Signed-off-by: Nishka Dasgupta <nishkadg.linux@gmail.com>
Link: https://lore.kernel.org/r/20190808074720.15754-1-nishkadg.linux@gmail.com
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-10 10:29:19 +02:00
Nishka Dasgupta 5a6bc29032 pinctrl: sprd: Add of_node_put() before return to prevent memory leak
Each iteration of for_each_child_of_node puts the previous node, but in
the case of a return from the middle of the loop, there is no put, thus
causing a memory leak. Hence add an of_node_put before the return in
two places.
Issue found with Coccinelle.

Signed-off-by: Nishka Dasgupta <nishkadg.linux@gmail.com>
Link: https://lore.kernel.org/r/20190808074329.15579-1-nishkadg.linux@gmail.com
Reviewed-by: Baolin Wang <baolin.wang@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-10 10:22:50 +02:00
Nishka Dasgupta 474137c911 pinctrl: stm32: stm32: Add of_node_put() before return
Each iteration of for_each_child_of_node and
for_each_available_child_of_node puts the previous node, but in
the case of a return from the middle of the loop, there is no put, thus
causing a memory leak. Hence add an of_node_put before the return in
two places.
Issue found with Coccinelle.

Signed-off-by: Nishka Dasgupta <nishkadg.linux@gmail.com>
Link: https://lore.kernel.org/r/20190808075457.16109-1-nishkadg.linux@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-10 10:21:51 +02:00
Nathan Chancellor 21b2920fb5 pinctrl: aspeed: g6: Remove const specifier from aspeed_g6_sig_expr_set's ctx parameter
clang errors:

drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c:2325:9: error: incompatible
pointer types initializing 'int (*)(struct aspeed_pinmux_data *, const
struct aspeed_sig_expr *, bool)' with an expression of type 'int (const
struct aspeed_pinmux_data *, const struct aspeed_sig_expr *, bool)'
[-Werror,-Wincompatible-pointer-types]
        .set = aspeed_g6_sig_expr_set,
               ^~~~~~~~~~~~~~~~~~~~~~
1 error generated.

Commit 674fa8daa8 ("pinctrl: aspeed-g5: Delay acquisition of regmaps")
changed the set function pointer declaration and the g6 one wasn't
updated (I assume because it wasn't merged yet).

Fixes: 2eda1cdec4 ("pinctrl: aspeed: Add AST2600 pinmux support")
Link: https://github.com/ClangBuiltLinux/linux/issues/632
Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
Link: https://lore.kernel.org/r/20190807003037.48457-1-natechancellor@gmail.com
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-10 10:13:11 +02:00
Geert Uytterhoeven 625efea83a pinctrl: rza1: Use devm_platform_ioremap_resource() helper
Use the devm_platform_ioremap_resource() helper instead of open-coding
the same operation.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-08-09 09:34:45 +02:00
Andy Shevchenko bf5ab1bded pinctrl: denverton: Update pin names according to v1.08
Version 1.08 of pin list has some changes in pin names for Intel Denverton.

Update the driver accordingly.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-08-08 12:57:01 +03:00
Geert Uytterhoeven 6da53cfa0f pinctrl: sh-pfc: Use dev_notice_once() instead of open-coding
At the time of commit 9a643c9a11 ("sh-pfc: Convert message
printing from pr_* to dev_*"), the dev_*_once() variants didn't exist
yet, so the once behavior was open-coded.

Since commit e135303bd5 ("device: Add dev_<level>_once variants")
they do, so "revert" to the good practice of using a helper.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulrich Hecht <uli+renesas@fpond.eu>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2019-08-08 10:18:57 +02:00
Stephen Boyd 57afe3ea27 pinctrl: cherryview: Remove dev_err() usage after platform_get_irq()
We don't need dev_err() messages when platform_get_irq() fails now that
platform_get_irq() prints an error message itself when something goes
wrong. Let's remove these prints with a simple semantic patch.

// <smpl>
@@
expression ret;
struct platform_device *E;
@@

ret =
(
platform_get_irq(E, ...)
|
platform_get_irq_byname(E, ...)
);

if ( \( ret < 0 \| ret <= 0 \) )
{
(
-if (ret != -EPROBE_DEFER)
-{ ...
-dev_err(...);
-... }
|
...
-dev_err(...);
)
...
}
// </smpl>

While we're here, remove braces on if statements that only have one
statement (manually).

Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: linux-gpio@vger.kernel.org
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Mika Westerberg <mika.westerberg@linux.intel.com>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-08-07 17:25:49 +03:00
Stephen Boyd 4e73d02f16 pinctrl: intel: Remove dev_err() usage after platform_get_irq()
We don't need dev_err() messages when platform_get_irq() fails now that
platform_get_irq() prints an error message itself when something goes
wrong. Let's remove these prints with a simple semantic patch.

// <smpl>
@@
expression ret;
struct platform_device *E;
@@

ret =
(
platform_get_irq(E, ...)
|
platform_get_irq_byname(E, ...)
);

if ( \( ret < 0 \| ret <= 0 \) )
{
(
-if (ret != -EPROBE_DEFER)
-{ ...
-dev_err(...);
-... }
|
...
-dev_err(...);
)
...
}
// </smpl>

While we're here, remove braces on if statements that only have one
statement (manually).

Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: linux-gpio@vger.kernel.org
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Mika Westerberg <mika.westerberg@linux.intel.com>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-08-07 17:25:49 +03:00
Andy Shevchenko 6a33a1d6d6 pinctrl: intel: Use NSEC_PER_USEC for debounce calculus
Replace hard coded constants with self-explanatory names, i.e.
use NSEC_PER_USEC for debounce calculus.

While here, add a unit suffix to debounce period constant.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-08-07 17:25:19 +03:00
Andy Shevchenko 34e656703e pinctrl: baytrail: Re-use data structures from pinctrl-intel.h (part 2)
We have some data structures duplicated across the drivers.
Let's deduplicate them by using ones that being provided by
pinctrl-intel.h.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-08-07 17:25:19 +03:00
Andy Shevchenko 179e5a6114 pinctrl: intel: Remove default Interrupt Status offset
Since some of the GPIO controllers use different Interrupt Status offset,
it make sense to provide it explicitly in the drivers.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-08-07 17:25:19 +03:00
Andy Shevchenko 3b1e9188df pinctrl: lewisburg: Provide Interrupt Status register offset
Since some of the GPIO controllers use different Interrupt Status offset,
it make sense to provide it explicitly in the driver.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-08-07 16:45:41 +03:00
Andy Shevchenko 2a2ed47521 pinctrl: denverton: Provide Interrupt Status register offset
Since some of the GPIO controllers use different Interrupt Status offset,
it make sense to provide it explicitly in the driver.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-08-07 16:45:41 +03:00
Andy Shevchenko f702e0b93c pinctrl: sunrisepoint: Provide Interrupt Status register offset
Since some of the GPIO controllers use different Interrupt Status offset,
it make sense to provide it explicitly in the driver.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-08-07 16:45:41 +03:00
Andy Shevchenko b8d728687e pinctrl: icelake: Provide Interrupt Status register offset
Since some of the GPIO controllers use different Interrupt Status offset,
it make sense to provide it explicitly in the driver.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-08-07 16:45:41 +03:00
Andy Shevchenko cd5acb2bce pinctrl: geminilake: Provide Interrupt Status register offset
Since some of the GPIO controllers use different Interrupt Status offset,
it make sense to provide it explicitly in the driver.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-08-07 16:45:41 +03:00
Andy Shevchenko 82af745d2f pinctrl: cannonlake: Provide Interrupt Status register offset
Since some of the GPIO controllers use different Interrupt Status offset,
it make sense to provide it explicitly in the driver.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-08-07 16:45:41 +03:00
Andy Shevchenko 3818d73612 pinctrl: broxton: Provide Interrupt Status register offset
Since some of the GPIO controllers use different Interrupt Status offset,
it make sense to provide it explicitly in the driver.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-08-07 16:45:41 +03:00
Andy Shevchenko 7eb7ecddd3 pinctrl: intel: Simplify offset validation in intel_get_padcfg()
There is more generic and simpler validation just against the nregs.
Using it allows to drop customization from the intel_get_padcfg().

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-08-07 16:44:55 +03:00
Jitendra Sharma f2ae04c45b pinctrl: qcom: Add SC7180 pinctrl driver
Add initial pinctrl driver to support pin configuration with
pinctrl framework for SC7180

Signed-off-by: Jitendra Sharma <shajit@codeaurora.org>
Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org>
[rnayak: modify to use upstream tile support
	 sort and squash some functions]
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20190806060536.18094-2-rnayak@codeaurora.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-07 14:43:51 +02:00
Nishka Dasgupta 8df92d676c pinctrl: spear: spear: Add of_node_put() before return
Each iteration of for_each_child_of_node puts the previous node, but in
the case of a return from the middle of the loop, there is no put, thus
causing a memory leak. Hence add an of_node_put before the return in
two places.
Issue found with Coccinelle.

Signed-off-by: Nishka Dasgupta <nishkadg.linux@gmail.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Link: https://lore.kernel.org/r/20190804154948.4584-1-nishkadg.linux@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-06 16:18:49 +02:00
Nishka Dasgupta 646d90c3c2 pinctrl: freescale: mxs: Add of_node_put() before return
Each iteration of for_each_child_of_node puts the previous node, but in
the case of a return from the middle of the loop, there is no put, thus
causing a memory leak. Hence add an of_node_put before the return in
three places.
Issue found with Coccinelle.

Signed-off-by: Nishka Dasgupta <nishkadg.linux@gmail.com>
Link: https://lore.kernel.org/r/20190804160420.5309-1-nishkadg.linux@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-06 14:52:24 +02:00
Nishka Dasgupta f452444709 pinctrl: nomadik: abx500: Add of_node_put() before return
Each iteration of for_each_child_of_node puts the previous node, but in
the case of a return from the middle of the loop, there is no put, thus
causing a memory leak. Hence add an of_node_put before the return.
Issue found with Coccinelle.

Signed-off-by: Nishka Dasgupta <nishkadg.linux@gmail.com>
Link: https://lore.kernel.org/r/20190804155154.4916-1-nishkadg.linux@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-06 14:51:59 +02:00
Nishka Dasgupta ea8cf5c518 pinctrl: nomadik: nomadik: Add of_node_put() before return
Each iteration of for_each_child_of_node puts the previous node, but in
the case of a return from the middle of the loop, there is no put, thus
causing a memory leak. Hence add an of_node_put before the return.
Issue found with Coccinelle.

Signed-off-by: Nishka Dasgupta <nishkadg.linux@gmail.com>
Link: https://lore.kernel.org/r/20190804155117.4753-1-nishkadg.linux@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-06 14:51:13 +02:00
Nishka Dasgupta f17d2f54d3 pinctrl: falcon: Add of_node_put() before return
Each iteration of for_each_compatible_node puts the previous node, but in
the case of a return from the middle of the loop, there is no put, thus
causing a memory leak. Hence add an of_node_put before the return in two
places.
Issue found with Coccinelle.

Signed-off-by: Nishka Dasgupta <nishkadg.linux@gmail.com>
Link: https://lore.kernel.org/r/20190804152745.2231-1-nishkadg.linux@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-06 14:50:04 +02:00
Geert Uytterhoeven d55b7fdd58 pinctrl: xway: Use devm_kasprintf() instead of fixed buffer formatting
Improve readability and maintainability by replacing a hardcoded string
allocation and formatting by the use of the devm_kasprintf() helper.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20190731132917.17607-4-geert+renesas@glider.be
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-05 13:31:17 +02:00
Geert Uytterhoeven 811604d01e pinctrl: lantiq: Use kasprintf() instead of fixed buffer formatting
Improve readability and maintainability by replacing a hardcoded string
allocation and formatting by the use of the kasprintf() helper.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20190731132917.17607-3-geert+renesas@glider.be
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-05 13:30:15 +02:00
Geert Uytterhoeven f0b0e923e0 pinctrl: devicetree: Use strlen() instead of hardcoded number
Improve readability by replacing a hardcoded number requiring a comment
by strlen().

Gcc is smart enough to evaluate the length of a constant string at
compile-time.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20190731132917.17607-2-geert+renesas@glider.be
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-05 13:29:29 +02:00
Stephen Boyd 64c4dcbfcc pinctrl: Remove dev_err() usage after platform_get_irq()
We don't need dev_err() messages when platform_get_irq() fails now that
platform_get_irq() prints an error message itself when something goes
wrong. Let's remove these prints with a simple semantic patch.

// <smpl>
@@
expression ret;
struct platform_device *E;
@@

ret =
(
platform_get_irq(E, ...)
|
platform_get_irq_byname(E, ...)
);

if ( \( ret < 0 \| ret <= 0 \) )
{
(
-if (ret != -EPROBE_DEFER)
-{ ...
-dev_err(...);
-... }
|
...
-dev_err(...);
)
...
}
// </smpl>

While we're here, remove braces on if statements that only have one
statement (manually).

Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: linux-gpio@vger.kernel.org
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/20190730181557.90391-34-swboyd@chromium.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-05 13:24:06 +02:00
Kunihiko Hayashi 31b4c4b124 pinctrl: uniphier: Fix Pro5 SD pin-mux setting
SD uses the following pins starting from 247:
    SDCD, SDWP, SDVOLC, SDCLK, SDCMD, SDDAT{0,1,2,3}

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Link: https://lore.kernel.org/r/1564465410-9165-6-git-send-email-hayashi.kunihiko@socionext.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-05 13:21:31 +02:00
Kunihiko Hayashi 490bbdcfc4 pinctrl: uniphier: Add Pro5 PCIe pin-mux settings
Pro5 PCIe interface uses the following pins:
    XPERST, XPEWAKE, XPECLKRQ

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/1564465410-9165-5-git-send-email-hayashi.kunihiko@socionext.com
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-05 13:20:26 +02:00
Kunihiko Hayashi fc1d910ae9 pinctrl: uniphier: Add 5th LD20 MPEG2-TS input pin-mux setting
The 5th serial TS interface uses the following pins:
  hscin4_s: PCA[11-14]

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Link: https://lore.kernel.org/r/1564465410-9165-4-git-send-email-hayashi.kunihiko@socionext.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-05 13:19:35 +02:00
Kunihiko Hayashi f686867266 pinctrl: uniphier: Add another audio I/O pin-mux settings for LD20
This adds support for pinmux settings of aout1b group. This group includes
audio I/O signals derived from xirq pins, and it is equivalent to "aout1"
in functionality.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/1564465410-9165-3-git-send-email-hayashi.kunihiko@socionext.com
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-05 13:18:34 +02:00
Kunihiko Hayashi 111a8fcb2c pinctrl: uniphier: Separate modem group from UART ctsrts group
It depends on the board implementation whether to have each pins of
CTS/RTS, and others for modem. So it is necessary to divide current
uart_ctsrts group into uart_ctsrts and uart_modem groups.

Since the number of implemented pins for modem differs depending
on SoC, each uart_modem group also has a different number of pins.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/1564465410-9165-2-git-send-email-hayashi.kunihiko@socionext.com
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-05 13:17:20 +02:00
Neil Armstrong 726e8d8137 pinctrl: meson-g12a: add pwm_a on GPIOE_2 pinmux
Add the missing pinmux for the pwm_a function on the GPIOE_2 pin.

Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lore.kernel.org/r/20190729125838.6498-1-narmstrong@baylibre.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-05 13:00:54 +02:00
Andrew Jeffery 73c732c571 pinctrl: aspeed: Document existence of deprecated compatibles
Otherwise they look odd in the face of not being listed in the bindings
documents.

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20190724081313.12934-3-andrew@aj.id.au
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-05 12:47:09 +02:00
Andrew Jeffery 2eda1cdec4 pinctrl: aspeed: Add AST2600 pinmux support
The AST2600 pinmux is fairly similar to the previous generations of
ASPEED BMC SoCs in terms of architecture, though differ in some of the
design details. The complexity of the pin expressions is largely reduced
(e.g. there are no-longer signals with multiple expressions muxing them
to the associated pin), and there are now signals and buses with
multiple pin groups.

The driver implements pinmux support for all 244 GPIO-capable pins plus
a further four pins that are not GPIO capable but which expose multiple
signals. pinconf will be implemented in a follow-up patch.

The implementation has been smoke-tested under qemu, and run on hardware
by ASPEED.

Debugged-by: Johnny Huang <johnny_huang@aspeedtech.com>
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20190711041942.23202-7-andrew@aj.id.au
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-05 12:41:18 +02:00
Andrew Jeffery 86392fac9a pinctrl: aspeed: Add SIG_DESC_CLEAR() helper
The complement of SIG_DESC_SET().

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20190729055604.13239-6-andrew@aj.id.au
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-05 12:40:48 +02:00
Andrew Jeffery e7a96b0b7d pinctrl: aspeed: Add multiple pin group support for functions
The AST2400 and AST2500 SoCs only exposed one pin group per function.
Lone pin groups drove some implementation simplifications in the ASPEED
pinmux infrastructure that is now invalid for the AST2600, which
supports multiple groups per function for some functions on the chip
(SMBus Alert pins and UARTs among others).

This patch reworks the macro jungle to enable support for multiple pin
groups. In the process we inflict some collateral damage on the existing
AST2400 and AST2500 drivers, but the rework is mostly a relatively
straight-forward, automated transform of adding the pin name as an
argument to some macro calls and implementing wrappers to paper over
groups in the cases where there aren't multiple.

As previously documented, the macro infrastructure exposes mux
configuration as symbols in the source file which are used to detect
accidental duplication. Previously these symbols were named in terms of
the signal for a given expression. As the AST2600 supports multiple pin
groups for a function, the signal name on its own is no-longer unique,
and we must switch to the (signal, group) tuple. However, this means
that we can no-longer derive the signal expression symbol name from the
signal name alone, which among other cases, impacts the operation of the
PIN_DECL_x() macros.

To fix that and avoid requiring we awkwardly provide the associated
group name for every signal for every PIN_DECL_x() invocation, instead
opportunistically alias the name of the signal expression symbol from
the unique (signal, group) tuple to the also unique (pin, signal) tuple,
then reference the alias symbol in the tables generated by PIN_DECL_x().
This way we do not require extra group parameters for PIN_DECL_x() as
the pin name was already provided as an argument, and instead simply
require that the pin name be provided to the expression declaration
macros in order to generate the alias symbol.

The patch implements the alias strategy and fixes up all the expression
definition macro calls in the AST2400 and AST2500 drivers to account for
pin groups. Given the implementation strategy has the property that
compilation either fails or loudly warns for bad pin descriptions, this
patch is theoretically tested by successfully compiling both affected
drivers. For a more practical test I've inspected the diff of the
content of the pinctrl debugfs entries before and after the patch under
qemu; all pins, functions and groups match.

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20190729055604.13239-5-andrew@aj.id.au
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-05 12:40:21 +02:00
Andrew Jeffery 27d1f73670 pinctrl: aspeed: Add PIN_DECL_3() helper
This case is common in the AST2600, so add to the collection.

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20190729055604.13239-4-andrew@aj.id.au
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-05 12:39:48 +02:00
Andrew Jeffery 7b38897081 pinctrl: aspeed: Rename pin declaration macros
Rename macros as follows:

* s/SS_PIN_DECL()/PIN_DECL_1()/
* s/MS_PIN_DECL()/PIN_DECL_2()/
* s/MS_PIN_DECL_()/PIN_DECL_()/

This is in preparation for adding PIN_DECL_3(). We could clean this up
with e.g. CPPMAGIC_MAP() from ccan, but that might be a bridge too far
given how much of a macro jungle we already have.

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20190729055604.13239-3-andrew@aj.id.au
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-05 12:39:27 +02:00
Icenowy Zheng fb18f1887f pinctrl: sunxi: v3s: introduce support for V3
Introduce the GPIO pins that is only available on V3 (not on V3s) to the
V3s pinctrl driver.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>

Link: https://lore.kernel.org/r/20190728031227.49140-2-icenowy@aosc.io
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-05 12:35:29 +02:00
Anders Roxell 6161dc0358 pinctrl: qcom: spmi-gpio: Mark expected switch fall-through
When fall-through warnings was enabled by default the following warnings
was starting to show up:

../drivers/pinctrl/qcom/pinctrl-spmi-gpio.c: In function ‘pmic_gpio_populate’:
../drivers/pinctrl/qcom/pinctrl-spmi-gpio.c:815:20: warning: this statement may fall
 through [-Wimplicit-fallthrough=]
   pad->have_buffer = true;
   ~~~~~~~~~~~~~~~~~^~~~~~
../drivers/pinctrl/qcom/pinctrl-spmi-gpio.c:816:2: note: here
  case PMIC_GPIO_SUBTYPE_GPIOC_4CH:
  ^~~~
../drivers/pinctrl/qcom/pinctrl-spmi-gpio.c:820:20: warning: this statement may fall
 through [-Wimplicit-fallthrough=]
   pad->have_buffer = true;
   ~~~~~~~~~~~~~~~~~^~~~~~
../drivers/pinctrl/qcom/pinctrl-spmi-gpio.c:821:2: note: here
  case PMIC_GPIO_SUBTYPE_GPIOC_8CH:
  ^~~~

Rework so that the compiler doesn't warn about fall-through.

Fixes: d93512ef0f0e ("Makefile: Globally enable fall-through warning")
Signed-off-by: Anders Roxell <anders.roxell@linaro.org>
Link: https://lore.kernel.org/r/20190726112816.19723-1-anders.roxell@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-05 12:33:28 +02:00
Anders Roxell cd927f140d pinctrl: rockchip: Mark expected switch fall-through
When fall-through warnings was enabled by default the following warning
was starting to show up:

../drivers/pinctrl/pinctrl-rockchip.c: In function ‘rockchip_gpio_set_config’:
../drivers/pinctrl/pinctrl-rockchip.c:2783:3: warning: this statement may fall
 through [-Wimplicit-fallthrough=]
   rockchip_gpio_set_debounce(gc, offset, true);
   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../drivers/pinctrl/pinctrl-rockchip.c:2795:2: note: here
  default:
  ^~~~~~~

Rework so that the compiler doesn't warn about fall-through. Add
'return -ENOTSUPP;' to match the comment.

Fixes: d93512ef0f0e ("Makefile: Globally enable fall-through warning")
Signed-off-by: Anders Roxell <anders.roxell@linaro.org>
Link: https://lore.kernel.org/r/20190726112812.19665-1-anders.roxell@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-05 12:32:27 +02:00
YueHaibing be65c8bb0c pinctrl: oxnas: remove set but not used variable 'arg'
Fixes gcc '-Wunused-but-set-variable' warning:

drivers/pinctrl/pinctrl-oxnas.c: In function oxnas_ox810se_pinconf_set:
drivers/pinctrl/pinctrl-oxnas.c:905:6: warning: variable arg set but not used [-Wunused-but-set-variable]
drivers/pinctrl/pinctrl-oxnas.c: In function oxnas_ox820_pinconf_set:
drivers/pinctrl/pinctrl-oxnas.c:944:6: warning: variable arg set but not used [-Wunused-but-set-variable]

It is never used since commit 4b0c0c25fa ("pinctrl:
oxnas: Add support for OX820"), so can be removed.

Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Link: https://lore.kernel.org/r/20190725142419.29892-1-yuehaibing@huawei.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-05 12:15:56 +02:00
Alexandre Torgue a502b343eb pinctrl: stmfx: update pinconf settings
According to the following tab (coming from STMFX datasheet), updates
have to done in stmfx_pinconf_set function:

-"type" has to be set when "bias" is configured as "pull-up or pull-down"
-PIN_CONFIG_DRIVE_PUSH_PULL should only be used when gpio is configured as
 output. There is so no need to check direction.

DIR | TYPE | PUPD | MFX GPIO configuration
----|------|------|---------------------------------------------------
1   | 1    | 1    | OUTPUT open drain with internal pull-up resistor
----|------|------|---------------------------------------------------
1   | 1    | 0    | OUTPUT open drain with internal pull-down resistor
----|------|------|---------------------------------------------------
1   | 0    | 0/1  | OUTPUT push pull no pull
----|------|------|---------------------------------------------------
0   | 1    | 1    | INPUT with internal pull-up resistor
----|------|------|---------------------------------------------------
0   | 1    | 0    | INPUT with internal pull-down resistor
----|------|------|---------------------------------------------------
0   | 0    | 1    | INPUT floating
----|------|------|---------------------------------------------------
0   | 0    | 0    | analog (GPIO not used, default setting)

Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
Link: https://lore.kernel.org/r/1564053416-32192-1-git-send-email-amelie.delaunay@st.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-05 12:14:30 +02:00
Baolin Wang 2f22e2028c pinctrl: sprd: Combine the condition of MISC_PIN and COMMON_PIN
Since the follow-up pin design on Spreadtrum platform has some changes,
some configuration of MISC_PIN moved to COMMON_PIN. To support current
pin design and keep backward compatibility, we should combine the
condition of MISC_PIN and COMMON_PIN to configure an individual pin.

Signed-off-by: Baolin Wang <baolin.wang@linaro.org>
Link: https://lore.kernel.org/r/17af5e761e0515d288a7ea4078ac9aa4a82a7a4e.1564048446.git.baolin.wang@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-05 12:13:18 +02:00
Baolin Wang e89febc75d pinctrl: sprd: Change to use devm_platform_ioremap_resource()
The devm_platform_ioremap_resource() function wraps platform_get_resource()
and devm_ioremap_resource() in a single helper, thus use it to simplify
the code.

Signed-off-by: Baolin Wang <baolin.wang@linaro.org>
Link: https://lore.kernel.org/r/ff410d312ed0047b5a36e5113daf7df78bcf1aa8.1564048446.git.baolin.wang@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-05 12:12:32 +02:00
Andy Shevchenko db5b44f82a pinctrl: qdf2xxx: Switch to use device_property_count_uXX()
Use use device_property_count_uXX() directly, that makes code neater.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20190723192738.68486-2-andriy.shevchenko@linux.intel.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-05 12:01:45 +02:00
Andy Shevchenko 720b8ec676 pinctrl: msm: Switch to use device_property_count_uXX()
Use use device_property_count_uXX() directly, that makes code neater.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20190723192738.68486-1-andriy.shevchenko@linux.intel.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-05 11:55:41 +02:00
Charles Keepax a1db8da7c2 pinctrl: madera: Add configuration for Cirrus Logic CS47L92
This adds the pinctrl configuration for the CS47L92 codec to
the madera pinctrl driver.

Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Link: https://lore.kernel.org/r/20190722091015.20884-3-ckeepax@opensource.cirrus.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-05 11:48:03 +02:00
Richard Fitzgerald b0bca3e4ee pinctrl: madera: Add configuration for Cirrus Logic CS47L15
This adds the pinctrl configuration for the CS47L15 codec to
the madera pinctrl driver.

Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com>
Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Link: https://lore.kernel.org/r/20190722091015.20884-2-ckeepax@opensource.cirrus.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-05 11:47:14 +02:00
Charles Keepax f134b85177 pinctrl: madera: Use local copy of pdata
A local copy of the pdata exists and it should be used rather than
pulling a fresh copy.

Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Link: https://lore.kernel.org/r/20190722091015.20884-1-ckeepax@opensource.cirrus.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-05 11:46:25 +02:00
Stefan Wahren e38a9a437f pinctrl: bcm2835: Add support for BCM2711 pull-up functionality
The BCM2711 has a new way of selecting the pull-up/pull-down setting
for a GPIO pin. The registers used for the BCM2835, GP_PUD and
GP_PUDCLKn0, are no longer connected. A new set of registers,
GP_GPIO_PUP_PDN_CNTRL_REGx must be used. This commit will add
a new compatible string "brcm,bcm2711-gpio" and the kernel
driver will use it to select which method is used to select
pull-up/pull-down.

This patch based on a patch by Al Cooper which was intended for the
BCM7211. This is a bugfixed and improved version.

Signed-off-by: Stefan Wahren <wahrenst@gmx.net>
Link: https://lore.kernel.org/r/1563776607-8368-3-git-send-email-wahrenst@gmx.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-05 11:35:41 +02:00
Sowjanya Komatineni 6c172af579 pinctrl: tegra210: Add Tegra210 pinctrl pm ops
This patch adds suspend and resume functionality to Tegra210 pinctrl.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Link: https://lore.kernel.org/r/1564607463-28802-3-git-send-email-skomatineni@nvidia.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-05 11:21:28 +02:00
Sowjanya Komatineni 9870acd374 pinctrl: tegra: Add suspend and resume support
This patch adds support for Tegra pinctrl driver suspend and resume.

During suspend, context of all pinctrl registers are stored and
on resume they are all restored to have all the pinmux and pad
configuration for normal operation.

Acked-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Link: https://lore.kernel.org/r/1564607463-28802-2-git-send-email-skomatineni@nvidia.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-05 11:19:35 +02:00
Nishka Dasgupta 2f64dc70ba pinctrl: rzn1: Add of_node_put() before return
Each iteration of for_each_child_of_node puts the previous node, but in
the case of a return from the middle of the loop, there is no put, thus
causing a memory leak. Hence add an of_node_put before the return in
three places.
Issue found with Coccinelle.

Signed-off-by: Nishka Dasgupta <nishkadg.linux@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-08-05 09:23:57 +02:00
YueHaibing 1d1def89bd pinctrl: sprd: Fix platform_no_drv_owner.cocci warnings
Remove .owner field if calls are used which set it automatically
Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci

Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Link: https://lore.kernel.org/r/20190719032414.85369-1-yuehaibing@huawei.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-03 00:32:34 +02:00
Zhou Yanjie 5d21595b17 pinctrl: Ingenic: Add pinctrl driver for X1500.
Add support for probing the pinctrl-ingenic driver on the
X1500 Soc from Ingenic.

Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
Link: https://lore.kernel.org/r/1563076436-5338-7-git-send-email-zhouyanjie@zoho.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 23:42:08 +02:00
Zhou Yanjie fe1ad5eedc pinctrl: Ingenic: Add pinctrl driver for X1000 and X1000E.
Add support for probing the pinctrl-ingenic driver on the
X1000 Soc and the X1000E Soc from Ingenic.

Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
Link: https://lore.kernel.org/r/1563076436-5338-5-git-send-email-zhouyanjie@zoho.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 23:41:27 +02:00
Zhou Yanjie 0257595a5c pinctrl: Ingenic: Add pinctrl driver for JZ4760 and JZ4760B.
Add support for probing the pinctrl-ingenic driver on the
JZ4760 Soc and the JZ4760B Soc from Ingenic.

Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
Link: https://lore.kernel.org/r/1563076436-5338-3-git-send-email-zhouyanjie@zoho.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 23:40:23 +02:00
YueHaibing 8c4407de3b pinctrl: aspeed: Make aspeed_pinmux_ips static
Fix sparse warning:

drivers/pinctrl/aspeed/pinmux-aspeed.c:8:12: warning:
 symbol 'aspeed_pinmux_ips' was not declared. Should it be static?

Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Link: https://lore.kernel.org/r/20190711142457.37028-1-yuehaibing@huawei.com
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 23:35:31 +02:00
Marc Gonzalez fa21cbea92 pinctrl: msm8998: Squash TSIF pins together
TSIF is the Transport Stream Interface.
First, rename tsif1 to tsif0, and tsif2 to tsif1.
Then squash all 5 tsif0 pins into a single function.
Same for tsif1.

Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr>
Link: https://lore.kernel.org/r/503b2ae8-ead6-70cd-7b21-ce5f5166a23a@free.fr
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 23:28:57 +02:00
Andrew Jeffery 674fa8daa8 pinctrl: aspeed-g5: Delay acquisition of regmaps
While sorting out some devicetree issues I found that the pinctrl driver
was failing to acquire its GFX regmap even though the phandle was
present in the devicetree:

    [    0.124190] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: No GFX phandle found, some mux configurations may fail

Without access to the GFX regmap we fail to configure the mux for the
VPO function:

    [    1.548866] pinctrl core: add 1 pinctrl maps
    [    1.549826] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: found group selector 164 for VPO
    [    1.550638] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: request pin 144 (V20) for 1e6e6000.display
    [    1.551346] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: request pin 145 (U19) for 1e6e6000.display
    ...
    [    1.562057] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: request pin 218 (T22) for 1e6e6000.display
    [    1.562541] aspeed-g5-pinctrl 1e6e2000.syscon:pinctrl: request pin 219 (R20) for 1e6e6000.display
    [    1.563113] Muxing pin 144 for VPO
    [    1.563456] Want SCU8C[0x00000001]=0x1, got 0x0 from 0x00000000
    [    1.564624] aspeed_gfx 1e6e6000.display: Error applying setting, reverse things back

This turned out to be a simple problem of timing: The ASPEED pinctrl
driver is probed during arch_initcall(), while GFX is processed much
later. As such the GFX syscon is not yet registered during the pinctrl
probe() and we get an -EPROBE_DEFER when we try to look it up, however
we must not defer probing the pinctrl driver for the inability to mux
some GFX-related functions.

Switch to lazily grabbing the regmaps when they're first required by the
mux configuration. This generates a bit of noise in the patch as we have
to drop the `const` qualifier on arguments for several function
prototypes, but has the benefit of working.

I've smoke tested this for the ast2500-evb under qemu with a dummy
graphics device. We now succeed in our attempts to configure the SoC's
VPO pinmux function.

Fixes: 7d29ed88ac ("pinctrl: aspeed: Read and write bits in LPC and GFX controllers")
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20190724080155.12209-1-andrew@aj.id.au
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 00:52:51 +02:00
Linus Walleij 0ce242ad2e pinctrl: qcom: Pass irqchip when adding gpiochip
We need to convert all old gpio irqchips to pass the irqchip
setup along when adding the gpio_chip.

For chained irqchips this is a pretty straight-forward
conversion.

Cc: Thierry Reding <treding@nvidia.com>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Co-developed-by: Lina Iyer <ilina@codeaurora.org>
Link: https://lore.kernel.org/r/20190724083828.7496-1-linus.walleij@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 00:43:25 +02:00
Andy Shevchenko cfc1c34585 pinctrl: intel: Drop double check for data in intel_pinctrl_probe_by_uid()
There is no need to duplicate the check which is done in the common
intel_pinctrl_probe().

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-07-23 18:50:48 +03:00
Andy Shevchenko fa01aff976 pinctrl: merrifield: Use devm_platform_ioremap_resource()
Use the new helper that wraps the calls to platform_get_resource()
and devm_ioremap_resource() together.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-07-23 16:13:14 +03:00
Andy Shevchenko 9d5b6a9520 pinctrl: intel: Use devm_platform_ioremap_resource()
Use the new helper that wraps the calls to platform_get_resource()
and devm_ioremap_resource() together.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-07-23 16:13:14 +03:00
Andy Shevchenko a86f12b277 pinctrl: cherryview: Use devm_platform_ioremap_resource()
Use the new helper that wraps the calls to platform_get_resource()
and devm_ioremap_resource() together.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-07-23 16:13:14 +03:00
Andy Shevchenko 24025010d1 pinctrl: baytrail: Use devm_platform_ioremap_resource()
Use the new helper that wraps the calls to platform_get_resource()
and devm_ioremap_resource() together.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-07-23 16:13:13 +03:00
Linus Torvalds 43c95d3694 This is the bulk of pin control changes for the v5.3 kernel
cycle:
 
 Core changes:
 
 - Device links can optionally be added between a pin control
   producer and its consumers. This will affect how the system
   power management is handled: a pin controller will not suspend
   before all of its consumers have been suspended. This was
   necessary for the ST Microelectronics STMFX expander and
   need to be tested on other systems as well: it makes sense
   to make this default in the long run. Right now it is
   opt-in per driver.
 
 - Drive strength can be specified in microamps. With decreases
   in silicon technology, milliamps isn't granular enough, let's
   make it possible to select drive strengths in microamps. Right
   now the Meson (AMlogic) driver needs this.
 
 New drivers:
 
 - New subdriver for the Tegra 194 SoC.
 
 - New subdriver for the Qualcomm SDM845.
 
 - New subdriver for the Qualcomm SM8150.
 
 - New subdriver for the Freescale i.MX8MN (Freescale is now a
   product line of NXP).
 
 - New subdriver for Marvell MV98DX1135.
 
 Driver improvements:
 
 - The Bitmain BM1880 driver now supports pin config in
   addition to muxing.
 
 - The Qualcomm drivers can now reserve some GPIOs as taken
   aside and not usable for users. This is used in ACPI systems
   to take out some GPIO lines used by the BIOS so that
   noone else (neither kernel nor userspace) will play with them
   by mistake and crash the machine.
 
 - A slew of refurbishing around the Aspeed drivers (board
   management controllers for servers) in preparation for the
   new Aspeed AST2600 SoC.
 
 - A slew of improvements over the SH PFC drivers as usual.
 
 - Misc cleanups and fixes.
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Merge tag 'pinctrl-v5.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij:
 "This is the bulk of pin control changes for the v5.3 kernel cycle:

  Core changes:

   - Device links can optionally be added between a pin control producer
     and its consumers. This will affect how the system power management
     is handled: a pin controller will not suspend before all of its
     consumers have been suspended.

     This was necessary for the ST Microelectronics STMFX expander and
     need to be tested on other systems as well: it makes sense to make
     this default in the long run.

     Right now it is opt-in per driver.

   - Drive strength can be specified in microamps. With decreases in
     silicon technology, milliamps isn't granular enough, let's make it
     possible to select drive strengths in microamps.

     Right now the Meson (AMlogic) driver needs this.

  New drivers:

   - New subdriver for the Tegra 194 SoC.

   - New subdriver for the Qualcomm SDM845.

   - New subdriver for the Qualcomm SM8150.

   - New subdriver for the Freescale i.MX8MN (Freescale is now a product
     line of NXP).

   - New subdriver for Marvell MV98DX1135.

  Driver improvements:

   - The Bitmain BM1880 driver now supports pin config in addition to
     muxing.

   - The Qualcomm drivers can now reserve some GPIOs as taken aside and
     not usable for users. This is used in ACPI systems to take out some
     GPIO lines used by the BIOS so that noone else (neither kernel nor
     userspace) will play with them by mistake and crash the machine.

   - A slew of refurbishing around the Aspeed drivers (board management
     controllers for servers) in preparation for the new Aspeed AST2600
     SoC.

   - A slew of improvements over the SH PFC drivers as usual.

   - Misc cleanups and fixes"

* tag 'pinctrl-v5.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (106 commits)
  pinctrl: aspeed: Strip moved macros and structs from private header
  pinctrl: aspeed: Fix missed include
  pinctrl: baytrail: Use GENMASK() consistently
  pinctrl: baytrail: Re-use data structures from pinctrl-intel.h
  pinctrl: baytrail: Use defined macro instead of magic in byt_get_gpio_mux()
  pinctrl: qcom: Add SM8150 pinctrl driver
  dt-bindings: pinctrl: qcom: Add SM8150 pinctrl binding
  dt-bindings: pinctrl: qcom: Document missing gpio nodes
  pinctrl: aspeed: Add implementation-related documentation
  pinctrl: aspeed: Split out pinmux from general pinctrl
  pinctrl: aspeed: Clarify comment about strapping W1C
  pinctrl: aspeed: Correct comment that is no longer true
  MAINTAINERS: Add entry for ASPEED pinctrl drivers
  dt-bindings: pinctrl: aspeed: Convert AST2500 bindings to json-schema
  dt-bindings: pinctrl: aspeed: Convert AST2400 bindings to json-schema
  dt-bindings: pinctrl: aspeed: Split bindings document in two
  pinctrl: qcom: Add irq_enable callback for msm gpio
  pinctrl: madera: Fixup SPDX headers
  pinctrl: qcom: sdm845: Fix CONFIG preprocessor guard
  pinctrl: tegra: Add bitmask support for parked bits
  ...
2019-07-13 15:02:27 -07:00
Linus Torvalds f632a8170a Driver Core and debugfs changes for 5.3-rc1
Here is the "big" driver core and debugfs changes for 5.3-rc1
 
 It's a lot of different patches, all across the tree due to some api
 changes and lots of debugfs cleanups.  Because of this, there is going
 to be some merge issues with your tree at the moment, I'll follow up
 with the expected resolutions to make it easier for you.
 
 Other than the debugfs cleanups, in this set of changes we have:
 	- bus iteration function cleanups (will cause build warnings
 	  with s390 and coresight drivers in your tree)
 	- scripts/get_abi.pl tool to display and parse Documentation/ABI
 	  entries in a simple way
 	- cleanups to Documenatation/ABI/ entries to make them parse
 	  easier due to typos and other minor things
 	- default_attrs use for some ktype users
 	- driver model documentation file conversions to .rst
 	- compressed firmware file loading
 	- deferred probe fixes
 
 All of these have been in linux-next for a while, with a bunch of merge
 issues that Stephen has been patient with me for.  Other than the merge
 issues, functionality is working properly in linux-next :)
 
 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Merge tag 'driver-core-5.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core

Pull driver core and debugfs updates from Greg KH:
 "Here is the "big" driver core and debugfs changes for 5.3-rc1

  It's a lot of different patches, all across the tree due to some api
  changes and lots of debugfs cleanups.

  Other than the debugfs cleanups, in this set of changes we have:

   - bus iteration function cleanups

   - scripts/get_abi.pl tool to display and parse Documentation/ABI
     entries in a simple way

   - cleanups to Documenatation/ABI/ entries to make them parse easier
     due to typos and other minor things

   - default_attrs use for some ktype users

   - driver model documentation file conversions to .rst

   - compressed firmware file loading

   - deferred probe fixes

  All of these have been in linux-next for a while, with a bunch of
  merge issues that Stephen has been patient with me for"

* tag 'driver-core-5.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core: (102 commits)
  debugfs: make error message a bit more verbose
  orangefs: fix build warning from debugfs cleanup patch
  ubifs: fix build warning after debugfs cleanup patch
  driver: core: Allow subsystems to continue deferring probe
  drivers: base: cacheinfo: Ensure cpu hotplug work is done before Intel RDT
  arch_topology: Remove error messages on out-of-memory conditions
  lib: notifier-error-inject: no need to check return value of debugfs_create functions
  swiotlb: no need to check return value of debugfs_create functions
  ceph: no need to check return value of debugfs_create functions
  sunrpc: no need to check return value of debugfs_create functions
  ubifs: no need to check return value of debugfs_create functions
  orangefs: no need to check return value of debugfs_create functions
  nfsd: no need to check return value of debugfs_create functions
  lib: 842: no need to check return value of debugfs_create functions
  debugfs: provide pr_fmt() macro
  debugfs: log errors when something goes wrong
  drivers: s390/cio: Fix compilation warning about const qualifiers
  drivers: Add generic helper to match by of_node
  driver_find_device: Unify the match function with class_find_device()
  bus_find_device: Unify the match callback with class_find_device
  ...
2019-07-12 12:24:03 -07:00
Andrew Jeffery 4c105769bf pinctrl: aspeed: Strip moved macros and structs from private header
Further cleanup from the SPDX fixup fallout for the recent ASPEED
series. aspeed_g4_defconfig, aspeed_g5_defconfig and multi_v5_defconfig
now compile. Smoke tested the g4 and g5 kernels under QEMU's
palmetto-bmc and romulus-bmc machines respectively.

Fixes: 35d8510ea3ad ("pinctrl: aspeed: Fix missed include")
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20190710032216.4088-1-andrew@aj.id.au
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-10 11:19:20 +02:00
Linus Walleij a1cd6c8b8f pinctrl: aspeed: Fix missed include
Some SPDX churn made my fixes drop an important include
from the Aspeed pinctrl header. Fix it up.

Cc: Andrew Jeffery <andrew@aj.id.au>
Reported-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-10 11:19:00 +02:00
Andy Shevchenko eb0a2daa45 pinctrl: baytrail: Use GENMASK() consistently
Use GENMASK() macro for all definitions where it's appropriate.
No functional change intended.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20190703151554.30454-1-andriy.shevchenko@linux.intel.com
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-04 09:58:13 +02:00
Andy Shevchenko 4f010b936b pinctrl: baytrail: Re-use data structures from pinctrl-intel.h
We have some data structures duplicated across the drivers.
Let's deduplicate them by using ones that being provided by
pinctrl-intel.h.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20190703003018.75186-2-andriy.shevchenko@linux.intel.com
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-04 09:51:24 +02:00
Andy Shevchenko a705f9c179 pinctrl: baytrail: Use defined macro instead of magic in byt_get_gpio_mux()
By the fact byt_get_gpio_mux() returns a value of mux settings as
it is represented in hardware. Use defined macro instead of magic numbers
to clarify this.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20190703003018.75186-1-andriy.shevchenko@linux.intel.com
Reviewed-By: Enrico Weigelt <info@metux.net>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-04 09:48:49 +02:00
Prasad Sodagudi 57218371d5 pinctrl: qcom: Add SM8150 pinctrl driver
Add initial pinctrl driver to support pin configuration with
pinctrl framework for SM8150

Signed-off-by: Prasad Sodagudi <psodagud@codeaurora.org>
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
[vkoul: modify to use upstream tile support
	use upstream code style
	order the functions and squash functions]
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20190702105045.27646-4-vkoul@kernel.org
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-04 09:47:13 +02:00
Thierry Reding 62a6bc3a1e driver: core: Allow subsystems to continue deferring probe
Some subsystems, such as pinctrl, allow continuing to defer probe
indefinitely. This is useful for devices that depend on resources
provided by devices that are only probed after the init stage.

One example of this can be seen on Tegra, where the DPAUX hardware
contains pinmuxing controls for pins that it shares with an I2C
controller. The I2C controller is typically used for communication
with a monitor over HDMI (DDC). However, other instances of the I2C
controller are used to access system critical components, such as a
PMIC. The I2C controller driver will therefore usually be a builtin
driver, whereas the DPAUX driver is part of the display driver that
is loaded from a module to avoid bloating the kernel image with all
of the DRM/KMS subsystem.

In this particular case the pins used by this I2C/DDC controller
become accessible very late in the boot process. However, since the
controller is only used in conjunction with display, that's not an
issue.

Unfortunately the driver core currently outputs a warning message
when a device fails to get the pinctrl before the end of the init
stage. That can be confusing for the user because it may sound like
an unwanted error occurred, whereas it's really an expected and
harmless situation.

In order to eliminate this warning, this patch allows callers of the
driver_deferred_probe_check_state() helper to specify that they want
to continue deferring probe, regardless of whether we're past the
init stage or not. All of the callers of that function are updated
for the new signature, but only the pinctrl subsystem passes a true
value in the new persist parameter if appropriate.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20190621151725.20414-1-thierry.reding@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-07-03 21:28:20 +02:00
Andrew Jeffery 1bbe61d892 pinctrl: aspeed: Add implementation-related documentation
The ASPEED pinctrl driver implementations make heavy use of macros to
minimise tedium of implementation and maximise the chance that the
compiler will catch errors in defining signal and pin configurations.
While the goal of minimising errors is achieved, it is at the cost of
the complexity of the macros.

Document examples of the expanded form of pin declarations to
demonstrate the operation of the macros.

Cc: Johnny Huang <johnny_huang@aspeedtech.com>
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20190628023838.15426-9-andrew@aj.id.au
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-03 10:38:58 +02:00
Andrew Jeffery efa5623981 pinctrl: aspeed: Split out pinmux from general pinctrl
ASPEED have completely rearranged the System Control Unit register
layout with the AST2600. The existing code took advantage of the fact
that the AST2400 and AST2500 had layouts that were similar enough to
have little impact on the pinmux infrastructure (though there is a wart
with read-modify-write vs write-1-clear semantics of the hardware
strapping registers between the two).

Given that any similarity has been thrown out with the AST2600, separate
out the function applying an expression state to be driver-specific.
With it, extract out the pinmux macro jungle to its own header and
implementation so the pieces can be composed without dependency cycles.

Cc: Johnny Huang <johnny_huang@aspeedtech.com>
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20190628023838.15426-8-andrew@aj.id.au
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-03 10:38:03 +02:00
Andrew Jeffery d0d88b5c9e pinctrl: aspeed: Clarify comment about strapping W1C
Writes of 1 to SCU7C clear set bits in SCU70, the hardware strapping
register. The information was correct if you squinted while reading, but
hopefully switching the order of the registers as listed conveys it
better.

Cc: Johnny Huang <johnny_huang@aspeedtech.com>
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Acked-by: Joel Stanley <joel@jms.id.au>
Link: https://lore.kernel.org/r/20190628023838.15426-7-andrew@aj.id.au
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-03 10:35:21 +02:00
Andrew Jeffery 0290eba96b pinctrl: aspeed: Correct comment that is no longer true
We have handled the GFX register case for quite some time now.

Cc: Johnny Huang <johnny_huang@aspeedtech.com>
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Acked-by: Joel Stanley <joel@jms.id.au>
Link: https://lore.kernel.org/r/20190628023838.15426-6-andrew@aj.id.au
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-03 10:35:00 +02:00
Srinivas Ramana 4b7618fdc7 pinctrl: qcom: Add irq_enable callback for msm gpio
Introduce the irq_enable callback which will be same as irq_unmask
except that it will also clear the status bit before unmask.

This will help in clearing any erroneous interrupts that would
have got latched when the interrupt is not in use.

There may be devices like UART which can use the same gpio line
for data rx as well as a wakeup gpio when in suspend. The data that
was flowing on the line may latch the interrupt and when we enable
the interrupt before going to suspend, this would trigger the
unexpected interrupt. This change helps clearing the interrupt
so that these unexpected interrupts gets cleared.

Signed-off-by: Srinivas Ramana <sramana@codeaurora.org>
Signed-off-by: Neeraj Upadhyay <neeraju@codeaurora.org>
Link: https://lore.kernel.org/r/1561472086-23360-1-git-send-email-neeraju@codeaurora.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-03 10:25:53 +02:00
Linus Torvalds 061913712d Pin control fixes for the v5.2 cycle:
- Fix IRQ setup in the MCP23s08.
 - Fix pin setup on pins > 31 in the Ocelot driver.
 - Fix IRQs in the Mediatek driver.
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Merge tag 'pinctrl-v5.2-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control fixes from Linus Walleij:
 "Sorry to bomb in fixes this late. Maybe I can comfort you by saying it
  is only driver fixes, and mostly IRQ handling which is something GPIO
  and pin control drivers never get right. You think it works and then
  it doesn't.

  Summary:

   - Fix IRQ setup in the MCP23s08.

   - Fix pin setup on pins > 31 in the Ocelot driver.

   - Fix IRQs in the Mediatek driver"

* tag 'pinctrl-v5.2-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
  pinctrl: mediatek: Update cur_mask in mask/mask ops
  pinctrl: mediatek: Ignore interrupts that are wake only during resume
  pinctrl: ocelot: fix pinmuxing for pins after 31
  pinctrl: ocelot: fix gpio direction for pins after 31
  pinctrl: mcp23s08: Fix add_data and irqchip_add_nested call order
2019-06-29 16:51:10 +08:00
Nicolas Boichat 9d957a959b pinctrl: mediatek: Update cur_mask in mask/mask ops
During suspend/resume, mtk_eint_mask may be called while
wake_mask is active. For example, this happens if a wake-source
with an active interrupt handler wakes the system:
irq/pm.c:irq_pm_check_wakeup would disable the interrupt, so
that it can be handled later on in the resume flow.

However, this may happen before mtk_eint_do_resume is called:
in this case, wake_mask is loaded, and cur_mask is restored
from an older copy, re-enabling the interrupt, and causing
an interrupt storm (especially for level interrupts).

Step by step, for a line that has both wake and interrupt enabled:
 1. cur_mask[irq] = 1; wake_mask[irq] = 1; EINT_EN[irq] = 1 (interrupt
    enabled at hardware level)
 2. System suspends, resumes due to that line (at this stage EINT_EN
    == wake_mask)
 3. irq_pm_check_wakeup is called, and disables the interrupt =>
    EINT_EN[irq] = 0, but we still have cur_mask[irq] = 1
 4. mtk_eint_do_resume is called, and restores EINT_EN = cur_mask, so
    it reenables EINT_EN[irq] = 1 => interrupt storm as the driver
    is not yet ready to handle the interrupt.

This patch fixes the issue in step 3, by recording all mask/unmask
changes in cur_mask. This also avoids the need to read the current
mask in eint_do_suspend, and we can remove mtk_eint_chip_read_mask
function.

The interrupt will be re-enabled properly later on, sometimes after
mtk_eint_do_resume, when the driver is ready to handle it.

Fixes: 58a5e1b64b ("pinctrl: mediatek: Implement wake handler and suspend resume")
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Acked-by: Sean Wang <sean.wang@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-27 12:22:11 +01:00
Nicolas Boichat 35594bc7ce pinctrl: mediatek: Ignore interrupts that are wake only during resume
Before suspending, mtk-eint would set the interrupt mask to the
one in wake_mask. However, some of these interrupts may not have a
corresponding interrupt handler, or the interrupt may be disabled.

On resume, the eint irq handler would trigger nevertheless,
and irq/pm.c:irq_pm_check_wakeup would be called, which would
try to call irq_disable. However, if the interrupt is not enabled
(irqd_irq_disabled(&desc->irq_data) is true), the call does nothing,
and the interrupt is left enabled in the eint driver.

Especially for level-sensitive interrupts, this will lead to an
interrupt storm on resume.

If we detect that an interrupt is only in wake_mask, but not in
cur_mask, we can just mask it out immediately (as mtk_eint_resume
would do anyway at a later stage in the resume sequence, when
restoring cur_mask).

Fixes: bf22ff45be ("genirq: Avoid unnecessary low level irq function calls")
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Acked-by: Sean Wang <sean.wang@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-26 16:09:50 +02:00
Charles Keepax 4cb8df37a7 pinctrl: madera: Fixup SPDX headers
GPL-2.0-only is the preferred way of expressing v2 of the GPL, so switch
to that. Remove some redundant copyright notices and correct some
instances where the wrong comment type has been used in header files.

Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-26 09:51:37 +02:00