3 Commits

Author	SHA1	Message	Date
Soren Brinkmann	353dc6c47d	clk/zynq/pll: Use #defines for fbdiv min/max values ... Use more descriptive #defines for the minimum and maximum PLL feedback divider. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>	2013-08-20 07:54:41 +02:00
Soren Brinkmann	14924ba288	clk/zynq/pll: Fix documentation for PLL register function ... Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>	2013-08-20 07:54:40 +02:00
Soren Brinkmann	3682af46d5	clk: zynq: Factor out PLL driver ... Refactor the PLL driver so it works with the clock controller driver. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Mike Turquette <mturquette@linaro.org>	2013-05-21 16:21:35 +02:00