Commit Graph

17 Commits

Author SHA1 Message Date
Jean-Christophe PLAGNIOL-VILLARD 2b11ea5bf2 ARM: at91/dt: add specific DT soc init
This will allow to have static Device mapping and DT probe mapping for the
System Controller.

Temporary keep the call to ioremap_registers() until we have the binding
for the SDRAM/DDR Controller.

Temporary keep the main clock hardcoded to 12MHz until we have the binding
for the PMC.

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Rob Herring <rob.herring@calxeda.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2012-03-15 23:30:05 +08:00
Jean-Christophe PLAGNIOL-VILLARD 4342d6479e ARM: at91: make matrix register base soc independent
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Reviewed-by: Ryan Mallon <rmallon@gmail.com>
Cc: linux-usb@vger.kernel.org
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2012-02-23 09:24:46 +01:00
Jean-Christophe PLAGNIOL-VILLARD 9918ceafd4 ARM: at91: code removal of CAP9 SoC
Following removal announce and addition to feature-removal-schedule.txt,
here is the actual source code deletion for Atmel CAP9 family.

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2012-02-03 13:33:05 +01:00
Jean-Christophe PLAGNIOL-VILLARD e9f68b5cc6 ARM: at91: make rstc soc independent
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2012-01-20 17:22:38 +01:00
Nicolas Ferre 3e90772f76 ARM: at91: fix at91rm9200 soc subtype handling
Currently setting it to PQFP changes subtype to BGA as subtypes are
swapped in at91rm9200_set_type().

Wrong subtype causes GPIO bank D not to work at all.

After this fix, subtype is still set as unknown. But board code should
fill it in with proper value. Another information is thus printed.

Bug discovery and first implementation made by Veli-Pekka Peltola.

Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: stable <stable@vger.kernel.org>
2012-01-20 14:58:13 +01:00
Olof Johansson 844e8a16f2 Merge branch 'picoxcell/cleanup' into next/cleanup
* picoxcell/cleanup: (4 commits)
  MAINTAINERS: add maintainer entry for Picochip picoxcell
  ARM: picoxcell: move io mappings to common.c
  ARM: picoxcell: don't reserve irq_descs
  ARM: picoxcell: remove mach/memory.h

Conflicts:
	arch/arm/mach-at91/setup.c
2011-12-19 21:13:41 -08:00
Jean-Christophe PLAGNIOL-VILLARD 13079a7333 ARM: at91: make DBGU soc independent
we will select now the DBGU used by the soc at Kconfig level

For the DEBUG_LL and early_printk this will allow to select which DBGU to use
this will also allow to select them when multiple SOC are enabled

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2011-11-28 22:50:39 +08:00
Jean-Christophe PLAGNIOL-VILLARD f22deee523 ARM: at91: make shutdown controler soc independent
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2011-11-28 22:50:38 +08:00
Jean-Christophe PLAGNIOL-VILLARD cfa5a1fe7e ARM: at91: add ioremap_registers entry point to soc setup
this will allow to ioremap the register of the PIT, PMC and others
and make the code soc independent

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2011-11-28 22:50:38 +08:00
Nicolas Pitre cf48c02e3b ARM: mach-at91: remove arch specific special handling for ioremap
A generic version should replace this later.

Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
2011-11-15 22:30:39 -05:00
Jean-Christophe PLAGNIOL-VILLARD fb149f9e28 at91: add arch specific ioremap support
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
2011-07-28 15:09:26 +00:00
Jean-Christophe PLAGNIOL-VILLARD f0051d82a6 at91: factorize sram init
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
2011-07-28 15:07:29 +00:00
Jean-Christophe PLAGNIOL-VILLARD 51ddec7617 at91: move register clocks to soc generic init
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
2011-07-28 15:07:29 +00:00
Jean-Christophe PLAGNIOL-VILLARD 465393749d at91: move clock subsystem init to soc generic init
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
2011-07-28 15:07:29 +00:00
Jean-Christophe PLAGNIOL-VILLARD 8c3583b634 at91: use structure to store the current soc
instead of reading the registers everytime

the current implementation respect the following constrain:
 - allow 1 to n soc to be enabled
 - allow to have a virtual cpu type and subtype
 - always detect the cpu type and subtype and report it
 - detect if the soc support is enabled
 - prepare for sysfs export support
 - drop soc specific code via compiler when the soc not enabled
   (via cpu_is_xxx)

Today if we read the exid we will have the same value for 9g35 and 9m11
and we will need to check the cidr too

with the new implementation we just need to check the soc subtype

this will also allow to have specific virtual subtype for rm9200 which the
board will have to specify via at91rm9200_set_type(int) as we have no way to
detect it.

this implementation is inspired by the SH cpu detection support

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
2011-07-28 15:07:28 +00:00
Jean-Christophe PLAGNIOL-VILLARD 92100c12ca at91: factorize at91 interrupts init to soc
they are the same except the default priority

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
2011-07-28 15:07:28 +00:00
Jean-Christophe PLAGNIOL-VILLARD 21d08b9d55 at91: introduce commom AT91_BASE_SYS
On all at91 except rm9200 and x40 have the System Controller starts
at address 0xffffc000 and has a size of 16KiB.

On rm9200 it's start at 0xfffe4000 of 111KiB with non reserved data starting
at 0xfffff000

This patch removes the individual definitions of AT91_BASE_SYS and
replaces them with a common version at base 0xfffffc000 and size 16KiB
and map the same memory space

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
2011-07-28 15:07:28 +00:00