Commit Graph

3 Commits

Author SHA1 Message Date
kbuild test robot b9f1308458 staging: fix platform_no_drv_owner.cocci warnings
drivers/staging/axis-fifo/axis-fifo.c:1081:3-8: No need to set .owner here. The core will do it.

 Remove .owner field if calls are used which set it automatically

Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci

Fixes: 4a965c5f89 ("staging: add driver for Xilinx AXI-Stream FIFO v4.1 IP core")
CC: Jacob Feder <jacobsfeder@gmail.com>
Signed-off-by: kbuild test robot <fengguang.wu@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-07-29 14:40:41 +02:00
Wei Yongjun 6d4abf1c0e staging: axis-fifo: fix return value check in axis_fifo_probe()
In case of error, the function device_create() returns ERR_PTR() and
never returns NULL. The NULL test in the return value check should be
replaced with IS_ERR().

Fixes: 4a965c5f89 ("staging: add driver for Xilinx AXI-Stream FIFO v4.1 IP core")
Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-07-28 09:26:31 +02:00
Jacob Feder 4a965c5f89 staging: add driver for Xilinx AXI-Stream FIFO v4.1 IP core
This IP core has read and write AXI-Stream FIFOs, the contents of which can
be accessed from the AXI4 memory-mapped interface. This is useful for
transferring data from a processor into the FPGA fabric. The driver creates
a character device that can be read/written to with standard
open/read/write/close.

See Xilinx PG080 document for IP details.

https://www.xilinx.com/support/documentation/ip_documentation/axi_fifo_mm_s/v4_1/pg080-axi-fifo-mm-s.pdf

The driver currently supports only store-forward mode with a 32-bit
AXI4 Lite interface. DOES NOT support:
        - cut-through mode
        - AXI4 (non-lite)

Signed-off-by: Jacob Feder <jacobsfeder@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-07-24 14:14:13 +02:00