The AXG Analog MIPI-DSI PHY also provides functions to the PCIe PHY,
thus we need to have inclusive support for both interfaces at runtime.
This fixes the regmap get from parent node, removes cell param
to select a mode and implement runtime configuration & power on/off
for both functions since they are not exclusive.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Remi Pommarel <repk@triplefau.lt>
Link: https://lore.kernel.org/r/20201116101647.73448-4-narmstrong@baylibre.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
This adds support for the MIPI analog PHY which is also used for PCIE
found in the Amlogic AXG SoC Family.
MIPI or PCIE selection is done by the #phy-cells, making the mode
static and exclusive.
For now only PCIE functionality is supported.
This PHY will be used to replace the mipi_enable clock gating logic
which was mistakenly added in the clock subsystem. This also activates
a non documented band gap bit in those registers that allows reliable
PCIE clock signal generation on AXG platforms.
Signed-off-by: Remi Pommarel <repk@triplefau.lt>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Jerome Brunet <jbrunet@baylibre.com>
Neil Armstrong