Commit Graph

13 Commits

Author SHA1 Message Date
Marc Zyngier f42798c689 ARM: KVM: Fix length of mmio access
Instead of hardcoding the maximum MMIO access to be 4 bytes,
compare it to sizeof(unsigned long), which will do the
right thing on both 32 and 64bit systems.

Same thing for sign extention.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <cdall@cs.columbia.edu>
2013-03-06 16:01:51 -08:00
Marc Zyngier 23b415d61a ARM: KVM: abstract IL decoding away
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <cdall@cs.columbia.edu>
2013-03-06 15:48:43 -08:00
Marc Zyngier a7123377e7 ARM: KVM: abstract SAS decoding away
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <cdall@cs.columbia.edu>
2013-03-06 15:48:43 -08:00
Marc Zyngier b37670b0f3 ARM: KVM: abstract S1TW abort detection away
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <cdall@cs.columbia.edu>
2013-03-06 15:48:42 -08:00
Marc Zyngier 78abfcde49 ARM: KVM: abstract (and fix) external abort detection away
Bit 8 is cache maintenance, bit 9 is external abort.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <cdall@cs.columbia.edu>
2013-03-06 15:48:42 -08:00
Marc Zyngier d0adf747c9 ARM: KVM: abstract HSR_SRT_{MASK,SHIFT} away
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2013-03-06 15:48:42 -08:00
Marc Zyngier 7c511b881f ARM: KVM: abstract HSR_SSE away
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <cdall@cs.columbia.edu>
2013-03-06 15:48:42 -08:00
Marc Zyngier 023cc96406 ARM: KVM: abstract HSR_WNR away
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <cdall@cs.columbia.edu>
2013-03-06 15:48:42 -08:00
Marc Zyngier 4a1df28ac0 ARM: KVM: abstract HSR_ISV away
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <cdall@cs.columbia.edu>
2013-03-06 15:48:42 -08:00
Marc Zyngier 7393b59917 ARM: KVM: abstract fault register accesses
Instead of directly accessing the fault registers, use proper accessors
so the core code can be shared.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2013-03-06 15:48:42 -08:00
Marc Zyngier db730d8d62 ARM: KVM: convert GP registers from u32 to unsigned long
On 32bit ARM, unsigned long is guaranteed to be a 32bit quantity.
On 64bit ARM, it is a 64bit quantity.

In order to be able to share code between the two architectures,
convert the registers to be unsigned long, so the core code can
be oblivious of the change.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2013-03-06 15:48:42 -08:00
Marc Zyngier 1a89dd9113 ARM: KVM: Initial VGIC infrastructure code
Wire the basic framework code for VGIC support and the initial in-kernel
MMIO support code for the VGIC, used for the distributor emulation.

Reviewed-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2013-02-11 18:58:55 +00:00
Christoffer Dall 45e96ea6b3 KVM: ARM: Handle I/O aborts
When the guest accesses I/O memory this will create data abort
exceptions and they are handled by decoding the HSR information
(physical address, read/write, length, register) and forwarding reads
and writes to QEMU which performs the device emulation.

Certain classes of load/store operations do not support the syndrome
information provided in the HSR.  We don't support decoding these (patches
are available elsewhere), so we report an error to user space in this case.

This requires changing the general flow somewhat since new calls to run
the VCPU must check if there's a pending MMIO load and perform the write
after userspace has made the data available.

Reviewed-by: Will Deacon <will.deacon@arm.com>
Reviewed-by: Marcelo Tosatti <mtosatti@redhat.com>
Signed-off-by: Rusty Russell <rusty@rustcorp.com.au>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com>
2013-01-23 13:29:17 -05:00