Commit Graph

967451 Commits

Author SHA1 Message Date
Marek Vasut 242639c0dc dt-bindings: arm: stm32: Add compatible strings for DH SoMs and boards
Document devicetree compatible strings of the DH SoMs and boards.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-11-26 14:42:41 +01:00
Ahmad Fatoum b19d3a55d4 ARM: dts: stm32: support child mfd cells for the stm32mp1 TAMP syscon
The stm32mp1 TAMP peripheral has 32 backup registers that survive
a warm reset. This makes them suitable for storing a reboot
mode, which the vendor's kernel tree is already doing[0].

The actual syscon-reboot-mode child node can be added by a board.dts or
fixed up by the bootloader. For the child node to be probed, the
compatible needs to include simple-mfd. The binding now specifies this,
so have the SoC dtsi adhere to it.

[0]: https://github.com/STMicroelectronics/linux/commit/2e9bfc29dd

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-11-26 14:42:41 +01:00
Ahmad Fatoum 82765d1495 dt-bindings: arm: stm32: add simple-mfd compatible for tamp node
The stm32mp1 TAMP (Tamper and backup registers) does tamper detection
and features 32 backup registers that, being in the RTC domain, may
survive even with Vdd switched off.

This makes it suitable for use to communicate a reboot mode from OS
to bootloader via the syscon-reboot-mode binding. Add a "simple-mfd"
to support probing such a child node. The actual reboot mode
node could then be defined in a board.dts or fixed up by the bootloader.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-11-26 14:42:41 +01:00
Arnaud Pouliquen 4c903a9464 ARM: dts: stm32: update stm32mp151 for remote proc synchronization support
Two backup registers are used to store the Cortex-M4 state and the resource
table address.
Declare the tamp node and add associated properties in m4_rproc node
to allow Linux to attach to a firmware loaded by the first boot stages.

Associated driver implementation is available in commit 9276536f45
("remoteproc: stm32: Parse syscon that will manage M4 synchronisation").

Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-11-26 14:42:41 +01:00
Amelie Delaunay d27209f04d ARM: dts: stm32: adjust USB OTG gadget fifo sizes in stm32mp151
Defaut use case on stm32mp151 USB OTG is ethernet gadget, using EP1 bulk
endpoint (MPS=512 bytes) and EP2 interrupt endpoint (MPS=16 bytes).
This patch optimizes USB OTG FIFO sizes accordingly.

Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-11-26 14:42:41 +01:00
Amelie Delaunay 7e4bc946db ARM: dts: stm32: fix dmamux reg property on stm32h743
Reg property length should cover all DMAMUX_CxCR registers.
DMAMUX_CxCR Address offset: 0x000 + 0x04 * x (x = 0 to 15), so latest
offset is at 0x3c, so length should be 0x40.

Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-11-26 14:42:41 +01:00
Amelie Delaunay e3b37ca311 ARM: dts: stm32: fix dmamux reg property on stm32mp151
Reg property length should cover all DMAMUX_CxCR registers.
DMAMUX_CxCR Address offset: 0x000 + 0x04 * x (x = 0 to 15), so latest
offset is at 0x3c, so length should be 0x40.

Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-11-26 14:42:41 +01:00
Amelie Delaunay fc082d2bb2 ARM: dts: stm32: fix mdma1 clients channel priority level on stm32mp151
Update mdma1 clients channel priority level following stm32-mdma bindings.

Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-11-26 14:42:41 +01:00
Amelie Delaunay 83686162c0 ARM: dts: stm32: add STUSB1600 Type-C using I2C4 on stm32mp15xx-dkx
This patch adds support for STUSB1600 USB Type-C port controller, used on
I2C4 on stm32mp15xx-dkx.
The default configuration on this board, on Type-C connector, is:
- Dual Power Role (DRP), so set power-role to "dual";
- Vbus limited to 500mA, so set typec-power-opmode to "default" (it means
  500mA in USB 2.0).
typec-power-opmode is used to reconfigure the STUSB1600 advertising of
current capability when its NVM is not in line with the board layout.
On stm32mp15xx-dkx, Vbus power source of STUSB1600 is 5V_VIN. So power
operation mode depends on the power supply used. To avoid any power
issues, it is better to limit Vbus to 500mA on this board.
ALERT# is the interrupt pin of STUSB1600. It needs an external pull-up, and
signal is active low.

USB OTG controller ID and Vbus signals are not connected on stm32mp15xx-dkx
boards, so disconnection are not detected.
Without DWC2 usb-role-switch:
- if you unplug the USB cable from the Type-C port, you have to manually
disconnect the USB gadget:
echo disconnect > /sys/devices/platform/soc/49000000.usb-otg/udc/49000000.usb-otg/soft_connect
- Then you can plug the USB cable again in the Type-C port, and manually
reconnect the USB gadget:
echo connect > /sys/devices/platform/soc/49000000.usb-otg/udc/49000000.usb-otg/soft_connect
With DWC2 usb-role-switch, USB gadget is dynamically disconnected or connected.

Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-11-26 14:42:41 +01:00
Amelie Delaunay 70966729b5 dt-bindings: usb: Add DT bindings for STUSB160x Type-C controller
Add binding documentation for the STMicroelectronics STUSB160x Type-C port
controller.

Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-11-26 14:42:41 +01:00
Amelie Delaunay 8e568db602 dt-bindings: connector: add typec-power-opmode property to usb-connector
Power operation mode may depends on hardware design, so, add the optional
property typec-power-opmode for usb-c connector to select the power
operation mode capability.

Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-11-26 14:42:41 +01:00
Patrick Delaunay dc37a51b25 ARM: dts: stm32: reorder spi4 within stm32mp15-pinctrl
Move spi4 at the right alphabetical place within stm32mp15-pinctrl

Fixes: 4fe663890a ("ARM: dts: stm32: Fix spi4 pins in stm32mp15-pinctrl")
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-11-26 14:42:41 +01:00
Hugues Fruchet 096b0243fa ARM: dts: stm32: set bus-type in DCMI endpoint for stm32429i-eval board
Explicitly set bus-type to parallel mode in DCMI endpoint (bus-type=5).

Signed-off-by: Hugues Fruchet <hugues.fruchet@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-11-26 14:42:41 +01:00
Hugues Fruchet 07e3454493 ARM: dts: stm32: set bus-type in DCMI endpoint for stm32mp157c-ev1 board
Explicitly set bus-type to parallel mode in DCMI endpoint (bus-type=5).

Signed-off-by: Hugues Fruchet <hugues.fruchet@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-11-26 14:42:41 +01:00
Lionel Debieve b6aa35c739 ARM: dts: stm32: enable CRYP by default on stm32mp15
Enable CRYP1 device for cryp accelerated support on
stm32mp157C-EV1/DK2 STMicroelectronics platforms.

Signed-off-by: Nicolas Toromanoff <nicolas.toromanoff@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-11-26 14:42:41 +01:00
Nicolas Toromanoff ee0035b233 ARM: dts: stm32: enable CRC1 by default on stm32mp15
Enable CRC1 device for CRC-32 accelerated support on
stm32mp15 STMicroelectronics platforms.

Signed-off-by: Nicolas Toromanoff <nicolas.toromanoff@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-11-26 14:42:41 +01:00
Lionel Debieve 304b5691bf ARM: dts: stm32: enable HASH by default on stm32mp15
Enable HASH1 device for HASH accelerated support on
stm32mp15 STMicroelectronics platforms.

Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-11-26 14:42:41 +01:00
Fabrice Gasnier 928caf877d ARM: dts: stm32: Add LP timer wakeup-source on stm32mp151
LP timer can be used to wakeup from stop mode on stm32mp151.
Add wakeup-source properties to all LP timer instances.

Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-11-26 14:42:41 +01:00
Fabrice Gasnier f885fbca0f ARM: dts: stm32: Add LP timer irqs on stm32mp151
Add all LP timer irqs on stm32mp151.

Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-11-26 14:42:41 +01:00
Yann Gautier 08f07e9a19 ARM: dts: stm32: update sdmmc IP version for STM32MP15
Update the IP version to v2.0, which supports linked lists in internal DMA,
and is present in STM32MP1 SoCs.

The mmci driver supports the v2.0 periph id since 7a2a98be67 ("mmc: mmci:
Add support for sdmmc variant revision 2.0"), so it's now Ok to add it into
the SoC device tree to benefit from the improved DMA support.

Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-11-26 14:42:41 +01:00
Serge Semin 4f551b7bba ARM: dts: stm32: Harmonize EHCI/OHCI DT nodes name on stm32mp15
In accordance with the Generic EHCI/OHCI bindings the corresponding node
name is suppose to comply with the Generic USB HCD DT schema, which
requires the USB nodes to have the name acceptable by the regexp:
"^usb(@.*)?" . Make sure the "generic-ehci" and "generic-ohci"-compatible
nodes are correctly named.

Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Acked-by: Amelie Delaunay <amelie.delaunay@st.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-11-26 14:42:41 +01:00
Matthias Kaehlcke 066c2a9448 arm64: dts: qcom: sc7180-trogdor: Make pp3300_a the default supply for pp3300_hub
The trogdor design has two options for supplying the 'pp3300_hub' power
rail, it can be supplied by 'pp3300_l7c' or 'pp3300_a'. The 'pp3300_a'
path includes a load switch that can be controlled through GPIO84.
Initially trogdor boards used 'pp3300_l7c' to power the USB hub, newer
revisions (will) use 'pp3300_a' as supply for 'pp3300_hub'.

Add a DT node for the 'pp3300_a' path and a pinctrl entry for the GPIO.
Make this path the default and keep trogdor rev1, lazor rev0 and rev1
on 'pp3300_l7c'. These earlier revisions also allocated the GPIO to the
purpose of controlling the power switch, so there is no need to limit
the pinctrl config to newer revisions. Remove the platform-wide
'always/boot-on' properties from 'pp3300_l7c' and add them to the
boards that use this supply. Also delete the 'always/boot-on'
properties of 'pp3300_hub' for these boards.

Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20201124164714.v4.1.I0ed4abdd2b2916fbedf76be254bc3457fb8b9655@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-11-25 18:07:40 -06:00
Rafał Miłecki dccb22d078 arm64: add config for Broadcom BCM4908 SoCs
Add ARCH_BCM4908 config that can be used for compiling DTS files.

Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2020-11-25 09:07:49 -08:00
Rafał Miłecki 2961f69f15 arm64: dts: broadcom: add BCM4908 and Asus GT-AC5300 early DTS files
They don't descibe hardware fully yet but it's enough to boot a system.

Some missing blocks:
1. PMC (Power Management Controller?)
2. Ethernet
3. Crypto
4. Thermal

Asus DTS is missing defining full NAND partitions layout and buttons.

Further changes will fill those gaps as soon as required bindings will
be found / tested / added.

Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2020-11-25 09:07:49 -08:00
Rafał Miłecki 2f8913a7b1 dt-bindings: arm: bcm: document BCM4908 bindings
BCM4908 is a new family that includes BCM4906, BCM4908 and BCM49408.
It's mostly used in home routers and often replaces Northstar in vendors
portfolio.

Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2020-11-25 09:07:49 -08:00
Sameer Pujar b6e136c7e6 arm64: tegra: Rename ADMA device nodes for Tegra210
DMA device nodes should follow regex pattern of "^dma-controller(@.*)?$".
This is a preparatory patch to use YAML doc format for ADMA.

Signed-off-by: Sameer Pujar <spujar@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-11-25 15:33:35 +01:00
Thierry Reding 1289bd9fec arm64: tegra: Hook up edp interrupt on Tegra132 SOCTHERM
For some reason this was never hooked up. Do it now so that over-current
interrupts can be logged.

Reported-by: Nicolas Chauvet <kwizart@gmail.com>
Suggested-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-11-25 15:33:34 +01:00
Nicolas Chauvet fdf278257e arm64: tegra: Add missing hot temperatures to Tegra210 thermal-zones
According to dmesg, thermal-zones for mem and cpu are missing hot
temperatures properties.

  throttrip: pll: missing hot temperature
...
  throttrip: mem: missing hot temperature
...

Adding them will clear the messages.

Signed-off-by: Nicolas Chauvet <kwizart@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-11-25 15:33:34 +01:00
Nicolas Chauvet 3146cd55b0 arm64: tegra: Add missing gpu-throt-level to Tegra210 soctherm
On Jetson TX1 the following message can be seen:

 tegra_soctherm 700e2000.thermal-sensor: throttle-cfg: heavy: no throt prop or invalid prop

This patch will fix the invalid prop issue according to the binding.

Signed-off-by: Nicolas Chauvet <kwizart@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-11-25 15:33:34 +01:00
Nicolas Chauvet 5aaa0de991 arm64: tegra: Add missing hot temperatures to Tegra132 thermal-zones
According to dmesg, thermal-zones for mem and cpu are missing hot
temperatures properties.

  throttrip: pll: missing hot temperature
...
  throttrip: mem: missing hot temperature
...

Adding them will clear the messages.

Signed-off-by: Nicolas Chauvet <kwizart@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-11-25 15:33:34 +01:00
Vidya Sagar 6b26c1a034 arm64: tegra: Fix DT binding for IO High Voltage entry
Fix the device-tree entry that represents I/O High Voltage property
by replacing 'nvidia,io-high-voltage' with 'nvidia,io-hv' as the former
entry is deprecated.

Fixes: dbb72e2c30 ("arm64: tegra: Add configuration for PCIe C5 sideband signals")
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-11-25 15:33:33 +01:00
Marc Zyngier 776a3c04da arm64: tegra: Fix GIC400 missing GICH/GICV register regions
GIC400 has full support for virtualization, and yet the tegra186
DT doesn't expose the GICH/GICV regions (despite exposing the
maintenance interrupt that only makes sense for virtualization).

Add the missing regions, based on the hunch that the HW doesn't
use the CPU build-in interfaces, but instead the external ones
provided by the GIC. KVM's virtual GIC now works with this change.

Signed-off-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-11-25 15:33:33 +01:00
Marc Zyngier 3b4c137856 arm64: tegra: Add missing CPU PMUs on Tegra186
Add the description of CPU PMUs for both the Denver and A57 clusters,
which enables the perf subsystem.

Signed-off-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-11-25 15:33:33 +01:00
Jon Hunter d98bccf10d arm64: tegra: Fix Tegra234 VDK node names
When the device-tree board file was added for the Tegra234 VDK simulator
it incorrectly used the names 'cbb' and 'sdhci' instead of 'bus' and
'mmc', respectively. The names 'bus' and 'mmc' are required by the
device-tree json-schema validation tools. Therefore, fix this by
renaming these nodes accordingly.

Fixes: 639448912b ("arm64: tegra: Initial Tegra234 VDK support")
Reported-by: Ashish Singhal <ashishsingha@nvidia.com>
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-11-25 15:33:30 +01:00
Dipen Patel 1741e18737 arm64: tegra: Wrong AON HSP reg property size
The AON HSP node's "reg" property size 0xa0000 will overlap with other
resources. This patch fixes that wrong value with correct size 0x90000.

Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Dipen Patel <dipenp@nvidia.com>
Fixes: a38570c22e ("arm64: tegra: Add nodes for TCU on Tegra194")
Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-11-25 15:24:28 +01:00
JC Kuo f24a2acc15 arm64: tegra: Fix USB_VBUS_EN0 regulator on Jetson TX1
USB host mode is broken on the OTG port of Jetson TX1 platform because
the USB_VBUS_EN0 regulator (regulator@11) is being overwritten by the
vdd-cam-1v2 regulator. This commit rearranges USB_VBUS_EN0 to be
regulator@14.

Fixes: 257c8047be ("arm64: tegra: jetson-tx1: Add camera supplies")
Cc: stable@vger.kernel.org
Signed-off-by: JC Kuo <jckuo@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-11-25 15:23:41 +01:00
Jon Hunter 476e23f4c5 arm64: tegra: Correct the UART for Jetson Xavier NX
The Jetson Xavier NX board routes UARTA to the 40-pin header and UARTC
to a 12-pin debug header. The UARTs can be used by either the Tegra
Combined UART (TCU) driver or the Tegra 8250 driver. By default, the
TCU will use UARTC on Jetson Xavier NX. Currently, device-tree for
Xavier NX enables the TCU and the Tegra 8250 node for UARTC. Fix this
by disabling the Tegra 8250 node for UARTC and enabling the Tegra 8250
node for UARTA.

Fixes: 3f9efbbe57 ("arm64: tegra: Add support for Jetson Xavier NX")
Cc: stable@vger.kernel.org
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-11-25 15:23:39 +01:00
Jon Hunter fb31949693 arm64: tegra: Disable the ACONNECT for Jetson TX2
Commit ff4c371d2b ("arm64: defconfig: Build ADMA and ACONNECT driver")
enable the Tegra ADMA and ACONNECT drivers and this is causing resume
from system suspend to fail on Jetson TX2. Resume is failing because the
ACONNECT driver is being resumed before the BPMP driver, and the ACONNECT
driver is attempting to power on a power-domain that is provided by the
BPMP. While a proper fix for the resume sequencing problem is identified,
disable the ACONNECT for Jetson TX2 temporarily to avoid breaking system
suspend.

Please note that ACONNECT driver is used by the Audio Processing Engine
(APE) on Tegra, but because there is no mainline support for APE on
Jetson TX2 currently, disabling the ACONNECT does not disable any useful
feature at the moment.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-11-25 15:23:39 +01:00
Sibi Sankar 3c9c31c252 arm64: dts: qcom: sc7180: Add DDR/L3 votes for the pro variant
Add DDR/L3 bandwidth votes for the pro variant of SC7180 SoC, as it support
frequencies upto 2.5 GHz.

Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Link: https://lore.kernel.org/r/1606198876-3515-2-git-send-email-sibis@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-11-24 17:04:41 -06:00
Sibi Sankar 8fd01e01fd arm64: dts: qcom: sc7180-lite: Tweak DDR/L3 scaling on SC7180-lite
Tweak the DDR/L3 bandwidth votes on the lite variant of the SC7180 SoC
since the gold cores only support frequencies upto 2.1 GHz.

Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Link: https://lore.kernel.org/r/1606198876-3515-1-git-send-email-sibis@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-11-24 17:04:30 -06:00
Terry Hsiao d4b85bc550 arm64: dts: qcom: sc7180-trogdor: add "pen-insert" label for trogdor
Add a label to the "pen-insert" node in sc7180-trogdor.dtsi

Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Terry Hsiao <terry_hsiao@compal.corp-partner.google.com>
Link: https://lore.kernel.org/r/20201116083014.547-1-terry_hsiao@compal.corp-partner.google.com
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-11-24 17:03:30 -06:00
Antony Wang bb06eb3607 arm64: qcom: sc7180: trogdor: Add ADC nodes and thermal zone for charger thermistor
Trogdor has a thermistor to monitor the temperature of the charger IC.
Add the ADC (monitor) nodes and a thermal zone for this thermistor.

Signed-off-by: Antony Wang <antony_wang@compal.corp-partner.google.com>
[mka: tweaked commit message]
Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
Link: https://lore.kernel.org/r/20201030084840.1.If389f211a8532b83095ff8c66ec181424440f8d6@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-11-24 17:02:46 -06:00
Jishnu Prakash 7ee3eae868 arm64: dts: qcom: pm6150x: add ADC_TM definitions
Add ADC_TM peripheral definitions for PM6150 and PM6150L. Add
ADC peripheral definition for PM6150l, which is needed for ADC_TM.

Signed-off-by: Jishnu Prakash <jprakash@codeaurora.org>
Link: https://lore.kernel.org/r/1602160825-10414-2-git-send-email-jprakash@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-11-24 17:02:15 -06:00
Bjorn Andersson 95e6f8467c arm64: dts: qcom: sdm845: Limit ipa iommu streams
The Android and Windows firmware does not accept the use of 3 as a mask
to cover the IPA streams. But with 0x721 being related to WiFi and 0x723
being unsed the mapping can be reduced to just cover 0x720 and 0x722,
which is accepted.

Acked-by: Alex Elder <elder@linaro.org>
Tested-by: Alex Elder <elder@linaro.org>
Fixes: e9e89c45bf ("arm64: dts: sdm845: add IPA iommus property")
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20201123052305.157686-1-bjorn.andersson@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-11-24 13:48:05 -06:00
Jonathan Marek e9fd12df32 arm64: dts: qcom: fix indentation error in sm8250 cpu nodes
Use tabs instead of 6 spaces.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Link: https://lore.kernel.org/r/20201123144016.19596-1-jonathan@marek.ca
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-11-24 10:57:50 -06:00
Jonathan Marek c5a0609b06 arm64: dts: qcom: sm8150-mtp: Enable WiFi node
Enable the WiFi node and specify its supply regulators.

Reviewed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
[bjorn: Extracted patch from larger HDK patch]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20201121055808.582401-2-bjorn.andersson@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-11-24 09:33:25 -06:00
Jonathan Marek 05090bb9e5 arm64: dts: qcom: sm8150: Add wifi node
Add a node for the WCN3990 WiFi module.

Reviewed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
[bjorn: Extracted patch from larger "misc" patch, added qdss clock]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20201121055808.582401-1-bjorn.andersson@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-11-24 09:33:21 -06:00
Bjorn Andersson 036e110925 arm64: dts: qcom: sm8150-mtp: Specify remoteproc firmware
Point the various remoteprocs of SM8150 MTP to a place with the platform
specific firmware.

Reviewed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20201121055603.582281-1-bjorn.andersson@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-11-24 09:33:05 -06:00
Michael Klein 036b7334ee
ARM: dts: sun8i-h2-plus-bananapi-m2-zero: add gpio-line-names
Add gpio-line-names as documented in the Banana Pi wiki [1] and in the
schematics [2].

[1]: http://wiki.banana-pi.org/Banana_Pi_BPI-M2_ZERO#GPIO_PIN_define
[2]: https://drive.google.com/file/d/0B4PAo2nW2KfnMW5sVkxWSW9qa28/view

Signed-off-by: Michael Klein <michael@fossekall.de>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20201123114535.1605939-1-michael@fossekall.de
2020-11-24 15:24:59 +01:00
Stephen Boyd 4785cff7cb arm64: dts: sdm845: Add iommus property to qup
The SMMU that sits in front of the QUP needs to be programmed properly
so that the i2c geni driver can allocate DMA descriptors. Failure to do
this leads to faults when using devices such as an i2c touchscreen where
the transaction is larger than 32 bytes and we use a DMA buffer.

arm-smmu 15000000.iommu: Unexpected global fault, this could be serious
arm-smmu 15000000.iommu:         GFSR 0x00000002, GFSYNR0 0x00000002, GFSYNR1 0x000006c0, GFSYNR2 0x00000000

Add the right SID and mask so this works.

Reviewed-by: Vinod Koul <vkoul@kernel.org>
Tested-by: Caleb Connolly <caleb@connolly.tech>
Tested-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
[bjorn: Define for second QUP as well, be more specific in sdm845.dtsi]
Link: https://lore.kernel.org/r/20201122034149.626045-1-bjorn.andersson@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-11-24 08:08:10 -06:00