Commit Graph

6 Commits

Author SHA1 Message Date
Chris Metcalf cd6f32aa08 arch/tile: support <asm/cachectl.h> header for cacheflush() syscall
We already had a syscall that did some dcache flushing, but it was
not used in practice.  Make it MIPS compatible instead so it can
do both the DCACHE and ICACHE actions.  We have code that wants to
be able to use the ICACHE flush mode from userspace so this change
enables that.

Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
2012-05-25 12:48:24 -04:00
Chris Metcalf d5d14ed6f2 arch/tile: Allow tilegx to build with either 16K or 64K page size
This change introduces new flags for the hv_install_context()
API that passes a page table pointer to the hypervisor.  Clients
can explicitly request 4K, 16K, or 64K small pages when they
install a new context.  In practice, the page size is fixed at
kernel compile time and the same size is always requested every
time a new page table is installed.

The <hv/hypervisor.h> header changes so that it provides more abstract
macros for managing "page" things like PFNs and page tables.  For
example there is now a HV_DEFAULT_PAGE_SIZE_SMALL instead of the old
HV_PAGE_SIZE_SMALL.  The various PFN routines have been eliminated and
only PA- or PTFN-based ones remain (since PTFNs are always expressed
in fixed 2KB "page" size).  The page-table management macros are
renamed with a leading underscore and take page-size arguments with
the presumption that clients will use those macros in some single
place to provide the "real" macros they will use themselves.

I happened to notice the old hv_set_caching() API was totally broken
(it assumed 4KB pages) so I changed it so it would nominally work
correctly with other page sizes.

Tag modules with the page size so you can't load a module built with
a conflicting page size.  (And add a test for SMP while we're at it.)

Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
2012-05-25 12:48:24 -04:00
Chris Metcalf aeddea5d37 arch/tile: add the <arch> headers to the set of installed kernel headers
These headers are similar to the <asm> headers that describe kernel
APIs, but instead describe aspects of the actual hardware in an
OS- and application-independent manner.  We need to include them in
the set of installed headers so that userspace tools (including glibc)
can build purely from the provided kernel headers.

Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
2011-11-03 16:58:48 -04:00
Chris Metcalf 2c007a9d8c tile: use generic-y format for one-line asm-generic headers
This lets us remove a lot of one-line wrapper header files.
See commit d8ecc5cd8e for context.

Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
2011-06-03 17:36:18 -04:00
Chris Metcalf 9ff27fdbd5 arch/tile: export <asm/hardwall.h> to userspace
This should have been as part of the initial hardwall submission to
LKML but was overlooked.  The header provides the ioctl definitions for
manipulating the hardwall fd, so needs to be available to userspace.

Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
2011-03-01 16:20:23 -05:00
Chris Metcalf 867e359b97 arch/tile: core support for Tilera 32-bit chips.
This change is the core kernel support for TILEPro and TILE64 chips.
No driver support (except the console driver) is included yet.

This includes the relevant Linux headers in asm/; the low-level
low-level "Tile architecture" headers in arch/, which are
shared with the hypervisor, etc., and are build-system agnostic;
and the relevant hypervisor headers in hv/.

Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: FUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp>
Reviewed-by: Paul Mundt <lethal@linux-sh.org>
2010-06-04 17:11:18 -04:00