The DMA params for McASP with FIFO has been updated so that it works for
various FIFO levels. A member- 'fifo_level' has been added to the DMA
params data structure. The fifo_level can be adjusted by the tx[rx]_numevt
platform data. This is relevant only for DA8xx/OMAP-L1xx platforms. This
implementation has been tested for numevt values 1, 2, 4, 8.
Signed-off-by: Chaithrika U S <chaithrika@ti.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
This patch removes references to cpu_dai->dma_data.
It makes struct davinci_pcm_dma_params part of
struct davinci_mcbsp_dev or struct davinci_audio_dev.
It removes the unused name variable from davinci_pcm_dma_params.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
On DA830/OMAP-L137 and DA850/OMAP-L138 SoCs, the McASP peripheral has FIFO
support. This FIFO provides additional data buffering. It also provides
tolerance to variation in host/DMA controller response times.
The read and write FIFO sizes are 256 bytes each. If FIFO is enabled,
the DMA events from McASP are sent to the FIFO which in turn sends DMA requests
to the host CPU according to the thresholds programmed.
More details of the FIFO operation can be found at
http://focus.ti.com/general/docs/lit/getliterature.tsp?literatureNumber=
sprufm1&fileType=pdf
This patch adds support for FIFO configuration. The platform data has a
version field which differentiates the McASP on different SoCs.
Signed-off-by: Chaithrika U S <chaithrika@ti.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Adds driver support for the two instances of McASP on TI's DM646x.
The multichannel audio serial port (McASP) functions as a general-purpose audio
serial port optimized for the needs of multichannel audio application.
(http://www.ti.com/litv/pdf/spruer1b).
There are two instances of McASP on DM646x. The McASP0 module includes up to 4
serializers that can be individually enabled to either transmit or receive
in different modes. The McASP1 module is limited with only 1 pinned-out
serializer that can be enabled to only transmit in DIT mode (neither receiving
in any mode nor transmitting in either Burst or TDM mode is supported).
McASP0 consists of transmit and receive sections that may operate
synchronized, or completely independently with separate master clocks, bit
clocks, and frame syncs, and using different transmit modes with different
bit-stream formats.
Signed-off-by: Steve Chen <schen@mvista.com>
Signed-off-by: Pavel Kiryukhin <pkiryukhin@ru.mvista.com>
Signed-off-by: Naresh Medisetty <naresh@ti.com>
Signed-off-by: Chaithrika U S <chaithrika@ti.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Chaithrika U S