Commit Graph

13036 Commits

Author SHA1 Message Date
Arnd Bergmann 0db5ee73df Texas Instruments K3 SoC family changes for v5.7
- Add missing clocks to dwc3 nodes on am65x (fixes USB)
 - Add DMA entries for main_spi0 on am65x
 - Add phy-gmii-sel nodes for both am65x and j721e (towards ethernet
   support)
 - Add DMA entries for ADC for both am65x and j721e
 - Add MCU system control module on j721e (needed by phy-gmii-sel)
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Merge tag 'ti-k3-soc-for-v5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux into arm/dt

Texas Instruments K3 SoC family changes for v5.7

- Add missing clocks to dwc3 nodes on am65x (fixes USB)
- Add DMA entries for main_spi0 on am65x
- Add phy-gmii-sel nodes for both am65x and j721e (towards ethernet
  support)
- Add DMA entries for ADC for both am65x and j721e
- Add MCU system control module on j721e (needed by phy-gmii-sel)

* tag 'ti-k3-soc-for-v5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux:
  arm64: dts: ti: k3-j721e-mcu: add scm node and phy-gmii-sel nodes
  arm64: dts: ti: k3-am65-mcu: add phy-gmii-sel node
  arm64: dts: ti: k3-am65-mcu: Add DMA entries for ADC
  arm64: dts: ti: k3-am65-main: Add DMA entries for main_spi0
  arm64: dts: ti: k3-j721e-mcu-wakeup: Add DMA entries for ADC
  arm64: dts: ti: k3-am65: Add clocks to dwc3 nodes

Link: https://lore.kernel.org/r/4b6b7804-4bcb-07ba-5e76-6a411e1f457f@ti.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-03-25 22:25:04 +01:00
Arnd Bergmann c1cf2b3d63 SoCFPGA DTS updates for v5.7
- Increase NAND boot partition for Arria10
 - Increase QSPI partition for Stratix10 and Agilex
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Merge tag 'socfpga_dts_update_for_v5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into arm/dt

SoCFPGA DTS updates for v5.7
- Increase NAND boot partition for Arria10
- Increase QSPI partition for Stratix10 and Agilex

* tag 'socfpga_dts_update_for_v5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
  arm64: dts: increase the QSPI reg address for Stratix10 and Agilex
  ARM: dts: socfpga: arria10: Increase boot partition size for NAND

Link: https://lore.kernel.org/r/20200318145957.30338-1-dinguyen@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-03-25 22:23:50 +01:00
Arnd Bergmann a95e12db9e i.MX arm64 DTS update for 5.7:
- New support for Kontron LS1028A based boards and NXP i.MX8MP EVK.
  - Add Ethernet PHY reset GPIO for imx8mm-evk and imx8mq-evk board.
  - Add gpio-fan, thermal and Ethernet support for imx8mq-phanbell board.
  - Add SNVS clock description to pwrkey device for i.MX8 SoCs.
  - A number of updates on librem5-devkit board to add audio, proximity
    sensor, lsm9ds1 mount matrix support, and improve WoWWAN, DVFS, SD
    devices as well.
  - A series of patches from Anson Huang to update i.MX8 EVK boards
    for support of I2C PCA6416, thermal, GPIO LED, OPP table etc.
  - Add PCIe device nodes for LX2160A and LS1028A SoC.
  - Add FSPI deivce support for LX2160A evaluation boards.
  - Add EEPROM and LTC3882 regulator support for lx2160a-cex7 board.
  - Other small and random updates on LS1028A and i.MX8 support.
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Merge tag 'imx-dt64-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt

i.MX arm64 DTS update for 5.7:

 - New support for Kontron LS1028A based boards and NXP i.MX8MP EVK.
 - Add Ethernet PHY reset GPIO for imx8mm-evk and imx8mq-evk board.
 - Add gpio-fan, thermal and Ethernet support for imx8mq-phanbell board.
 - Add SNVS clock description to pwrkey device for i.MX8 SoCs.
 - A number of updates on librem5-devkit board to add audio, proximity
   sensor, lsm9ds1 mount matrix support, and improve WoWWAN, DVFS, SD
   devices as well.
 - A series of patches from Anson Huang to update i.MX8 EVK boards
   for support of I2C PCA6416, thermal, GPIO LED, OPP table etc.
 - Add PCIe device nodes for LX2160A and LS1028A SoC.
 - Add FSPI deivce support for LX2160A evaluation boards.
 - Add EEPROM and LTC3882 regulator support for lx2160a-cex7 board.
 - Other small and random updates on LS1028A and i.MX8 support.

* tag 'imx-dt64-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (63 commits)
  arm64: dts: ls1028a: disable the felix switch by default
  arm64: dts: imx8mp: Add snvs clock to powerkey
  arm64: dts: imx8mn: Add snvs clock to powerkey
  arm64: dts: ls1028a: Add PCIe controller DT nodes
  arm64: dts: ls1028a: sl28: add support for variant 2
  arm64: dts: ls1028a: sl28: expose switch ports in KBox A-230-LS
  arm64: dts: ls1028a: sl28: fix on-board EEPROMS
  arm64: dts: freescale: sl28: add SPI flash
  arm64: dts: imx8m: fix aips dts node
  arm64: dts: imx8mn: Add CPU thermal zone support
  arm64: dts: imx8mm: Add thermal zone support
  arm64: dts: imx8mq-phanbell: Fix Ethernet PHY post-reset duration
  arm64: dts: enable fspi in imx8mm dts
  arm64: dts: imx8mn: align name for crypto child nodes
  arm64: dts: lx2160aqds: Add FSPI node properties
  arm64: dts: lx2160ardb: Update FSPI node properties
  arm64: dts: imx8mq-phanbell: Add gpio-fan/thermal support
  arm64: dts: layerscape: add iommu-map property to pci nodes
  arm64: dts: imx8mp-evk: Enable pca6416 on i2c3 bus
  arm64: dts: imx8mp-evk: Add i2c3 support
  ...

Link: https://lore.kernel.org/r/20200318051918.32579-5-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-03-25 22:22:48 +01:00
Arnd Bergmann b3d0ee51c2 UniPhier ARM64 SoC DT updates for v5.7
- Rename nodes to avoid dt-schema warnings
 
 - Enable SPI for PXs3 reference board
 
 - Enable thermal monitor for PXs3 SoC
 
 - Fix clock and reset of SPI nodes
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Merge tag 'uniphier-dt64-v5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier into arm/dt

UniPhier ARM64 SoC DT updates for v5.7

- Rename nodes to avoid dt-schema warnings

- Enable SPI for PXs3 reference board

- Enable thermal monitor for PXs3 SoC

- Fix clock and reset of SPI nodes

* tag 'uniphier-dt64-v5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier:
  arm64: dts: uniphier: Set SCSSI clock and reset IDs for each channel
  arm64: dts: uniphier: Add nodes of thermal monitor and thermal zone for PXs3
  arm64: dts: uniphier: Enable spi node for PXs3 reference board
  arm64: dts: uniphier: rename NAND node names to follow json-schema
  arm64: dts: uniphier: rename aidet node names to follow json-schema
  arm64: dts: uniphier: change SD/eMMC node names to follow json-schema

Link: https://lore.kernel.org/r/CAK7LNASMD-zqNfG02WhU1LeAJevnjBv=oT2N_7y6C8w7kryotQ@mail.gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-03-25 22:19:05 +01:00
Arnd Bergmann 80e7f21d19 arm64: dts: Amlogic updates for v5.7
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Merge tag 'amlogic-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into arm/dt

arm64: dts: Amlogic updates for v5.7
 - sound, bluetooth, thermal updates
 - A1: add secure power domain nodes
 - misc. cleanups

* tag 'amlogic-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic:
  arm64: dts: meson: add thermal zones to meson gx devices
  arm64: dts: meson: khadas-vim3: move model to g12b-khadas-vim3 dtsi
  arm64: dts: meson-g12b: fix N2/VIM3 audio card model names
  arm64: dts: meson-gxbb-vega-s95: fix bluetooth node
  arm64: dts: meson-gxl-s905x-p212: add bluetooth nodes
  arm64: dts: meson-gxbb-odroid-c2: add rc-odroid ir keymap
  arm64: dts: meson: fix gxm-khadas-vim2 wifi
  arm64: dts: meson: sei510: fix sound card codec node
  arm64: dts: meson: s400: fix sound card codec nodes
  arm64: dts: meson: add pdm reset line
  arm64: dts: g12-common: add parkmode_disable_ss_quirk on DWC3 controller
  arm64: dts: amlogic: add rc-videostrong-kii-pro keymap
  arm64: dts: meson: a1: add secure power domain controller

Link: https://lore.kernel.org/r/7hlfo0ugnj.fsf@baylibre.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-03-25 22:03:27 +01:00
Arnd Bergmann 8e2d11360d Support for the rk3399-based Pinebook Pro, eDP support and power-tree for
the rk3399 evaluation board, a big number of fixes for issues found by
 checking against the new yaml dt-bindings.
 And on the smaller side, fixes for network transfers, the mute gpio
 on rk3328 gets actually described and one lvds fix on the px30 and
 the rk3399-hugsun board gets IR and power led.
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Merge tag 'v5.7-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt

Support for the rk3399-based Pinebook Pro, eDP support and power-tree for
the rk3399 evaluation board, a big number of fixes for issues found by
checking against the new yaml dt-bindings.
And on the smaller side, fixes for network transfers, the mute gpio
on rk3328 gets actually described and one lvds fix on the px30 and
the rk3399-hugsun board gets IR and power led.

* tag 'v5.7-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (27 commits)
  arm64: dts: rockchip: Add Hugsun X99 power led
  arm64: dts: rockchip: Add Hugsun X99 IR receiver
  arm64: dts: rockchip: remove clock-names property from 'generic-ohci' nodes
  arm64: dts: rockchip: remove clock-names property from 'generic-ehci' nodes
  arm64: dts: rockchip: remove properties from spdif node RK3399 Excavator
  arm64: dts: add bus to rockchip amba nodenames
  arm64: dts: rockchip: replace clock-freq-min-max by max-frequency
  arm64: dts: rockchip: fix vqmmc-supply property name for rk3399 puma
  arm64: dts: remove no-emmc from mmc node for Rockchip PX5 EVB
  arm64: dts: rockchip: remove rockchip,grf from vop nodes for px30
  arm64: dts: rockchip: remove max-freq from &spi1 node for Hugsun X99
  arm64: dts: rockchip: fix compatible property for rk3399-evb
  arm64: dts: rockchip: Add initial support for Pinebook Pro
  dt-bindings: Add doc for Pine64 Pinebook Pro
  arm64: dts: rockchip: Enable eDP display on rk3399 evb
  arm64: dts: rockchip: remove enable-gpio of backlight on rk3399 evb
  arm64: dts: rockchip: Add pmic dt tree for rk3399 evb
  arm64: dts: rockchip: remove dvs2 pinctrl for pmic on rk3399 evb
  arm64: dts: rockchip: fix px30 lvds ports
  arm64: dts: rockchip: Add txpbl node for RK3399/RK3328
  ...

Link: https://lore.kernel.org/r/27799037.pT45f1LVdF@phil
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-03-25 22:01:57 +01:00
Linus Torvalds 1b649e0bca Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
Pull networking fixes from David Miller:

 1) Fix deadlock in bpf_send_signal() from Yonghong Song.

 2) Fix off by one in kTLS offload of mlx5, from Tariq Toukan.

 3) Add missing locking in iwlwifi mvm code, from Avraham Stern.

 4) Fix MSG_WAITALL handling in rxrpc, from David Howells.

 5) Need to hold RTNL mutex in tcindex_partial_destroy_work(), from Cong
    Wang.

 6) Fix producer race condition in AF_PACKET, from Willem de Bruijn.

 7) cls_route removes the wrong filter during change operations, from
    Cong Wang.

 8) Reject unrecognized request flags in ethtool netlink code, from
    Michal Kubecek.

 9) Need to keep MAC in reset until PHY is up in bcmgenet driver, from
    Doug Berger.

10) Don't leak ct zone template in act_ct during replace, from Paul
    Blakey.

11) Fix flushing of offloaded netfilter flowtable flows, also from Paul
    Blakey.

12) Fix throughput drop during tx backpressure in cxgb4, from Rahul
    Lakkireddy.

13) Don't let a non-NULL skb->dev leave the TCP stack, from Eric
    Dumazet.

14) TCP_QUEUE_SEQ socket option has to update tp->copied_seq as well,
    also from Eric Dumazet.

15) Restrict macsec to ethernet devices, from Willem de Bruijn.

16) Fix reference leak in some ethtool *_SET handlers, from Michal
    Kubecek.

17) Fix accidental disabling of MSI for some r8169 chips, from Heiner
    Kallweit.

* git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net: (138 commits)
  net: Fix CONFIG_NET_CLS_ACT=n and CONFIG_NFT_FWD_NETDEV={y, m} build
  net: ena: Add PCI shutdown handler to allow safe kexec
  selftests/net/forwarding: define libs as TEST_PROGS_EXTENDED
  selftests/net: add missing tests to Makefile
  r8169: re-enable MSI on RTL8168c
  net: phy: mdio-bcm-unimac: Fix clock handling
  cxgb4/ptp: pass the sign of offset delta in FW CMD
  net: dsa: tag_8021q: replace dsa_8021q_remove_header with __skb_vlan_pop
  net: cbs: Fix software cbs to consider packet sending time
  net/mlx5e: Do not recover from a non-fatal syndrome
  net/mlx5e: Fix ICOSQ recovery flow with Striding RQ
  net/mlx5e: Fix missing reset of SW metadata in Striding RQ reset
  net/mlx5e: Enhance ICOSQ WQE info fields
  net/mlx5_core: Set IB capability mask1 to fix ib_srpt connection failure
  selftests: netfilter: add nfqueue test case
  netfilter: nft_fwd_netdev: allow to redirect to ifb via ingress
  netfilter: nft_fwd_netdev: validate family and chain type
  netfilter: nft_set_rbtree: Detect partial overlaps on insertion
  netfilter: nft_set_rbtree: Introduce and use nft_rbtree_interval_start()
  netfilter: nft_set_pipapo: Separate partial and complete overlap cases on insertion
  ...
2020-03-25 13:58:05 -07:00
Arnd Bergmann 19a71cf494 mvebu dt64 for 5.7 (part 1)
Improve network support on two Armada 8040 based board:
 Clearfog GT 8 and Macchiatobin.
 
 Add ethernet alias on Espressobin for U-Boot support.
 
 Fix various dt compilation issue or warning.
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Merge tag 'mvebu-dt64-5.7-1' of git://git.infradead.org/linux-mvebu into arm/dt

mvebu dt64 for 5.7 (part 1)

Improve network support on two Armada 8040 based board:
Clearfog GT 8 and Macchiatobin.

Add ethernet alias on Espressobin for U-Boot support.

Fix various dt compilation issue or warning.

* tag 'mvebu-dt64-5.7-1' of git://git.infradead.org/linux-mvebu:
  arm64: dts: marvell: Fix cpu compatible for AP807-quad
  arm64: dts: marvell: fix non-existed cpu referrence in armada-ap806-dual.dtsi
  arm64: dts: marvell: build ESPRESSObin variants
  arm64: dts: marvell: espressobin: indicate dts version
  arm64: dts: marvell: espressobin: add ethernet alias
  arm64: dts: mcbin: support 2W SFP modules
  arm64: dts: clearfog-gt-8k: set gigabit PHY reset deassert delay

Link: https://lore.kernel.org/r/87h7yqx7w2.fsf@FE-laptop
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-03-25 21:49:11 +01:00
Arnd Bergmann c661d66ca1 arm64: tegra: Device tree changes for v5.7-rc1
These changes add support for the XUSB pad controller, as well as the
 XUSB controller on Tegra194. Furthermore, USB device mode is supported
 across Tegra210 and Tegra186 boards. PCIe endpoint mode support is added
 for the Jetson AGX Xavier platform.
 
 Various minor fixes eliminate warnings on boot related to missing power
 supplies for some devices.
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Merge tag 'tegra-for-5.7-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt

arm64: tegra: Device tree changes for v5.7-rc1

These changes add support for the XUSB pad controller, as well as the
XUSB controller on Tegra194. Furthermore, USB device mode is supported
across Tegra210 and Tegra186 boards. PCIe endpoint mode support is added
for the Jetson AGX Xavier platform.

Various minor fixes eliminate warnings on boot related to missing power
supplies for some devices.

* tag 'tegra-for-5.7-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  arm64: tegra: Add support for PCIe endpoint mode in P2972-0000 platform
  arm64: tegra: Add PCIe endpoint controllers nodes for Tegra194
  arm64: tegra: Add ethernet alias on Jetson TX1
  arm64: tegra: Populate LP8557 backlight regulator
  arm64: tegra: Fix Tegra186 SOR supply
  arm64: tegra: Add EEPROM supplies
  arm64: tegra: Enable I2C controller for EEPROM
  arm64: tegra: smaug: Change clk_out_2 provider to PMC
  arm64: tegra: Add clock-cells property to Tegra PMC node
  arm64: tegra: Enable XUDC node on Jetson Nano
  arm64: tegra: Update OTG port entries for Jetson Nano
  arm64: tegra: Enable XUDC node on Jetson TX2
  arm64: tegra: Add XUDC node for Tegra186
  arm64: tegra: Enable XUDC on Jetson TX1
  arm64: tegra: Add XUDC node for Tegra210
  arm64: tegra: Update OTG port entries for Jetson TX2
  arm64: tegra: Update OTG port entries for Jetson TX1
  arm64: tegra: Enable XUSB host in P2972-0000 board
  arm64: tegra: Add XUSB and pad controller on Tegra194
  arm64: tegra: Fix Tegra194 PCIe compatible string

Link: https://lore.kernel.org/r/20200313165848.2915133-8-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-03-25 21:48:18 +01:00
Arnd Bergmann 72680fbe5e Renesas ARM64 DT updates for v5.7 (take two)
- Thermal support for R-Car M3-W+,
   - Support for the M3ULCB board with R-Car M3-W+,
   - CPUIdle support for R-Car M3-N and E3,
   - Display support for the HiHope RZ/G2M board,
   - A minor fix.
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Merge tag 'renesas-arm64-dt-for-v5.7-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt

Renesas ARM64 DT updates for v5.7 (take two)

  - Thermal support for R-Car M3-W+,
  - Support for the M3ULCB board with R-Car M3-W+,
  - CPUIdle support for R-Car M3-N and E3,
  - Display support for the HiHope RZ/G2M board,
  - A minor fix.

* tag 'renesas-arm64-dt-for-v5.7-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
  arm64: dts: renesas: Add HiHope RZ/G2M board with idk-1110wr display
  arm64: dts: renesas: r8a77990: Add CPUIdle support for CA53 cores
  arm64: dts: renesas: r8a77965: Add CPUIdle support for CA57 cores
  arm64: dts: renesas: r8a77961: salvator-xs: Fix memory unit-address
  arm64: dts: renesas: Add support for M3ULCB with R-Car M3-W+
  arm64: dts: renesas: r8a77961: Add thermal nodes

Link: https://lore.kernel.org/r/20200313154304.1636-3-geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-03-25 21:43:28 +01:00
Arnd Bergmann d29600ae8c Allwinner Device Tree Changes for v5.7
A fairly large set of changes for v5.7, including some new devices.
 
 SoC specific changes:
 
   - SPI on H6 SoC enabled
   - Thermal sensor on R40 SoC enabled
   - Deinterlace core hardware on A64 SoC enabled
   - Redundant assigned-clocks properties removed
     - required clock rates are now enforced by drivers
   - LVDS panel support on A20 SoC enabled
   - PMU compatible fixed for H5 and H6 SoCs
   - Thermal trip points added for A83T and H5 SoCs
   - (Image) Rotation core hardware on A83T and A64 SoCs enabled
 
 Device specific changes:
 
   - Pine64 PineTab and PinePhone added
   - Various cleanups and improvements for Pine64 PineBook
   - GPIO pin bank regulator supplies added for A64-OlinXino
   - eMMC enabled on Orange Pi 3
   - PocketBook Touch Lux 3 added
   - Linutronix Testbox v2 added
   - Ethernet enabled on Orange Pi One Plus
   - HDMI enabled on H6-based Orange Pi boards
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Merge tag 'sunxi-dt-for-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/dt

Allwinner Device Tree Changes for v5.7

A fairly large set of changes for v5.7, including some new devices.

SoC specific changes:

  - SPI on H6 SoC enabled
  - Thermal sensor on R40 SoC enabled
  - Deinterlace core hardware on A64 SoC enabled
  - Redundant assigned-clocks properties removed
    - required clock rates are now enforced by drivers
  - LVDS panel support on A20 SoC enabled
  - PMU compatible fixed for H5 and H6 SoCs
  - Thermal trip points added for A83T and H5 SoCs
  - (Image) Rotation core hardware on A83T and A64 SoCs enabled

Device specific changes:

  - Pine64 PineTab and PinePhone added
  - Various cleanups and improvements for Pine64 PineBook
  - GPIO pin bank regulator supplies added for A64-OlinXino
  - eMMC enabled on Orange Pi 3
  - PocketBook Touch Lux 3 added
  - Linutronix Testbox v2 added
  - Ethernet enabled on Orange Pi One Plus
  - HDMI enabled on H6-based Orange Pi boards

* tag 'sunxi-dt-for-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: (46 commits)
  arm64: dts: allwinner: a64: add node for rotation core
  ARM: dts: sun8i: a83t: Add device node for rotation core
  arm64: dts: allwinner: a64: Fix display clock register range
  ARM: dts: sunxi: Fix DE2 clocks register range
  arm64: dts: allwinner: h6: orangepi: Enable HDMI
  arm64: dts: allwinner: h6: orangepi-one-plus: Enable ethernet
  arm64: dts: allwinner: h6: Move ext. oscillator to board DTs
  arm64: dts: allwinner: Add initial support for Pine64 PinePhone
  dt-bindings: arm: sunxi: Add PinePhone 1.0 and 1.1 bindings
  arm64: dts: sun50i-a64: Add i2c2 pins
  ARM: dts: sunxi: h3/h5: add r_pwm node
  arm64: allwinner: a64: enable LCD-related hardware for Pinebook
  ARM: dts: sun8i-a83t: Add thermal trip points/cooling maps
  ARM: dts: sun8i-h3: Add thermal trip points/cooling maps
  arm64: dts: allwinner: h6: Fix PMU compatible
  arm64: dts: allwinner: h5: Fix PMU compatible
  ARM: dts: sun8i-a83t-tbs-a711: Drop superfluous dr_mode
  arm64: dts: sun50i-h5-orange-pi-pc2: Add CPUX voltage regulator
  ARM: dts: sun5i: Add PocketBook Touch Lux 3 support
  dt-bindings: arm: sunxi: Add PocketBook Touch Lux 3
  ...

Link: https://lore.kernel.org/r/20200313055459.GA19820@wens.csie.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-03-25 21:42:03 +01:00
Chunyan Zhang 2cedfe1247 arm64: dts: specify console via command line
The SPRD serial driver need to know which serial port would be used as
console in an early period during initialization, otherwise console
init would fail since we added this feature[1].

So this patch add console to command line via devicetree.

[1] https://lore.kernel.org/lkml/20190826072929.7696-4-zhang.lyra@gmail.com/

Link: https://lore.kernel.org/r/20200311112120.30890-1-zhang.lyra@gmail.com
Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-03-25 21:40:54 +01:00
Arnd Bergmann 56fc0e678f Versatile DTS updates for the v5.7 series take one:
- Schema validation for the top level of all ARM reference
   designs: Integrator, Versatile, RealView, Juno.
 - Clean up some node names in the trees so they pass
   validation fine.
 - Drop the old text bindings.
 - A top level DMA ranges patch from Rob.
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Merge tag 'versatile-dts-v5.7-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator into arm/dt

Versatile DTS updates for the v5.7 series take one:

- Schema validation for the top level of all ARM reference
  designs: Integrator, Versatile, RealView, Juno.
- Clean up some node names in the trees so they pass
  validation fine.
- Drop the old text bindings.
- A top level DMA ranges patch from Rob.

* tag 'versatile-dts-v5.7-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator:
  ARM/arm64: dts: Rename SMB bus to just bus
  dt-bindings: arm: Drop the non-YAML bindings
  dt-bindings: arm: Add Versatile Express and Juno YAML schema
  dt-bindings: arm: Add RealView YAML schema
  dt-bindings: arm: Add Versatile YAML schema
  dt-bindings: arm: Add Integrator YAML schema
  ARM: dts: RealView: Fix the name of the SoC node
  ARM: dts: Versatile: Use syscon as node name for IB2
  ARM: dts: integratorap: Remove top level dma-ranges

Link: https://lore.kernel.org/r/CACRpkdbbniYVnsE-pAmU2qCerswserNgEFtY48XQ+_K+DUNC9Q@mail.gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-03-25 21:39:16 +01:00
Arnd Bergmann 7d716bd4b6 Renesas ARM64 DT updates for v5.7
- CryptoCell support for R-Car M3-W, M3-W+, M3-N, E3, and D3,
   - Miscellaneous fixes and improvements.
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Merge tag 'renesas-arm64-dt-for-v5.7-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt

Renesas ARM64 DT updates for v5.7

  - CryptoCell support for R-Car M3-W, M3-W+, M3-N, E3, and D3,
  - Miscellaneous fixes and improvements.

* tag 'renesas-arm64-dt-for-v5.7-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
  arm64: dts: renesas: rzg2: Add reset control properties for display
  arm64: dts: renesas: rcar-gen3: Add reset control properties for display
  arm64: dts: renesas: Remove use of ARCH_R8A7795
  arm64: dts: renesas: rcar-gen3: Add CCREE nodes
  arm64: dts: renesas: rcar-gen3: Replace "vsps" by "renesas,vsps"
  arm: dts: renesas: r8a77980: Remove r8a77970 DU compatible

Link: https://lore.kernel.org/r/20200226110221.19288-5-geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-03-25 21:24:44 +01:00
Arnd Bergmann 880e19294c arm64: soc: ZynqMP SoC changes for v5.7
- Change firmware dependency to be able to disable it
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Merge tag 'zynqmp-soc-for-v5.7' of https://github.com/Xilinx/linux-xlnx into arm/soc

arm64: soc: ZynqMP SoC changes for v5.7

- Change firmware dependency to be able to disable it

* tag 'zynqmp-soc-for-v5.7' of https://github.com/Xilinx/linux-xlnx:
  arm64: zynqmp: Make zynqmp_firmware driver optional
  include: linux: firmware: Correct config dependency of zynqmp_eemi_ops

Link: https://lore.kernel.org/r/ecef6de5-8318-9f88-db8c-7c33fe44901f@monstr.eu
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-03-25 21:06:37 +01:00
Arnd Bergmann 7cd6fa6062 This pull request contains Broadcom ARM64 SoCs changes for 5.7, please
pull the following:
 
 - Geert drops the non-existent HAVE_ARM_ARCH_TIMER symbol select for
   ARCH_BCM2835
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Merge tag 'arm-soc/for-5.7/soc-arm64' of https://github.com/Broadcom/stblinux into arm/soc

This pull request contains Broadcom ARM64 SoCs changes for 5.7, please
pull the following:

- Geert drops the non-existent HAVE_ARM_ARCH_TIMER symbol select for
  ARCH_BCM2835

* tag 'arm-soc/for-5.7/soc-arm64' of https://github.com/Broadcom/stblinux:
  arm64: bcm2835: Drop select of nonexistent HAVE_ARM_ARCH_TIMER

Link: https://lore.kernel.org/r/20200311212012.9418-4-f.fainelli@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-03-25 20:55:15 +01:00
Arnd Bergmann 9441e1f8fd i.MX defconfig changes for 5.7:
- A seris from Li Yang to make defconfig useful for NXP LS family SoCs.
    Most drivers are built as module there, but those helping boot system
    with NFS are enabled built-in.
  - Enable i.MX8MP pinctrl and i.MX8MM thermal driver support in
    defconfig.
  - Enable i.MX DRM driver support for multi_v7_defconfig.
  - Enable ATMEL_MXT and AD7879 touch support for imx_v6_v7_defconfig.
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Merge tag 'imx-defconfig-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/config

i.MX defconfig changes for 5.7:

 - A seris from Li Yang to make defconfig useful for NXP LS family SoCs.
   Most drivers are built as module there, but those helping boot system
   with NFS are enabled built-in.
 - Enable i.MX8MP pinctrl and i.MX8MM thermal driver support in
   defconfig.
 - Enable i.MX DRM driver support for multi_v7_defconfig.
 - Enable ATMEL_MXT and AD7879 touch support for imx_v6_v7_defconfig.

* tag 'imx-defconfig-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (22 commits)
  arm64: defconfig: Enable e1000 device
  arm64: defconfig: Enable PHY devices used on QorIQ boards
  arm64: defconfig: Enable RTC devices for QorIQ boards
  arm64: defconfig: Enable flash device drivers for QorIQ boards
  arm64: defconfig: Enable ARM Mali display driver
  arm64: defconfig: Enable QorIQ GPIO driver
  arm64: defconfig: Enable QorIQ IFC NAND controller driver
  arm64: defconfig: Enable ARM SBSA watchdog driver
  arm64: defconfig: Enable QorIQ cpufreq driver
  arm64: defconfig: Enable NXP/FSL SPI controller drivers
  arm64: defconfig: Enable ENETC Ethernet controller and FELIX switch
  arm64: defconfig: Enable QorIQ DPAA2 drivers
  arm64: defconfig: Enable QorIQ DPAA1 drivers
  arm64: defconfig: Enable NXP flexcan driver
  arm64: defconfig: run through savedefconfig for ordering
  arm64: defconfig: Enable CONFIG_IMX8MM_THERMAL as module
  arm64: defconfig: add i.MX system controller thermal support
  ARM: multi_v7_defconfig: enable drm imx support
  arm64: defconfig: Enable CONFIG_PCIE_LAYERSCAPE_GEN4
  ARM: imx_v6_v7_defconfig: Enable TOUCHSCREEN_AD7879
  ...

Link: https://lore.kernel.org/r/20200318051918.32579-6-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-03-25 17:21:15 +01:00
Arnd Bergmann bc82a35b9a Qualcomm ARM64 defconfig updates for v5.7
Enable SDM845 audio, display and gpu related configs and the Truly
 NT35597 panel driver, all relevant for various SDM845 based boards.
 Enable IPQ6018 clocks and pinctrl and the pmic vibrator driver for
 PM8916.
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Merge tag 'qcom-arm64-defconfig-for-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/config

Qualcomm ARM64 defconfig updates for v5.7

Enable SDM845 audio, display and gpu related configs and the Truly
NT35597 panel driver, all relevant for various SDM845 based boards.
Enable IPQ6018 clocks and pinctrl and the pmic vibrator driver for
PM8916.

* tag 'qcom-arm64-defconfig-for-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
  arm64: defconfig: Enable Qualcomm SDM845 audio configs
  arm64: defconfig: Enable Truly NT35597 WQXGA panel
  arm64: defconfig: Enable Qualcomm SDM845 display and gpu clocks
  arm64: defconfig: Enable qcom ipq6018 clock and pinctrl
  arm64: defconfig: Enable Qualcomm PM8XXX vibrator support

Link: https://lore.kernel.org/r/20200318043856.GB470201@yoga
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-03-25 17:15:43 +01:00
Arnd Bergmann c824d107e0 ARM64: hisilicon: defconfig updates for 5.7
- Enable MEGARAID_SAS to be able to boot from
   disk for the D06CS development board
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Merge tag 'hisi-arm64-defconfig-for-5.7' of git://github.com/hisilicon/linux-hisi into arm/config

ARM64: hisilicon: defconfig updates for 5.7

- Enable MEGARAID_SAS to be able to boot from
  disk for the D06CS development board

* tag 'hisi-arm64-defconfig-for-5.7' of git://github.com/hisilicon/linux-hisi:
  arm64: defconfig: Enable MEGARAID_SAS

Link: https://lore.kernel.org/r/5E61F3C1.1080909@hisilicon.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-03-25 16:49:20 +01:00
Arnd Bergmann 6825444ac3 Renesas ARM64 defconfig updates for v5.7
- Restore R-Car M3-W support,
   - Enable additional support for Renesas platforms.
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Merge tag 'renesas-arm64-defconfig-for-v5.7-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/config

Renesas ARM64 defconfig updates for v5.7

  - Restore R-Car M3-W support,
  - Enable additional support for Renesas platforms.

* tag 'renesas-arm64-defconfig-for-v5.7-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
  arm64: defconfig: Enable additional support for Renesas platforms
  arm64: defconfig: Replace ARCH_R8A7796 by ARCH_R8A77960

Link: https://lore.kernel.org/r/20200226110221.19288-4-geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-03-25 15:57:40 +01:00
Linus Walleij 9b631649c4 arm64: dts: Fix leftover entry-methods for PSCI
These two device trees were either missed or added after
the commit correcting the "entry-method" from
"arm,psci" to just "psci" as per the binding.

Link: https://lore.kernel.org/r/20200322115846.16265-1-linus.walleij@linaro.org
Cc: Sudeep Holla <sudeep.holla@arm.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Chunyan Zhang <chunyan.zhang@unisoc.com>
Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-03-25 14:27:22 +01:00
Qais Yousef e646ac5bb8 arm64: hibernate: Use bringup_hibernate_cpu()
Use bringup_hibernate_cpu() instead of open coding it.

[ tglx: Split out the core change ]

Signed-off-by: Qais Yousef <qais.yousef@arm.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Link: https://lkml.kernel.org/r/20200323135110.30522-9-qais.yousef@arm.com
2020-03-25 12:59:34 +01:00
Qais Yousef 5efbe6a6e1 arm64: Use reboot_cpu instead of hardconding it to 0
Use `reboot_cpu` variable instead of hardcoding 0 as the reboot cpu in
machine_shutdown().

Signed-off-by: Qais Yousef <qais.yousef@arm.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Link: https://lkml.kernel.org/r/20200323135110.30522-8-qais.yousef@arm.com
2020-03-25 12:59:33 +01:00
Qais Yousef d66b16f5df arm64: Don't use disable_nonboot_cpus()
disable_nonboot_cpus() is not safe to use when doing machine_down(),
because it relies on freeze_secondary_cpus() which in turn is
a suspend/resume related freeze and could abort if the logic detects any
pending activities that can prevent finishing the offlining process.

Beside disable_nonboot_cpus() is dependent on CONFIG_PM_SLEEP_SMP which
is an othogonal config to rely on to ensure this function works
correctly.

Signed-off-by: Qais Yousef <qais.yousef@arm.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Link: https://lkml.kernel.org/r/20200323135110.30522-7-qais.yousef@arm.com
2020-03-25 12:59:33 +01:00
Catalin Marinas 44ca0e00b6 Merge branch 'for-next/kernel-ptrauth' into for-next/core
* for-next/kernel-ptrauth:
  : Return address signing - in-kernel support
  arm64: Kconfig: verify binutils support for ARM64_PTR_AUTH
  lkdtm: arm64: test kernel pointer authentication
  arm64: compile the kernel with ptrauth return address signing
  kconfig: Add support for 'as-option'
  arm64: suspend: restore the kernel ptrauth keys
  arm64: __show_regs: strip PAC from lr in printk
  arm64: unwind: strip PAC from kernel addresses
  arm64: mask PAC bits of __builtin_return_address
  arm64: initialize ptrauth keys for kernel booting task
  arm64: initialize and switch ptrauth kernel keys
  arm64: enable ptrauth earlier
  arm64: cpufeature: handle conflicts based on capability
  arm64: cpufeature: Move cpu capability helpers inside C file
  arm64: ptrauth: Add bootup/runtime flags for __cpu_setup
  arm64: install user ptrauth keys at kernel exit time
  arm64: rename ptrauth key structures to be user-specific
  arm64: cpufeature: add pointer auth meta-capabilities
  arm64: cpufeature: Fix meta-capability cpufeature check
2020-03-25 11:11:08 +00:00
Catalin Marinas 806dc825f0 Merge branch 'for-next/asm-cleanups' into for-next/core
* for-next/asm-cleanups:
  : Various asm clean-ups (alignment, mov_q vs ldr, .idmap)
  arm64: move kimage_vaddr to .rodata
  arm64: use mov_q instead of literal ldr
2020-03-25 11:10:51 +00:00
Catalin Marinas 0829a07695 Merge branch 'for-next/asm-annotations' into for-next/core
* for-next/asm-annotations:
  : Modernise arm64 assembly annotations
  arm64: head: Convert install_el2_stub to SYM_INNER_LABEL
  arm64: Mark call_smc_arch_workaround_1 as __maybe_unused
  arm64: entry-ftrace.S: Fix missing argument for CONFIG_FUNCTION_GRAPH_TRACER=y
  arm64: vdso32: Convert to modern assembler annotations
  arm64: vdso: Convert to modern assembler annotations
  arm64: sdei: Annotate SDEI entry points using new style annotations
  arm64: kvm: Modernize __smccc_workaround_1_smc_start annotations
  arm64: kvm: Modernize annotation for __bp_harden_hyp_vecs
  arm64: kvm: Annotate assembly using modern annoations
  arm64: kernel: Convert to modern annotations for assembly data
  arm64: head: Annotate stext and preserve_boot_args as code
  arm64: head.S: Convert to modern annotations for assembly functions
  arm64: ftrace: Modernise annotation of return_to_handler
  arm64: ftrace: Correct annotation of ftrace_caller assembly
  arm64: entry-ftrace.S: Convert to modern annotations for assembly functions
  arm64: entry: Additional annotation conversions for entry.S
  arm64: entry: Annotate ret_from_fork as code
  arm64: entry: Annotate vector table and handlers as code
  arm64: crypto: Modernize names for AES function macros
  arm64: crypto: Modernize some extra assembly annotations
2020-03-25 11:10:46 +00:00
Catalin Marinas da12d2739f Merge branches 'for-next/memory-hotremove', 'for-next/arm_sdei', 'for-next/amu', 'for-next/final-cap-helper', 'for-next/cpu_ops-cleanup', 'for-next/misc' and 'for-next/perf' into for-next/core
* for-next/memory-hotremove:
  : Memory hot-remove support for arm64
  arm64/mm: Enable memory hot remove
  arm64/mm: Hold memory hotplug lock while walking for kernel page table dump

* for-next/arm_sdei:
  : SDEI: fix double locking on return from hibernate and clean-up
  firmware: arm_sdei: clean up sdei_event_create()
  firmware: arm_sdei: Use cpus_read_lock() to avoid races with cpuhp
  firmware: arm_sdei: fix possible double-lock on hibernate error path
  firmware: arm_sdei: fix double-lock on hibernate with shared events

* for-next/amu:
  : ARMv8.4 Activity Monitors support
  clocksource/drivers/arm_arch_timer: validate arch_timer_rate
  arm64: use activity monitors for frequency invariance
  cpufreq: add function to get the hardware max frequency
  Documentation: arm64: document support for the AMU extension
  arm64/kvm: disable access to AMU registers from kvm guests
  arm64: trap to EL1 accesses to AMU counters from EL0
  arm64: add support for the AMU extension v1

* for-next/final-cap-helper:
  : Introduce cpus_have_final_cap_helper(), migrate arm64 KVM to it
  arm64: kvm: hyp: use cpus_have_final_cap()
  arm64: cpufeature: add cpus_have_final_cap()

* for-next/cpu_ops-cleanup:
  : cpu_ops[] access code clean-up
  arm64: Introduce get_cpu_ops() helper function
  arm64: Rename cpu_read_ops() to init_cpu_ops()
  arm64: Declare ACPI parking protocol CPU operation if needed

* for-next/misc:
  : Various fixes and clean-ups
  arm64: define __alloc_zeroed_user_highpage
  arm64/kernel: Simplify __cpu_up() by bailing out early
  arm64: remove redundant blank for '=' operator
  arm64: kexec_file: Fixed code style.
  arm64: add blank after 'if'
  arm64: fix spelling mistake "ca not" -> "cannot"
  arm64: entry: unmask IRQ in el0_sp()
  arm64: efi: add efi-entry.o to targets instead of extra-$(CONFIG_EFI)
  arm64: csum: Optimise IPv6 header checksum
  arch/arm64: fix typo in a comment
  arm64: remove gratuitious/stray .ltorg stanzas
  arm64: Update comment for ASID() macro
  arm64: mm: convert cpu_do_switch_mm() to C
  arm64: fix NUMA Kconfig typos

* for-next/perf:
  : arm64 perf updates
  arm64: perf: Add support for ARMv8.5-PMU 64-bit counters
  KVM: arm64: limit PMU version to PMUv3 for ARMv8.1
  arm64: cpufeature: Extract capped perfmon fields
  arm64: perf: Clean up enable/disable calls
  perf: arm-ccn: Use scnprintf() for robustness
  arm64: perf: Support new DT compatibles
  arm64: perf: Refactor PMU init callbacks
  perf: arm_spe: Remove unnecessary zero check on 'nr_pages'
2020-03-25 11:10:32 +00:00
Mark Brown d4abd29d67 arm64: head: Convert install_el2_stub to SYM_INNER_LABEL
New assembly annotations have recently been introduced which aim to
make the way we describe symbols in assembly more consistent. Recently the
arm64 assembler was converted to use these but install_el2_stub was missed.

Signed-off-by: Mark Brown <broonie@kernel.org>
[catalin.marinas@arm.com: changed to SYM_L_LOCAL]
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2020-03-25 11:07:39 +00:00
Masahiro Yamada d198b34f38 .gitignore: add SPDX License Identifier
Add SPDX License Identifier to all .gitignore files.

Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-03-25 11:50:48 +01:00
Gavin Shan de58ed5e16 arm64: Introduce get_cpu_ops() helper function
This introduces get_cpu_ops() to return the CPU operations according to
the given CPU index. For now, it simply returns the @cpu_ops[cpu] as
before. Also, helper function __cpu_try_die() is introduced to be shared
by cpu_die() and ipi_cpu_crash_stop(). So it shouldn't introduce any
functional changes.

Signed-off-by: Gavin Shan <gshan@redhat.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
2020-03-24 17:24:19 +00:00
Gavin Shan 6885fb129b arm64: Rename cpu_read_ops() to init_cpu_ops()
This renames cpu_read_ops() to init_cpu_ops() as the function is only
called in initialization phase. Also, we will introduce get_cpu_ops() in
the subsequent patches, to retireve the CPU operation by the given CPU
index. The usage of cpu_read_ops() and get_cpu_ops() are difficult to be
distinguished from their names.

Signed-off-by: Gavin Shan <gshan@redhat.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2020-03-24 17:24:13 +00:00
Gavin Shan 7fec52bf80 arm64: Declare ACPI parking protocol CPU operation if needed
It's obvious we needn't declare the corresponding CPU operation when
CONFIG_ARM64_ACPI_PARKING_PROTOCOL is disabled, even it doesn't cause
any compiling warnings.

Signed-off-by: Gavin Shan <gshan@redhat.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2020-03-24 17:24:11 +00:00
Marc Zyngier 7bdabad127 KVM: arm64: GICv4.1: Allow non-trapping WFI when using HW SGIs
Just like for VLPIs, it is beneficial to avoid trapping on WFI when the
vcpu is using the GICv4.1 SGIs.

Add such a check to vcpu_clear_wfx_traps().

Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Zenghui Yu <yuzenghui@huawei.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Link: https://lore.kernel.org/r/20200304203330.4967-23-maz@kernel.org
2020-03-24 12:15:51 +00:00
Marc Zyngier d9c3872cd2 KVM: arm64: GICv4.1: Reload VLPI configuration on distributor enable/disable
Each time a Group-enable bit gets flipped, the state of these bits
needs to be forwarded to the hardware. This is a pretty heavy
handed operation, requiring all vcpus to reload their GICv4
configuration. It is thus implemented as a new request type.

These enable bits are programmed into the HW by setting the VGrp{0,1}En
fields of GICR_VPENDBASER when the vPEs are made resident again.

Of course, we only support Group-1 for now...

Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Zenghui Yu <yuzenghui@huawei.com>
Link: https://lore.kernel.org/r/20200304203330.4967-22-maz@kernel.org
2020-03-24 12:15:51 +00:00
Remi Denis-Courmont 6cf9a2dce6 arm64: move kimage_vaddr to .rodata
This datum is not referenced from .idmap.text: it does not need to be
mapped in idmap. Lets move it to .rodata as it is never written to after
early boot of the primary CPU.
(Maybe .data.ro_after_init would be cleaner though?)

Signed-off-by: Rémi Denis-Courmont <remi@remlab.net>
Acked-by: Will Deacon <will@kernel.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2020-03-24 11:48:24 +00:00
Remi Denis-Courmont dc374b477f arm64: use mov_q instead of literal ldr
In practice, this requires only 2 instructions, or even only 1 for
the idmap_pg_dir size (with 4 or 64 KiB pages). Only the MAIR values
needed more than 2 instructions and it was already converted to mov_q
by 95b3f74bec.

Signed-off-by: Remi Denis-Courmont <remi.denis.courmont@huawei.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
2020-03-24 11:48:24 +00:00
Linus Torvalds 979e52ca04 Merge branch 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6
Pull crypto fix from Herbert Xu:
 "This fixes a correctness bug in the ARM64 version of ChaCha for
  lib/crypto used by WireGuard"

* 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6:
  crypto: arm64/chacha - correctly walk through blocks
2020-03-23 15:55:21 -07:00
Greg Kroah-Hartman cbf580ff09 Merge 5.6-rc7 into tty-next
We need the tty fixes in here as well.

Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-03-23 08:02:55 +01:00
Vincenzo Frascino a5d442f50a arm64: vdso32: Enable Clang Compilation
Enable Clang Compilation for the vdso32 library.

Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Nathan Chancellor <natechancellor@gmail.com> # build
Tested-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Nathan Chancellor <natechancellor@gmail.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Link: https://lkml.kernel.org/r/20200320145351.32292-27-vincenzo.frascino@arm.com
2020-03-21 15:24:03 +01:00
Vincenzo Frascino 5340e87357 arm64: vdso32: Include common headers in the vdso library
The vDSO library should only include the necessary headers required for
a userspace library (UAPI and a minimal set of kernel headers). To make
this possible it is necessary to isolate from the kernel headers the
common parts that are strictly necessary to build the library.

Refactor the vdso32 implementation to include common headers.

Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Link: https://lkml.kernel.org/r/20200320145351.32292-22-vincenzo.frascino@arm.com
2020-03-21 15:24:02 +01:00
Vincenzo Frascino 60ad903e94 arm64: vdso: Include common headers in the vdso library
The vDSO library should only include the necessary headers required for
a userspace library (UAPI and a minimal set of kernel headers). To make
this possible it is necessary to isolate from the kernel headers the
common parts that are strictly necessary to build the library.

Refactor the vdso implementation to include common headers.

Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Link: https://lkml.kernel.org/r/20200320145351.32292-21-vincenzo.frascino@arm.com
2020-03-21 15:24:01 +01:00
Vincenzo Frascino f511e07917 arm64: Introduce asm/vdso/processor.h
The vDSO library should only include the necessary headers required for
a userspace library (UAPI and a minimal set of kernel headers). To make
this possible it is necessary to isolate from the kernel headers the
common parts that are strictly necessary to build the library.

Introduce asm/vdso/processor.h to contain all the arm64 specific
functions that are suitable for vDSO inclusion.

Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Link: https://lkml.kernel.org/r/20200320145351.32292-20-vincenzo.frascino@arm.com
2020-03-21 15:24:01 +01:00
Vincenzo Frascino 94d0f5be88 arm64: vdso32: Code clean up
The compat vdso library had some checks that are not anymore relevant.

Remove the unused code from the compat vDSO library.

Note: This patch is preparatory for a future one that will introduce
asm/vdso/processor.h on arm64.

Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Link: https://lore.kernel.org/lkml/20200317122220.30393-19-vincenzo.frascino@arm.com
Link: https://lkml.kernel.org/r/20200320145351.32292-19-vincenzo.frascino@arm.com
2020-03-21 15:24:00 +01:00
Vincenzo Frascino 31fdcac07f arm64: Introduce asm/vdso/clocksource.h
The vDSO library should only include the necessary headers required for
a userspace library (UAPI and a minimal set of kernel headers). To make
this possible it is necessary to isolate from the kernel headers the
common parts that are strictly necessary to build the library.

Introduce asm/vdso/clocksource.h to contain all the arm64 specific
functions that are suitable for vDSO inclusion.

This header will be required by a future patch that will generalize
vdso/clocksource.h.

Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Link: https://lkml.kernel.org/r/20200320145351.32292-7-vincenzo.frascino@arm.com
2020-03-21 15:23:55 +01:00
Linus Torvalds 5ad0ec0b86 arm64 fixes for -rc7
- Fix panic() when it occurs during secondary CPU startup
 
 - Fix "kpti=off" when KASLR is enabled
 
 - Fix howler in compat syscall table for vDSO clock_getres() fallback
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Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux

Pull arm64 fixes from Will Deacon:

 - Fix panic() when it occurs during secondary CPU startup

 - Fix "kpti=off" when KASLR is enabled

 - Fix howler in compat syscall table for vDSO clock_getres() fallback

* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
  arm64: compat: Fix syscall number of compat_clock_getres
  arm64: kpti: Fix "kpti=off" when KASLR is enabled
  arm64: smp: fix crash_smp_send_stop() behaviour
  arm64: smp: fix smp_send_stop() behaviour
2020-03-20 09:28:25 -07:00
Nick Desaulniers 3b446c7d27 arm64: Kconfig: verify binutils support for ARM64_PTR_AUTH
Clang relies on GNU as from binutils to assemble the Linux kernel,
currently. A recent patch to enable the armv8.3-a extension for pointer
authentication checked for compiler support of the relevant flags.
Everything works with binutils 2.34+, but for older versions we observe
assembler errors:

/tmp/vgettimeofday-36a54b.s: Assembler messages:
/tmp/vgettimeofday-36a54b.s:40: Error: unknown pseudo-op: `.cfi_negate_ra_state'

When compiling with Clang, require the assembler to support
.cfi_negate_ra_state directives, in order to support CONFIG_ARM64_PTR_AUTH.

Link: https://github.com/ClangBuiltLinux/linux/issues/938
Signed-off-by: Nick Desaulniers <ndesaulniers@google.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Nathan Chancellor <natechancellor@gmail.com>
Tested-by: Nathan Chancellor <natechancellor@gmail.com>
2020-03-20 15:01:04 +00:00
Ilie Halip 6f5459da2b arm64: alternative: fix build with clang integrated assembler
Building an arm64 defconfig with clang's integrated assembler, this error
occurs:
    <instantiation>:2:2: error: unrecognized instruction mnemonic
     _ASM_EXTABLE 9999b, 9f
     ^
    arch/arm64/mm/cache.S:50:1: note: while in macro instantiation
    user_alt 9f, "dc cvau, x4", "dc civac, x4", 0
    ^

While GNU as seems fine with case-sensitive macro instantiations, clang
doesn't, so use the actual macro name (_asm_extable) as in the rest of
the file.

Also checked that the generated assembly matches the GCC output.

Reviewed-by: Nick Desaulniers <ndesaulniers@google.com>
Tested-by: Nick Desaulniers <ndesaulniers@google.com>
Fixes: 290622efc7 ("arm64: fix "dc cvau" cache operation on errata-affected core")
Link: https://github.com/ClangBuiltLinux/linux/issues/924
Signed-off-by: Ilie Halip <ilie.halip@gmail.com>
Signed-off-by: Will Deacon <will@kernel.org>
2020-03-20 10:01:28 +00:00
Torsten Duwe 82ff493eb7 crypto: arm/neon - memzero_explicit aes-cbc key
At function exit, do not leave the expanded key in the rk struct
which got allocated on the stack.

Signed-off-by: Torsten Duwe <duwe@suse.de>
Acked-by: Will Deacon <will@kernel.org>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-03-20 14:36:51 +11:00
Jason A. Donenfeld c8cfcb78c6 crypto: arm64/chacha - correctly walk through blocks
Prior, passing in chunks of 2, 3, or 4, followed by any additional
chunks would result in the chacha state counter getting out of sync,
resulting in incorrect encryption/decryption, which is a pretty nasty
crypto vuln: "why do images look weird on webpages?" WireGuard users
never experienced this prior, because we have always, out of tree, used
a different crypto library, until the recent Frankenzinc addition. This
commit fixes the issue by advancing the pointers and state counter by
the actual size processed. It also fixes up a bug in the (optional,
costly) stride test that prevented it from running on arm64.

Fixes: b3aad5bad2 ("crypto: arm64/chacha - expose arm64 ChaCha routine as library function")
Reported-and-tested-by: Emil Renner Berthing <kernel@esmil.dk>
Cc: Ard Biesheuvel <ardb@kernel.org>
Cc: stable@vger.kernel.org # v5.5+
Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
Reviewed-by: Eric Biggers <ebiggers@google.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-03-20 14:35:27 +11:00
Vincenzo Frascino 3568b88944 arm64: compat: Fix syscall number of compat_clock_getres
The syscall number of compat_clock_getres was erroneously set to 247
(__NR_io_cancel!) instead of 264. This causes the vDSO fallback of
clock_getres() to land on the wrong syscall for compat tasks.

Fix the numbering.

Cc: <stable@vger.kernel.org>
Fixes: 53c489e1df ("arm64: compat: Add missing syscall numbers")
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Nick Desaulniers <ndesaulniers@google.com>
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>
2020-03-19 19:23:46 +00:00
Grygorii Strashko ad3bcb0f48 arm64: dts: ti: k3-j721e-mcu: add scm node and phy-gmii-sel nodes
Add DT node for MCU System Control module DT node and DT node for the TI
J721E SoC phy-gmii-sel PHY required for Ethernet ports mode selection.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2020-03-19 10:36:18 +02:00
Grygorii Strashko 243246b588 arm64: dts: ti: k3-am65-mcu: add phy-gmii-sel node
Add DT node for the TI AM65x SoC phy-gmii-sel PHY required for Ethernet
ports mode selection.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2020-03-19 10:36:17 +02:00
Vignesh Raghavendra 85800da0b0 arm64: dts: ti: k3-am65-mcu: Add DMA entries for ADC
Add DMA entries for ADC nodes

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2020-03-19 10:34:38 +02:00
Vignesh Raghavendra 7ec378ed1d arm64: dts: ti: k3-am65-main: Add DMA entries for main_spi0
Add DMA entry for main_spi0, that has SPI flash connected, for better
throughput and reduced CPU load.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2020-03-19 10:34:38 +02:00
Vignesh Raghavendra 5ccd8dfe8b arm64: dts: ti: k3-j721e-mcu-wakeup: Add DMA entries for ADC
Add DMA entries for ADC nodes

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2020-03-19 10:34:04 +02:00
Dave Gerlach a81e5442d7 arm64: dts: ti: k3-am65: Add clocks to dwc3 nodes
The TI sci-clk driver can scan the DT for all clocks provided by system
firmware and does this by checking the clocks property of all nodes, so
we must add this to the dwc3 nodes so USB clocks are available.

Without this USB does not work with latest system firmware i.e.
[    1.714662] clk: couldn't get parent clock 0 for /interconnect@100000/dwc3@4020000

Fixes: cc54a99464 ("arm64: dts: ti: k3-am6: add USB suppor")
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Cc: stable@kernel.org
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2020-03-19 10:30:23 +02:00
Will Deacon c83557859e arm64: kpti: Fix "kpti=off" when KASLR is enabled
Enabling KASLR forces the use of non-global page-table entries for kernel
mappings, as this is a decision that we have to make very early on before
mapping the kernel proper. When used in conjunction with the "kpti=off"
command-line option, it is possible to use non-global kernel mappings but
with the kpti trampoline disabled.

Since commit 09e3c22a86 ("arm64: Use a variable to store non-global
mappings decision"), arm64_kernel_unmapped_at_el0() reflects only the use of
non-global mappings and does not take into account whether the kpti
trampoline is enabled. This breaks context switching of the TPIDRRO_EL0
register for 64-bit tasks, where the clearing of the register is deferred to
the ret-to-user code, but it also breaks the ARM SPE PMU driver which
helpfully recommends passing "kpti=off" on the command line!

Report whether or not KPTI is actually enabled in
arm64_kernel_unmapped_at_el0() and check the 'arm64_use_ng_mappings' global
variable directly when determining the protection flags for kernel mappings.

Cc: Mark Brown <broonie@kernel.org>
Reported-by: Hongbo Yao <yaohongbo@huawei.com>
Tested-by: Hongbo Yao <yaohongbo@huawei.com>
Fixes: 09e3c22a86 ("arm64: Use a variable to store non-global mappings decision")
Signed-off-by: Will Deacon <will@kernel.org>
2020-03-19 08:28:43 +00:00
Kristina Martsenko 74afda4016 arm64: compile the kernel with ptrauth return address signing
Compile all functions with two ptrauth instructions: PACIASP in the
prologue to sign the return address, and AUTIASP in the epilogue to
authenticate the return address (from the stack). If authentication
fails, the return will cause an instruction abort to be taken, followed
by an oops and killing the task.

This should help protect the kernel against attacks using
return-oriented programming. As ptrauth protects the return address, it
can also serve as a replacement for CONFIG_STACKPROTECTOR, although note
that it does not protect other parts of the stack.

The new instructions are in the HINT encoding space, so on a system
without ptrauth they execute as NOPs.

CONFIG_ARM64_PTR_AUTH now not only enables ptrauth for userspace and KVM
guests, but also automatically builds the kernel with ptrauth
instructions if the compiler supports it. If there is no compiler
support, we do not warn that the kernel was built without ptrauth
instructions.

GCC 7 and 8 support the -msign-return-address option, while GCC 9
deprecates that option and replaces it with -mbranch-protection. Support
both options.

Clang uses an external assembler hence this patch makes sure that the
correct parameters (-march=armv8.3-a) are passed down to help it recognize
the ptrauth instructions.

Ftrace function tracer works properly with Ptrauth only when
patchable-function-entry feature is present and is ensured by the
Kconfig dependency.

Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Kees Cook <keescook@chromium.org>
Reviewed-by: Vincenzo Frascino <Vincenzo.Frascino@arm.com> # not co-dev parts
Co-developed-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Signed-off-by: Kristina Martsenko <kristina.martsenko@arm.com>
[Amit: Cover leaf function, comments, Ftrace Kconfig]
Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2020-03-18 09:50:21 +00:00
Amit Daniel Kachhap e51f5f56dd arm64: suspend: restore the kernel ptrauth keys
This patch restores the kernel keys from current task during cpu resume
after the mmu is turned on and ptrauth is enabled.

A flag is added in macro ptrauth_keys_install_kernel to check if isb
instruction needs to be executed.

Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
Reviewed-by: Vincenzo Frascino <Vincenzo.Frascino@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2020-03-18 09:50:21 +00:00
Amit Daniel Kachhap cdcb61ae4c arm64: __show_regs: strip PAC from lr in printk
lr is printed with %pS which will try to find an entry in kallsyms.
After enabling pointer authentication, this match will fail due to
PAC present in the lr.

Strip PAC from the lr to display the correct symbol name.

Suggested-by: James Morse <james.morse@arm.com>
Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
Reviewed-by: Vincenzo Frascino <Vincenzo.Frascino@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2020-03-18 09:50:20 +00:00
Mark Rutland 04ad99a0b1 arm64: unwind: strip PAC from kernel addresses
When we enable pointer authentication in the kernel, LR values saved to
the stack will have a PAC which we must strip in order to retrieve the
real return address.

Strip PACs when unwinding the stack in order to account for this.

When function graph tracer is used with patchable-function-entry then
return_to_handler will also have pac bits so strip it too.

Reviewed-by: Kees Cook <keescook@chromium.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: James Morse <james.morse@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Kristina Martsenko <kristina.martsenko@arm.com>
[Amit: Re-position ptrauth_strip_insn_pac, comment]
Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2020-03-18 09:50:20 +00:00
Amit Daniel Kachhap 689eae42af arm64: mask PAC bits of __builtin_return_address
Functions like vmap() record how much memory has been allocated by their
callers, and callers are identified using __builtin_return_address(). Once
the kernel is using pointer-auth the return address will be signed. This
means it will not match any kernel symbol, and will vary between threads
even for the same caller.

The output of /proc/vmallocinfo in this case may look like,
0x(____ptrval____)-0x(____ptrval____)   20480 0x86e28000100e7c60 pages=4 vmalloc N0=4
0x(____ptrval____)-0x(____ptrval____)   20480 0x86e28000100e7c60 pages=4 vmalloc N0=4
0x(____ptrval____)-0x(____ptrval____)   20480 0xc5c78000100e7c60 pages=4 vmalloc N0=4

The above three 64bit values should be the same symbol name and not
different LR values.

Use the pre-processor to add logic to clear the PAC to
__builtin_return_address() callers. This patch adds a new file
asm/compiler.h and is transitively included via include/compiler_types.h on
the compiler command line so it is guaranteed to be loaded and the users of
this macro will not find a wrong version.

Helper macros ptrauth_kernel_pac_mask/ptrauth_clear_pac are created for
this purpose and added in this file. Existing macro ptrauth_user_pac_mask
moved from asm/pointer_auth.h.

Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
Reviewed-by: James Morse <james.morse@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2020-03-18 09:50:20 +00:00
Amit Daniel Kachhap 2832158233 arm64: initialize ptrauth keys for kernel booting task
This patch uses the existing boot_init_stack_canary arch function
to initialize the ptrauth keys for the booting task in the primary
core. The requirement here is that it should be always inline and
the caller must never return.

As pointer authentication too detects a subset of stack corruption
so it makes sense to place this code here.

Both pointer authentication and stack canary codes are protected
by their respective config option.

Suggested-by: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
Reviewed-by: Vincenzo Frascino <Vincenzo.Frascino@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2020-03-18 09:50:20 +00:00
Kristina Martsenko 33e4523498 arm64: initialize and switch ptrauth kernel keys
Set up keys to use pointer authentication within the kernel. The kernel
will be compiled with APIAKey instructions, the other keys are currently
unused. Each task is given its own APIAKey, which is initialized during
fork. The key is changed during context switch and on kernel entry from
EL0.

The keys for idle threads need to be set before calling any C functions,
because it is not possible to enter and exit a function with different
keys.

Reviewed-by: Kees Cook <keescook@chromium.org>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Vincenzo Frascino <Vincenzo.Frascino@arm.com>
Signed-off-by: Kristina Martsenko <kristina.martsenko@arm.com>
[Amit: Modified secondary cores key structure, comments]
Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2020-03-18 09:50:20 +00:00
Kristina Martsenko 6982934e19 arm64: enable ptrauth earlier
When the kernel is compiled with pointer auth instructions, the boot CPU
needs to start using address auth very early, so change the cpucap to
account for this.

Pointer auth must be enabled before we call C functions, because it is
not possible to enter a function with pointer auth disabled and exit it
with pointer auth enabled. Note, mismatches between architected and
IMPDEF algorithms will still be caught by the cpufeature framework (the
separate *_ARCH and *_IMP_DEF cpucaps).

Note the change in behavior: if the boot CPU has address auth and a
late CPU does not, then the late CPU is parked by the cpufeature
framework. This is possible as kernel will only have NOP space intructions
for PAC so such mismatched late cpu will silently ignore those
instructions in C functions. Also, if the boot CPU does not have address
auth and the late CPU has then the late cpu will still boot but with
ptrauth feature disabled.

Leave generic authentication as a "system scope" cpucap for now, since
initially the kernel will only use address authentication.

Reviewed-by: Kees Cook <keescook@chromium.org>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Reviewed-by: Vincenzo Frascino <Vincenzo.Frascino@arm.com>
Signed-off-by: Kristina Martsenko <kristina.martsenko@arm.com>
[Amit: Re-worked ptrauth setup logic, comments]
Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2020-03-18 09:50:19 +00:00
Kristina Martsenko deeaac5175 arm64: cpufeature: handle conflicts based on capability
Each system capability can be of either boot, local, or system scope,
depending on when the state of the capability is finalized. When we
detect a conflict on a late CPU, we either offline the CPU or panic the
system. We currently always panic if the conflict is caused by a boot
scope capability, and offline the CPU if the conflict is caused by a
local or system scope capability.

We're going to want to add a new capability (for pointer authentication)
which needs to be boot scope but doesn't need to panic the system when a
conflict is detected. So add a new flag to specify whether the
capability requires the system to panic or not. Current boot scope
capabilities are updated to set the flag, so there should be no
functional change as a result of this patch.

Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
Signed-off-by: Kristina Martsenko <kristina.martsenko@arm.com>
Reviewed-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Reviewed-by: Kees Cook <keescook@chromium.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2020-03-18 09:50:19 +00:00
Amit Daniel Kachhap 8c176e1625 arm64: cpufeature: Move cpu capability helpers inside C file
These helpers are used only by functions inside cpufeature.c and
hence makes sense to be moved from cpufeature.h to cpufeature.c as
they are not expected to be used globally.

This change helps in reducing the header file size as well as to add
future cpu capability types without confusion. Only a cpu capability
type macro is sufficient to expose those capabilities globally.

Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
Reviewed-by: Vincenzo Frascino <Vincenzo.Frascino@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2020-03-18 09:50:19 +00:00
Amit Daniel Kachhap df3551011b arm64: ptrauth: Add bootup/runtime flags for __cpu_setup
This patch allows __cpu_setup to be invoked with one of these flags,
ARM64_CPU_BOOT_PRIMARY, ARM64_CPU_BOOT_SECONDARY or ARM64_CPU_RUNTIME.
This is required as some cpufeatures need different handling during
different scenarios.

The input parameter in x0 is preserved till the end to be used inside
this function.

There should be no functional change with this patch and is useful
for the subsequent ptrauth patch which utilizes it. Some upcoming
arm cpufeatures can also utilize these flags.

Suggested-by: James Morse <james.morse@arm.com>
Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
Reviewed-by: Vincenzo Frascino <Vincenzo.Frascino@arm.com>
Reviewed-by: James Morse <james.morse@arm.com>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2020-03-18 09:50:19 +00:00
Kristina Martsenko be12984256 arm64: install user ptrauth keys at kernel exit time
As we're going to enable pointer auth within the kernel and use a
different APIAKey for the kernel itself, so move the user APIAKey
switch to EL0 exception return.

The other 4 keys could remain switched during task switch, but are also
moved to keep things consistent.

Reviewed-by: Kees Cook <keescook@chromium.org>
Reviewed-by: James Morse <james.morse@arm.com>
Reviewed-by: Vincenzo Frascino <Vincenzo.Frascino@arm.com>
Signed-off-by: Kristina Martsenko <kristina.martsenko@arm.com>
[Amit: commit msg, re-positioned the patch, comments]
Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2020-03-18 09:50:19 +00:00
Kristina Martsenko 91a1b6ccff arm64: rename ptrauth key structures to be user-specific
We currently enable ptrauth for userspace, but do not use it within the
kernel. We're going to enable it for the kernel, and will need to manage
a separate set of ptrauth keys for the kernel.

We currently keep all 5 keys in struct ptrauth_keys. However, as the
kernel will only need to use 1 key, it is a bit wasteful to allocate a
whole ptrauth_keys struct for every thread.

Therefore, a subsequent patch will define a separate struct, with only 1
key, for the kernel. In preparation for that, rename the existing struct
(and associated macros and functions) to reflect that they are specific
to userspace.

Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Vincenzo Frascino <Vincenzo.Frascino@arm.com>
Signed-off-by: Kristina Martsenko <kristina.martsenko@arm.com>
[Amit: Re-positioned the patch to reduce the diff]
Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2020-03-18 09:50:18 +00:00
Kristina Martsenko cfef06bd06 arm64: cpufeature: add pointer auth meta-capabilities
To enable pointer auth for the kernel, we're going to need to check for
the presence of address auth and generic auth using alternative_if. We
currently have two cpucaps for each, but alternative_if needs to check a
single cpucap. So define meta-capabilities that are present when either
of the current two capabilities is present.

Leave the existing four cpucaps in place, as they are still needed to
check for mismatched systems where one CPU has the architected algorithm
but another has the IMP DEF algorithm.

Note, the meta-capabilities were present before but were removed in
commit a56005d321 ("arm64: cpufeature: Reduce number of pointer auth
CPU caps from 6 to 4") and commit 1e013d0612 ("arm64: cpufeature: Rework
ptr auth hwcaps using multi_entry_cap_matches"), as they were not needed
then. Note, unlike before, the current patch checks the cpucap values
directly, instead of reading the CPU ID register value.

Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Reviewed-by: Kees Cook <keescook@chromium.org>
Reviewed-by: Vincenzo Frascino <Vincenzo.Frascino@arm.com>
Signed-off-by: Kristina Martsenko <kristina.martsenko@arm.com>
[Amit: commit message and macro rebase, use __system_matches_cap]
Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2020-03-18 09:50:18 +00:00
Amit Daniel Kachhap 3ff047f697 arm64: cpufeature: Fix meta-capability cpufeature check
Some existing/future meta cpucaps match need the presence of individual
cpucaps. Currently the individual cpucaps checks it via an array based
flag and this introduces dependency on the array entry order.
This limitation exists only for system scope cpufeature.

This patch introduces an internal helper function (__system_matches_cap)
to invoke the matching handler for system scope. This helper has to be
used during a narrow window when,
- The system wide safe registers are set with all the SMP CPUs and,
- The SYSTEM_FEATURE cpu_hwcaps may not have been set.

Normal users should use the existing cpus_have_{const_}cap() global
function.

Suggested-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Suggested-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
Reviewed-by: Vincenzo Frascino <Vincenzo.Frascino@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2020-03-18 09:50:18 +00:00
Cristian Marussi f50b7daccc arm64: smp: fix crash_smp_send_stop() behaviour
On a system configured to trigger a crash_kexec() reboot, when only one CPU
is online and another CPU panics while starting-up, crash_smp_send_stop()
will fail to send any STOP message to the other already online core,
resulting in fail to freeze and registers not properly saved.

Moreover even if the proper messages are sent (case CPUs > 2)
it will similarly fail to account for the booting CPU when executing
the final stop wait-loop, so potentially resulting in some CPU not
been waited for shutdown before rebooting.

A tangible effect of this behaviour can be observed when, after a panic
with kexec enabled and loaded, on the following reboot triggered by kexec,
the cpu that could not be successfully stopped fails to come back online:

[  362.291022] ------------[ cut here ]------------
[  362.291525] kernel BUG at arch/arm64/kernel/cpufeature.c:886!
[  362.292023] Internal error: Oops - BUG: 0 [#1] PREEMPT SMP
[  362.292400] Modules linked in:
[  362.292970] CPU: 3 PID: 0 Comm: swapper/3 Kdump: loaded Not tainted 5.6.0-rc4-00003-gc780b890948a #105
[  362.293136] Hardware name: Foundation-v8A (DT)
[  362.293382] pstate: 200001c5 (nzCv dAIF -PAN -UAO)
[  362.294063] pc : has_cpuid_feature+0xf0/0x348
[  362.294177] lr : verify_local_elf_hwcaps+0x84/0xe8
[  362.294280] sp : ffff800011b1bf60
[  362.294362] x29: ffff800011b1bf60 x28: 0000000000000000
[  362.294534] x27: 0000000000000000 x26: 0000000000000000
[  362.294631] x25: 0000000000000000 x24: ffff80001189a25c
[  362.294718] x23: 0000000000000000 x22: 0000000000000000
[  362.294803] x21: ffff8000114aa018 x20: ffff800011156a00
[  362.294897] x19: ffff800010c944a0 x18: 0000000000000004
[  362.294987] x17: 0000000000000000 x16: 0000000000000000
[  362.295073] x15: 00004e53b831ae3c x14: 00004e53b831ae3c
[  362.295165] x13: 0000000000000384 x12: 0000000000000000
[  362.295251] x11: 0000000000000000 x10: 00400032b5503510
[  362.295334] x9 : 0000000000000000 x8 : ffff800010c7e204
[  362.295426] x7 : 00000000410fd0f0 x6 : 0000000000000001
[  362.295508] x5 : 00000000410fd0f0 x4 : 0000000000000000
[  362.295592] x3 : 0000000000000000 x2 : ffff8000100939d8
[  362.295683] x1 : 0000000000180420 x0 : 0000000000180480
[  362.296011] Call trace:
[  362.296257]  has_cpuid_feature+0xf0/0x348
[  362.296350]  verify_local_elf_hwcaps+0x84/0xe8
[  362.296424]  check_local_cpu_capabilities+0x44/0x128
[  362.296497]  secondary_start_kernel+0xf4/0x188
[  362.296998] Code: 52805001 72a00301 6b01001f 54000ec0 (d4210000)
[  362.298652] SMP: stopping secondary CPUs
[  362.300615] Starting crashdump kernel...
[  362.301168] Bye!
[    0.000000] Booting Linux on physical CPU 0x0000000003 [0x410fd0f0]
[    0.000000] Linux version 5.6.0-rc4-00003-gc780b890948a (crimar01@e120937-lin) (gcc version 8.3.0 (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36))) #105 SMP PREEMPT Fri Mar 6 17:00:42 GMT 2020
[    0.000000] Machine model: Foundation-v8A
[    0.000000] earlycon: pl11 at MMIO 0x000000001c090000 (options '')
[    0.000000] printk: bootconsole [pl11] enabled
.....
[    0.138024] rcu: Hierarchical SRCU implementation.
[    0.153472] its@2f020000: unable to locate ITS domain
[    0.154078] its@2f020000: Unable to locate ITS domain
[    0.157541] EFI services will not be available.
[    0.175395] smp: Bringing up secondary CPUs ...
[    0.209182] psci: failed to boot CPU1 (-22)
[    0.209377] CPU1: failed to boot: -22
[    0.274598] Detected PIPT I-cache on CPU2
[    0.278707] GICv3: CPU2: found redistributor 1 region 0:0x000000002f120000
[    0.285212] CPU2: Booted secondary processor 0x0000000001 [0x410fd0f0]
[    0.369053] Detected PIPT I-cache on CPU3
[    0.372947] GICv3: CPU3: found redistributor 2 region 0:0x000000002f140000
[    0.378664] CPU3: Booted secondary processor 0x0000000002 [0x410fd0f0]
[    0.401707] smp: Brought up 1 node, 3 CPUs
[    0.404057] SMP: Total of 3 processors activated.

Make crash_smp_send_stop() account also for the online status of the
calling CPU while evaluating how many CPUs are effectively online: this way
the right number of STOPs is sent and all other stopped-cores's registers
are properly saved.

Fixes: 78fd584cde ("arm64: kdump: implement machine_crash_shutdown()")
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Cristian Marussi <cristian.marussi@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>
2020-03-17 22:51:19 +00:00
Cristian Marussi d0bab0c39e arm64: smp: fix smp_send_stop() behaviour
On a system with only one CPU online, when another one CPU panics while
starting-up, smp_send_stop() will fail to send any STOP message to the
other already online core, resulting in a system still responsive and
alive at the end of the panic procedure.

[  186.700083] CPU3: shutdown
[  187.075462] CPU2: shutdown
[  187.162869] CPU1: shutdown
[  188.689998] ------------[ cut here ]------------
[  188.691645] kernel BUG at arch/arm64/kernel/cpufeature.c:886!
[  188.692079] Internal error: Oops - BUG: 0 [#1] PREEMPT SMP
[  188.692444] Modules linked in:
[  188.693031] CPU: 3 PID: 0 Comm: swapper/3 Not tainted 5.6.0-rc4-00001-g338d25c35a98 #104
[  188.693175] Hardware name: Foundation-v8A (DT)
[  188.693492] pstate: 200001c5 (nzCv dAIF -PAN -UAO)
[  188.694183] pc : has_cpuid_feature+0xf0/0x348
[  188.694311] lr : verify_local_elf_hwcaps+0x84/0xe8
[  188.694410] sp : ffff800011b1bf60
[  188.694536] x29: ffff800011b1bf60 x28: 0000000000000000
[  188.694707] x27: 0000000000000000 x26: 0000000000000000
[  188.694801] x25: 0000000000000000 x24: ffff80001189a25c
[  188.694905] x23: 0000000000000000 x22: 0000000000000000
[  188.694996] x21: ffff8000114aa018 x20: ffff800011156a38
[  188.695089] x19: ffff800010c944a0 x18: 0000000000000004
[  188.695187] x17: 0000000000000000 x16: 0000000000000000
[  188.695280] x15: 0000249dbde5431e x14: 0262cbe497efa1fa
[  188.695371] x13: 0000000000000002 x12: 0000000000002592
[  188.695472] x11: 0000000000000080 x10: 00400032b5503510
[  188.695572] x9 : 0000000000000000 x8 : ffff800010c80204
[  188.695659] x7 : 00000000410fd0f0 x6 : 0000000000000001
[  188.695750] x5 : 00000000410fd0f0 x4 : 0000000000000000
[  188.695836] x3 : 0000000000000000 x2 : ffff8000100939d8
[  188.695919] x1 : 0000000000180420 x0 : 0000000000180480
[  188.696253] Call trace:
[  188.696410]  has_cpuid_feature+0xf0/0x348
[  188.696504]  verify_local_elf_hwcaps+0x84/0xe8
[  188.696591]  check_local_cpu_capabilities+0x44/0x128
[  188.696666]  secondary_start_kernel+0xf4/0x188
[  188.697150] Code: 52805001 72a00301 6b01001f 54000ec0 (d4210000)
[  188.698639] ---[ end trace 3f12ca47652f7b72 ]---
[  188.699160] Kernel panic - not syncing: Attempted to kill the idle task!
[  188.699546] Kernel Offset: disabled
[  188.699828] CPU features: 0x00004,20c02008
[  188.700012] Memory Limit: none
[  188.700538] ---[ end Kernel panic - not syncing: Attempted to kill the idle task! ]---

[root@arch ~]# echo Helo
Helo
[root@arch ~]# cat /proc/cpuinfo | grep proce
processor	: 0

Make smp_send_stop() account also for the online status of the calling CPU
while evaluating how many CPUs are effectively online: this way, the right
number of STOPs is sent, so enforcing a proper freeze of the system at the
end of panic even under the above conditions.

Fixes: 08e875c16a ("arm64: SMP support")
Reported-by: Dave Martin <Dave.Martin@arm.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Cristian Marussi <cristian.marussi@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>
2020-03-17 22:51:18 +00:00
Andrew Murray 8673e02e58 arm64: perf: Add support for ARMv8.5-PMU 64-bit counters
At present ARMv8 event counters are limited to 32-bits, though by
using the CHAIN event it's possible to combine adjacent counters to
achieve 64-bits. The perf config1:0 bit can be set to use such a
configuration.

With the introduction of ARMv8.5-PMU support, all event counters can
now be used as 64-bit counters.

Let's enable 64-bit event counters where support exists. Unless the
user sets config1:0 we will adjust the counter value such that it
overflows upon 32-bit overflow. This follows the same behaviour as
the cycle counter which has always been (and remains) 64-bits.

Signed-off-by: Andrew Murray <andrew.murray@arm.com>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
[Mark: fix ID field names, compare with 8.5 value]
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>
2020-03-17 22:50:30 +00:00
Andrew Murray c854188ea0 KVM: arm64: limit PMU version to PMUv3 for ARMv8.1
We currently expose the PMU version of the host to the guest via
emulation of the DFR0_EL1 and AA64DFR0_EL1 debug feature registers.
However many of the features offered beyond PMUv3 for 8.1 are not
supported in KVM. Examples of this include support for the PMMIR
registers (added in PMUv3 for ARMv8.4) and 64-bit event counters
added in (PMUv3 for ARMv8.5).

Let's trap the Debug Feature Registers in order to limit
PMUVer/PerfMon in the Debug Feature Registers to PMUv3 for ARMv8.1
to avoid unexpected behaviour.

Both ID_AA64DFR0.PMUVer and ID_DFR0.PerfMon follow the "Alternative ID
scheme used for the Performance Monitors Extension version" where 0xF
means an IMPLEMENTATION DEFINED PMU is implemented, and values 0x0-0xE
are treated as with an unsigned field (with 0x0 meaning no PMU is
present). As we don't expect to expose an IMPLEMENTATION DEFINED PMU,
and our cap is below 0xF, we can treat these fields as unsigned when
applying the cap.

Signed-off-by: Andrew Murray <andrew.murray@arm.com>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
[Mark: make field names consistent, use perfmon cap]
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>
2020-03-17 22:46:14 +00:00
Andrew Murray 8e35aa642e arm64: cpufeature: Extract capped perfmon fields
When emulating ID registers there is often a need to cap the version
bits of a feature such that the guest will not use features that the
host is not aware of. For example, when KVM mediates access to the PMU
by emulating register accesses.

Let's add a helper that extracts a performance monitors ID field and
caps the version to a given value.

Fields that identify the version of the Performance Monitors Extension
do not follow the standard ID scheme, and instead follow the scheme
described in ARM DDI 0487E.a page D13-2825 "Alternative ID scheme used
for the Performance Monitors Extension version". The value 0xF means an
IMPLEMENTATION DEFINED PMU is present, and values 0x0-OxE can be treated
the same as an unsigned field with 0x0 meaning no PMU is present.

Signed-off-by: Andrew Murray <andrew.murray@arm.com>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
[Mark: rework to handle perfmon fields]
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>
2020-03-17 22:46:14 +00:00
Robin Murphy 29227d6ea1 arm64: perf: Clean up enable/disable calls
Reading this code bordered on painful, what with all the repetition and
pointless return values. More fundamentally, dribbling the hardware
enables and disables in one bit at a time incurs needless system
register overhead for chained events and on reset. We already use
bitmask values for the KVM hooks, so consolidate all the register
accesses to match, and make a reasonable saving in both source and
object code.

Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>
2020-03-17 22:45:59 +00:00
Neil Armstrong a084eaf309 arm64: dts: meson-g12b-odroid-n2: add SPIFC controller node
Add disabled SPIFC controller node with instruction on how to enable
it while lowering capabilities of the eMMC controller from 8bits bus
width to 4bits bus width, it's data pins 4 to 7 being shared with
the SPI NOR controller pins.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Link: https://lore.kernel.org/r/20200313090713.15147-5-narmstrong@baylibre.com
2020-03-17 15:15:09 -07:00
Neil Armstrong 0e1610e726 arm64: dts: khadas-vim3: add SPIFC controller node
Add disabled SPIFC controller node with instruction on how to enable
it while lowering capabilities of the eMMC controller from 8bits bus
width to 4bits bus width, it's data pins 4 to 7 being shared with
the SPI NOR controller pins.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Link: https://lore.kernel.org/r/20200313090713.15147-4-narmstrong@baylibre.com
2020-03-17 15:15:08 -07:00
Neil Armstrong f12a463d2f arm64: dts: meson-g12: add the SPIFC nodes
Add the controller and pinctrl nodes to enable the SPI Flash Controller
on the Amlogic G12A and compatible SoCs.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Link: https://lore.kernel.org/r/20200313090713.15147-3-narmstrong@baylibre.com
2020-03-17 15:15:08 -07:00
Neil Armstrong 4d2cb376e5 arm64: dts: meson-g12: split emmc pins to select 4 or 8 bus width
The Khadas VIM3 shares the eMMC pins 4 to 7 with the SPI NOR, in order
to enable the eMMC and the SPI NOR interface, we need to omit the
4 last pins from the eMMC pinctrl.

As it was done for the Khadas VIM2, split the eMMC pinctrls in ctrl, data
and ds pins with either 4bits data or 8bits data, and update the current
board accordingly.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Link: https://lore.kernel.org/r/20200313090713.15147-2-narmstrong@baylibre.com
2020-03-17 15:14:44 -07:00
glider@google.com c17a290f7e arm64: define __alloc_zeroed_user_highpage
When running the kernel with init_on_alloc=1, calling the default
implementation of __alloc_zeroed_user_highpage() from include/linux/highmem.h
leads to double-initialization of the allocated page (first by the page
allocator, then by clear_user_page().
Calling alloc_page_vma() with __GFP_ZERO, similarly to e.g. x86, seems
to be enough to ensure the user page is zeroed only once.

Signed-off-by: Alexander Potapenko <glider@google.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2020-03-17 18:36:57 +00:00
Gavin Shan d22b115cbf arm64/kernel: Simplify __cpu_up() by bailing out early
The function __cpu_up() is invoked to bring up the target CPU through
the backend, PSCI for example. The nested if statements won't be needed
if we bail out early on the following two conditions where the status
won't be checked. The code looks simplified in that case.

   * Error returned from the backend (e.g. PSCI)
   * The target CPU has been marked as onlined

Signed-off-by: Gavin Shan <gshan@redhat.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
2020-03-17 18:31:10 +00:00
韩科才 24b2cce91f arm64: remove redundant blank for '=' operator
remove redundant blank for '=' operator, it may be more elegant.

Signed-off-by: hankecai <hankecai@vivo.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2020-03-17 18:23:29 +00:00
Li Tao c2f4afdc3f arm64: kexec_file: Fixed code style.
Remove unnecessary blank.

Signed-off-by: Li Tao <tao.li@vivo.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2020-03-17 18:23:20 +00:00
Zheng Wei 62b9562a1c arm64: add blank after 'if'
add blank after 'if' for armv8_deprecated_init()
to make it comply with kernel coding style.

Signed-off-by: Zheng Wei <wei.zheng@vivo.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2020-03-17 18:22:53 +00:00
韩科才 0c837c4f73 arm64: fix spelling mistake "ca not" -> "cannot"
There is a spelling mistake in the comment, Fix it.

Signed-off-by: hankecai <hankecai@bbktel.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2020-03-17 18:22:40 +00:00
Bjorn Andersson dfaf16014f arm64: dts: qcom: sdm845-mtp: Relocate remoteproc firmware
Update the firmware-name of the remoteproc nodes to mimic the firmware
structure on other 845 devices.

Reviewed-by: Sibi Sankar <sibis@codeaurora.org>
Link: https://lore.kernel.org/r/20200302020757.551483-1-bjorn.andersson@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-03-16 22:20:34 -07:00
Alex Elder 392a585583 arm64: dts: sdm845: add IPA information
Add IPA-related nodes and definitions to "sdm845.dtsi".

Signed-off-by: Alex Elder <elder@linaro.org>
Link: https://lore.kernel.org/r/20200313115237.10491-2-elder@linaro.org
[bjorn: Moved modem-init to cheza.dtsi]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-03-16 22:16:35 -07:00
Vivek Unune 68c33366a9 arm64: dts: rockchip: Add Hugsun X99 power led
Remove pwm0 node as it interferes with power LED gpio.

Tested with LibreElec linux-next-20200305

Signed-off-by: Vivek Unune <npcomplete13@gmail.com>
Link: https://lore.kernel.org/r/20200313230513.123049-1-npcomplete13@gmail.com
[split out led addition into separate patch]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-03-17 01:49:03 +01:00
Vivek Unune cd2fd91e3d arm64: dts: rockchip: Add Hugsun X99 IR receiver
Add the IR receiver and its associated pinctrl entry.

Tested with LibreElec linux-next-20200305

Signed-off-by: Vivek Unune <npcomplete13@gmail.com>
Link: https://lore.kernel.org/r/20200313230513.123049-1-npcomplete13@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-03-17 01:48:12 +01:00
Johan Jonker 77460b3d7d arm64: dts: rockchip: remove clock-names property from 'generic-ohci' nodes
A test with the command below gives for example this error:

arch/arm64/boot/dts/rockchip/rk3328-evb.dt.yaml: usb@ff5d0000:
'clock-names' does not match any of the regexes: 'pinctrl-[0-9]+'

'clock-names' is not a valid property name for usb_host nodes with
compatible string 'generic-ohci', so remove them.

make ARCH=arm64 dtbs_check
DT_SCHEMA_FILES=Documentation/devicetree/bindings/usb/generic-ohci.yaml

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Link: https://lore.kernel.org/r/20200312171441.21144-4-jbx6244@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-03-17 01:39:37 +01:00
Johan Jonker 6a92e52bae arm64: dts: rockchip: remove clock-names property from 'generic-ehci' nodes
A test with the command below gives for example this error:

arch/arm64/boot/dts/rockchip/rk3328-evb.dt.yaml: usb@ff5c0000:
'clock-names' does not match any of the regexes: 'pinctrl-[0-9]+'

'clock-names' is not a valid property name for usb_host nodes with
compatible string 'generic-ehci', so remove them.

make ARCH=arm64 dtbs_check
DT_SCHEMA_FILES=Documentation/devicetree/bindings/usb/generic-ehci.yaml

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Link: https://lore.kernel.org/r/20200312171441.21144-3-jbx6244@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-03-17 01:39:26 +01:00
Johan Jonker a2712bfb1c arm64: dts: rockchip: remove properties from spdif node RK3399 Excavator
An expermental test with the command below gives this error:

arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dt.yaml:
spdif@ff870000:
'i2c-scl-falling-time-ns', 'i2c-scl-rising-time-ns', 'power-domains'
do not match any of the regexes: 'pinctrl-[0-9]+'

'i2c-scl-falling-time-ns', 'i2c-scl-rising-time-ns'
are not valid properties for 'spdif' nodes, so remove them.

make ARCH=arm64 dtbs_check
DT_SCHEMA_FILES=Documentation/devicetree/bindings/sound/rockchip-spdif.yaml

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Link: https://lore.kernel.org/r/20200312172240.21362-1-jbx6244@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-03-17 01:39:20 +01:00
Madalin Bucur d79e9d7c1e arm64: dts: ls1046ardb: set RGMII interfaces to RGMII_ID mode
The correct setting for the RGMII ports on LS1046ARDB is to
enable delay on both Rx and Tx so the interface mode used must
be PHY_INTERFACE_MODE_RGMII_ID.

Since commit 1b3047b520 ("net: phy: realtek: add support for
configuring the RX delay on RTL8211F") the Realtek 8211F PHY driver
has control over the RGMII RX delay and it is disabling it for
RGMII_TXID. The LS1046ARDB uses two such PHYs in RGMII_ID mode but
in the device tree the mode was described as "rgmii".

Changing the phy-connection-type to "rgmii-id" to address the issue.

Fixes: 3fa395d2c4 ("arm64: dts: add LS1046A DPAA FMan nodes")
Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-03-16 14:58:33 -07:00
Madalin Bucur 4022d808c4 arm64: dts: ls1043a-rdb: correct RGMII delay mode to rgmii-id
The correct setting for the RGMII ports on LS1043ARDB is to
enable delay on both Rx and Tx so the interface mode used must
be PHY_INTERFACE_MODE_RGMII_ID.

Since commit 1b3047b520 ("net: phy: realtek: add support for
configuring the RX delay on RTL8211F") the Realtek 8211F PHY driver
has control over the RGMII RX delay and it is disabling it for
RGMII_TXID. The LS1043ARDB uses two such PHYs in RGMII_ID mode but
in the device tree the mode was described as "rgmii_txid".
This issue was not apparent at the time as the PHY driver took the
same action for RGMII_TXID and RGMII_ID back then but it became
visible (RX no longer working) after the above patch.

Changing the phy-connection-type to "rgmii-id" to address the issue.

Fixes: bf02f2ffe5 ("arm64: dts: add LS1043A DPAA FMan support")
Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-03-16 14:58:32 -07:00
Neil Armstrong 5fa86f4f72 arm64: dts: meson-g12-common: add spicc controller nodes
This adds the controller and pinctrl nodes for the Amlogic G12A SPICC
controllers.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Link: https://lore.kernel.org/r/20200313091401.15888-1-narmstrong@baylibre.com
2020-03-16 14:42:25 -07:00
Paolo Bonzini 1c482452d5 KVM: s390: Features and Enhancements for 5.7 part1
1. Allow to disable gisa
 2. protected virtual machines
   Protected VMs (PVM) are KVM VMs, where KVM can't access the VM's
   state like guest memory and guest registers anymore. Instead the
   PVMs are mostly managed by a new entity called Ultravisor (UV),
   which provides an API, so KVM and the PV can request management
   actions.
 
   PVMs are encrypted at rest and protected from hypervisor access
   while running.  They switch from a normal operation into protected
   mode, so we can still use the standard boot process to load a
   encrypted blob and then move it into protected mode.
 
   Rebooting is only possible by passing through the unprotected/normal
   mode and switching to protected again.
 
   One mm related patch will go via Andrews mm tree ( mm/gup/writeback:
   add callbacks for inaccessible pages)
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Merge tag 'kvm-s390-next-5.7-1' of git://git.kernel.org/pub/scm/linux/kernel/git/kvms390/linux into HEAD

KVM: s390: Features and Enhancements for 5.7 part1

1. Allow to disable gisa
2. protected virtual machines
  Protected VMs (PVM) are KVM VMs, where KVM can't access the VM's
  state like guest memory and guest registers anymore. Instead the
  PVMs are mostly managed by a new entity called Ultravisor (UV),
  which provides an API, so KVM and the PV can request management
  actions.

  PVMs are encrypted at rest and protected from hypervisor access
  while running.  They switch from a normal operation into protected
  mode, so we can still use the standard boot process to load a
  encrypted blob and then move it into protected mode.

  Rebooting is only possible by passing through the unprotected/normal
  mode and switching to protected again.

  One mm related patch will go via Andrews mm tree ( mm/gup/writeback:
  add callbacks for inaccessible pages)
2020-03-16 18:19:34 +01:00