Commit Graph

99 Commits

Author SHA1 Message Date
Christoph Hellwig 002e67454f dma-direct: rename dma_noop to dma_direct
The trivial direct mapping implementation already does a virtual to
physical translation which isn't strictly a noop, and will soon learn
to do non-direct but linear physical to dma translations through the
device offset and a few small tricks.  Rename it to a better fitting
name.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Vladimir Murzin <vladimir.murzin@arm.com>
2018-01-15 09:35:06 +01:00
Christoph Hellwig c5cd037d1c dma-mapping: provide a generic asm/dma-mapping.h
For architectures that just use the generic dma_noop_ops we can provide
a generic version of dma-mapping.h.

Signed-off-by: Christoph Hellwig <hch@lst.de>
2018-01-15 09:35:05 +01:00
David Howells 0500871f21 Construct init thread stack in the linker script rather than by union
Construct the init thread stack in the linker script rather than doing it
by means of a union so that ia64's init_task.c can be got rid of.

The following symbols are then made available from INIT_TASK_DATA() linker
script macro:

	init_thread_union
	init_stack

INIT_TASK_DATA() also expands the region to THREAD_SIZE to accommodate the
size of the init stack.  init_thread_union is given its own section so that
it can be placed into the stack space in the right order.  I'm assuming
that the ia64 ordering is correct and that the task_struct is first and the
thread_info second.

Signed-off-by: David Howells <dhowells@redhat.com>
Tested-by: Tony Luck <tony.luck@intel.com>
Tested-by: Will Deacon <will.deacon@arm.com> (arm64)
Tested-by: Palmer Dabbelt <palmer@sifive.com>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
2018-01-09 23:21:02 +00:00
Christoph Hellwig b8ee205af4 riscv: remove the unused dma_capable helper
Signed-off-by: Christoph Hellwig <hch@lst.de>
2018-01-09 16:28:39 +01:00
Christoph Hellwig 1125203c13
riscv: rename SR_* constants to match the spec
Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-01-07 15:14:39 -08:00
Christoph Hellwig c163fb38ca
riscv: remove CONFIG_MMU ifdefs
The RISC-V port doesn't suport a nommu mode, so there is no reason
to provide some code only under a CONFIG_MMU ifdef.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-01-07 15:14:39 -08:00
Palmer Dabbelt 9e49a4ed07
RISC-V: Make __NR_riscv_flush_icache visible to userspace
We were hoping to avoid making this visible to userspace, but it looks
like we're going to have to because QEMU's user-mode emulation doesn't
want to emulate a vDSO.  Having vDSO-only system calls was a bit
unothodox anyway, so I think in this case it's OK to just make the
actual system call number public.

This patch simply moves the definition of __NR_riscv_flush_icache
availiable to userspace, which results in the deletion of the now empty
vdso-syscalls.h.

Changes since v1:

* I've moved the definition into uapi/asm/syscalls.h rathen than
  uapi/asm/unistd.h.  This allows me to keep asm/unistd.h, so we can
  keep the syscall table macros sane.
* As a side effect of the above, this no longer disables all system
  calls on RISC-V.  Whoops!

Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-01-07 15:14:37 -08:00
Karsten Merker 33c57c0d3c
RISC-V: Add a basic defconfig
This patch provides a basic defconfig for the RISC-V
architecture that enables enough kernel features to run a
basic Linux distribution on qemu's "virt" board for native
software development. Features include:

- serial console
- virtio block and network device support
- VFAT and ext2/3/4 filesystem support
- NFS client and NFS rootfs support
- an assortment of other kernel features required for
  running systemd

It also enables a number of drivers for physical hardware
that target the "SiFive U500" SoC and the corresponding
development platform.  These include:

- PCIe host controller support for the FPGA-based U500
  development platform (PCIE_XILINX)
- USB host controller support (OHCI/EHCI/XHCI)
- USB HID (keyboard/mouse) support
- USB mass storage support (bulk and UAS)
- SATA support (AHCI)
- ethernet drivers (MACB for a SoC-internal MAC block, microsemi
  ethernet phy, E1000E and R8169 for PCIe-connected external devices)
- DRM and framebuffer console support for PCIe-connected
  Radeon graphics chips

Signed-off-by: Karsten Merker <merker@debian.org>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-01-07 15:14:36 -08:00
Stephen Boyd e0af0c1610 arch: Remove clkdev.h asm-generic from Kbuild
Now that every architecture is using the generic clkdev.h file
and we no longer include asm/clkdev.h anywhere in the tree, we
can remove it.

Cc: Russell King <linux@armlinux.org.uk>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Cc: <linux-arch@vger.kernel.org>
Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> [m68k]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2018-01-03 09:02:11 -08:00
Palmer Dabbelt 27b0174525
RISC-V: Remove unused CONFIG_HVC_RISCV_SBI code
This is code that probably should never have made it into the kernel in
the first place: it depends on a driver that hadn't been reviewed yet.
During the HVC_SBI_RISCV review process a better way of doing this was
suggested, but that means this code is defunct.  It's compile-time
disabled in 4.15 because the driver isn't in, so I think it's safe to
just remove this for now.

CC: Greg KH <gregkh@linuxfoundation.org>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2017-12-11 07:51:09 -08:00
Palmer Dabbelt 3cfa500808
RISC-V: Resurrect smp_mb__after_spinlock()
I removed this last week because of an incorrect comment:
smp_mb__after_spinlock() is actually still used, and is necessary on
RISC-V.  It's been resurrected, with a comment that describes what it
actually does this time.  Thanks to Andrea for finding the bug!

Fixes: 3343eb6806 ("RISC-V: Remove smb_mb__{before,after}_spinlock()")
CC: Andrea Parri <parri.andrea@gmail.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2017-12-11 07:51:07 -08:00
Dan Carpenter 86ad5c97ce
RISC-V: Logical vs Bitwise typo
In the current code, there is a ! logical NOT where a bitwise ~ NOT was
intended.  It means that we never return -EINVAL.

Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2017-12-11 07:51:06 -08:00
Hendrik Brueckner c895f6f703 bpf: correct broken uapi for BPF_PROG_TYPE_PERF_EVENT program type
Commit 0515e5999a ("bpf: introduce BPF_PROG_TYPE_PERF_EVENT
program type") introduced the bpf_perf_event_data structure which
exports the pt_regs structure.  This is OK for multiple architectures
but fail for s390 and arm64 which do not export pt_regs.  Programs
using them, for example, the bpf selftest fail to compile on these
architectures.

For s390, exporting the pt_regs is not an option because s390 wants
to allow changes to it.  For arm64, there is a user_pt_regs structure
that covers parts of the pt_regs structure for use by user space.

To solve the broken uapi for s390 and arm64, introduce an abstract
type for pt_regs and add an asm/bpf_perf_event.h file that concretes
the type.  An asm-generic header file covers the architectures that
export pt_regs today.

The arch-specific enablement for s390 and arm64 follows in separate
commits.

Reported-by: Thomas Richter <tmricht@linux.vnet.ibm.com>
Fixes: 0515e5999a ("bpf: introduce BPF_PROG_TYPE_PERF_EVENT program type")
Signed-off-by: Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
Reviewed-and-tested-by: Thomas Richter <tmricht@linux.vnet.ibm.com>
Acked-by: Alexei Starovoitov <ast@kernel.org>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Daniel Borkmann <daniel@iogearbox.net>
Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
2017-12-05 15:02:40 +01:00
Al Viro 5e454b5457 riscv: use linux/uaccess.h, not asm/uaccess.h...
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2017-12-04 18:01:01 -05:00
Palmer Dabbelt 3b62de26cf
RISC-V: Fixes for clean allmodconfig build
Olaf said: Here's a short series of patches that produces a working
allmodconfig. Would be nice to see them go in so we can add build
coverage.

I've dropped patches 8 and 10 from the original set:

* [PATCH 08/10] (RISC-V: Set __ARCH_WANT_RENAMEAT to pick up generic
  version) has a better fix that I've sent out for review, we don't want
  renameat.
* [PATCH 10/10] (input: joystick: riscv has get_cycles) has already been
  taken into Dmitry Torokhov's tree.
2017-12-01 13:31:31 -08:00
Palmer Dabbelt 7382fbdeae
RISC-V: __io_writes should respect the length argument 2017-12-01 13:14:36 -08:00
Palmer Dabbelt 07f8ba7439 RISC-V: User-Visible Changes
This merge contains the user-visible, ABI-breaking changes that we want
to make sure we have in Linux before our first release.   Highlights
include:

* VDSO entries for clock_get/gettimeofday/getcpu have been added.  These
  are simple syscalls now, but we want to let glibc use them from the
  start so we can make them faster later.
* A VDSO entry for instruction cache flushing has been added so
  userspace can flush the instruction cache.
* The VDSO symbol versions for __vdso_cmpxchg{32,64} have been removed,
  as those VDSO entries don't actually exist.

Conflicts:
        arch/riscv/include/asm/tlbflush.h
2017-12-01 13:12:10 -08:00
Palmer Dabbelt da894ff100 RISC-V: __io_writes should respect the length argument
Whoops -- I must have just been being an idiot again.  Thanks to Segher
for finding the bug :).

CC: Segher Boessenkool <segher@kernel.crashing.org>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2017-12-01 13:09:57 -08:00
Palmer Dabbelt 0e710ac652 RISC-V: Clean up an unused include
We used to have some cmpxchg syscalls.  They're no longer there, so we
no longer need the include.

CC: Christoph Hellwig <hch@infradead.org>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2017-11-30 12:58:29 -08:00
Andrew Waterman 921ebd8f2c RISC-V: Allow userspace to flush the instruction cache
Despite RISC-V having a direct 'fence.i' instruction available to
userspace (which we can't trap!), that's not actually viable when
running on Linux because the kernel might schedule a process on another
hart.  There is no way for userspace to handle this without invoking the
kernel (as it doesn't know the thread->hart mappings), so we've defined
a RISC-V specific system call to flush the instruction cache.

This patch adds both a system call and a VDSO entry.  If possible, we'd
like to avoid having the system call be considered part of the
user-facing ABI and instead restrict that to the VDSO entry -- both just
in general to avoid having additional user-visible ABI to maintain, and
because we'd prefer that users just call the VDSO entry because there
might be a better way to do this in the future (ie, one that doesn't
require entering the kernel).

Signed-off-by: Andrew Waterman <andrew@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2017-11-30 12:58:29 -08:00
Andrew Waterman 08f051eda3 RISC-V: Flush I$ when making a dirty page executable
The RISC-V ISA allows for instruction caches that are not coherent WRT
stores, even on a single hart.  As a result, we need to explicitly flush
the instruction cache whenever marking a dirty page as executable in
order to preserve the correct system behavior.

Local instruction caches aren't that scary (our implementations actually
flush the cache, but RISC-V is defined to allow higher-performance
implementations to exist), but RISC-V defines no way to perform an
instruction cache shootdown.  When explicitly asked to do so we can
shoot down remote instruction caches via an IPI, but this is a bit on
the slow side.

Instead of requiring an IPI to all harts whenever marking a page as
executable, we simply flush the currently running harts.  In order to
maintain correct behavior, we additionally mark every other hart as
needing a deferred instruction cache which will be taken before anything
runs on it.

Signed-off-by: Andrew Waterman <andrew@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2017-11-30 12:58:25 -08:00
Olof Johansson 741fc3ff3a RISC-V: Add missing include
Fixes:

include/asm-generic/mm_hooks.h:20:11: warning: 'struct vm_area_struct' declared inside parameter list will not be visible outside of this definition or declaration
include/asm-generic/mm_hooks.h:19:38: warning: 'struct mm_struct' declared inside parameter list will not be visible outside of this definition or declaration

Signed-off-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2017-11-30 10:34:47 -08:00
Olof Johansson 4a41d5dbb0 RISC-V: Use define for get_cycles like other architectures
Signed-off-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2017-11-30 10:12:21 -08:00
Olof Johansson 4bde63286a RISC-V: Provide stub of setup_profiling_timer()
Fixes the following on allmodconfig build:

profile.c:(.text+0x3e4): undefined reference to `setup_profiling_timer'

Signed-off-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2017-11-30 10:12:15 -08:00
Olof Johansson 24948b7ec0 RISC-V: Export some expected symbols for modules
These are the ones needed by current allmodconfig, so add them instead
of everything other architectures are exporting -- the rest can be
added on demand later if needed.

Signed-off-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2017-11-30 10:01:10 -08:00
Olof Johansson 83e7b8769a RISC-V: move empty_zero_page definition to C and export it
Needed by some modules (exported by other architectures).

Signed-off-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2017-11-30 10:01:10 -08:00
Olof Johansson fe2726af9f RISC-V: io.h: type fixes for warnings
include <linux/types.h> for __iomem definition. Also, add volatile to
iounmap() like other architectures have it to avoid "discarding
volatile" warnings from some drivers.

Finally, explicitly promote the base address for INB/OUTB functions to
avoid some old legacy drivers complaining about int-to-ptr promotions.
The drivers are unlikely to work but they're included in allmodconfig
so the warnings are noisy.

Fixes, among other warnings, these with allmodconfig:

../arch/riscv/include/asm/io.h:24:21: error: expected '=', ',', ';', 'asm' or '__attribute__' before '*' token
 extern void __iomem *ioremap(phys_addr_t offset, unsigned long size);

sound/pci/echoaudio/echoaudio.c: In function 'snd_echo_free':
sound/pci/echoaudio/echoaudio.c:1879:10: warning: passing argument 1 of 'iounmap' discards 'volatile' qualifier from pointer target type [-Wdiscarded-qualifiers]

Signed-off-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2017-11-30 10:01:10 -08:00
Olof Johansson 5e6f82b0fe RISC-V: use RISCV_{INT,SHORT} instead of {INT,SHORT} for asm macros
INT and SHORT are used by some drivers that pull in the include files,
so prefixing helps avoid namespace conflicts. Other constructs in the
same file already uses this.

Fixes, among others, these warnings with allmodconfig:

../sound/core/pcm_misc.c:43:0: warning: "INT" redefined
 #define INT __force int

Signed-off-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2017-11-30 10:01:10 -08:00
Olof Johansson 5ddf755e44 RISC-V: use generic serial.h
Fixes this from allmodconfig:

drivers/tty/serial/earlycon.c:27:10: fatal error: asm/serial.h: No such file or directory

Signed-off-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2017-11-30 10:01:10 -08:00
Palmer Dabbelt bf73055273 RISC-V: remove spin_unlock_wait()
This was removed from the other architectures in commit
952111d7db ("arch: Remove spin_unlock_wait() arch-specific
definitions").  That landed between when we got upstream and when our
patches were reviewed, so this is a followup patch.

Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2017-11-28 14:06:31 -08:00
Palmer Dabbelt c901e45a99 RISC-V: `sfence.vma` orderes the instruction cache
This is just a comment change, but it's one that bit me on the mailing
list.  It turns out that issuing a `sfence.vma` enforces instruction
cache ordering in addition to TLB ordering.  This isn't explicitly
called out in the ISA manual, but Andrew will be making that more clear
in a future revision.

CC: Andrew Waterman <andrew@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2017-11-28 14:06:17 -08:00
Palmer Dabbelt 21db403660 RISC-V: Add READ_ONCE in arch_spin_is_locked()
This was just incorrect in the original version.

Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2017-11-28 14:05:04 -08:00
Palmer Dabbelt 9347ce54cd RISC-V: __test_and_op_bit_ord should be strongly ordered
I mis-read the documentation.  After looking at it again the
documentation is actually as clear as it can be, it's just that I didn't
actually read it in order and therefor did the wrong thing.

Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2017-11-28 14:04:05 -08:00
Palmer Dabbelt 3343eb6806 RISC-V: Remove smb_mb__{before,after}_spinlock()
These are obselete.

Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2017-11-28 14:03:55 -08:00
Palmer Dabbelt 61a60d35b7 RISC-V: Remove __smp_bp__{before,after}_atomic
These duplicate the asm-generic definitions are therefor aren't useful.

Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2017-11-28 14:03:48 -08:00
Palmer Dabbelt 8286d51a6c RISC-V: Comment on why {,cmp}xchg is ordered how it is
This is another memory model FIXME.

Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2017-11-28 14:03:29 -08:00
Palmer Dabbelt 4650d02ad2 RISC-V: Remove unused arguments from ATOMIC_OP
Our atomics are generated from a complicated series of preprocessor
macros, each of which is slightly different from the last.  When writing
the macros I'd accidentally left some unused arguments floating around.
This patch removes the unused macro arguments.

Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
2017-11-28 13:53:24 -08:00
Andrew Waterman 28dfbe6ed4 RISC-V: Add VDSO entries for clock_get/gettimeofday/getcpu
For now these are just placeholders that execute the syscall.  We will
later optimize them to avoid kernel crossings, but we'd like to have the
VDSO entries from the first released kernel version to make the ABI
simpler.

Signed-off-by: Andrew Waterman <andrew@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2017-11-27 07:51:39 -08:00
Palmer Dabbelt b7e5a59150 RISC-V: Remove __vdso_cmpxchg{32,64} symbol versions
These were left over from an earlier version of the port.

Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2017-11-27 07:51:39 -08:00
Linus Torvalds b293fca43b RISC-V Port for Linux 4.15 v9
This tag contains the core RISC-V Linux port, which has been through
 nine rounds of review on various mailing lists.  The port is not
 complete: there's some cleanup patches moving through the review
 process, a whole bunch of drivers that need some work, and a lot of
 feature additions that will be needed.
 
 The patches contained in this tag have been through nine rounds of
 review on the various mailing lists.  I have some outstanding cleanup
 patches, but since there's been so much review on these patches I
 thought it would be best to submit them as-is and then submit explicit
 cleanup patches so everyone can review them.  This first patch set is
 big enough that it's a bit of a pain to constantly rewrite, and it's
 caused a few headaches with various contributors.
 
 The port is definately a work in progress.  While what's there builds
 and boots with 4.14, it's a bit hard to actually see anything happen
 because there are no device drivers yet.  I maintain a staging branch
 that contains all the device drivers and cleanup that actually works,
 but those patches won't all be ready for a while.  I'd like to get what
 we currently have into your tree so everyone can start working from a
 single base -- of particular importance is allowing the glibc
 upstreaming process to proceed so we can sort out any possibly lingering
 user-visible ABI problems we might have.
 
 Copied below is the ChangeLog that contains the history of this patch
 set:
 
 (v9) As per suggestions on our v8 patch set, I've split the core architecture code
 out from our drivers and would like to submit this patch set to be included
 into linux-next, with the goal being to be merged in during the next merge
 window.  This patch set is based on 4.14-rc2, but if it's better to have it
 based on something else then I can change it around.
 
 This patch set contains just the core arch code for RISC-V, so while it builds
 an nominally boots, you can't print or take an interrupt so it's not that
 useful.  If you're looking to actually boot a system it would probably be
 better to use the full patch set listed below.
 
 We've collected a handful of tags from reviewers, and the remainder of the
 patch set only got minimal feedback last time.  Here's what changed:
 
  * We now use the device tree to initialize the timer driver so it's less
    tighly coupled with the arch port.
  * I cleaned up the defconfigs -- there's actually now just one, and it's
    empty.  For now I think we're OK with what the kernel sets as defaults, but
    I anticipate we'll begin to expand this as people start to use the port
    more.
  * The VDSO symbols version is sane.
  * We WFI while spinning in the boot loop.
  * A handful of comments have been added.
 
 While there are still a handful of FIXMEs in this patch set, we've started to
 get enough interest from various users and contributors that maintaining an out
 of tree patch set is starting to become a big burden.  Hopefully the patches
 are good enough to merge now, which will at least get everyone working in a
 more reasonable manner as we clean up the remaining issues.
 
 This patch set is also availiable on github
 
   https://github.com/riscv/riscv-linux/tree/riscv-for-submission-v9-arch
 
 as is the entire patch set necessary to get a more functional RISC-V system up
 and running, including a handful of patches that aren't ready for upstream yet.
 
   https://github.com/riscv/riscv-linux/tree/riscv-for-submission-v9
 
 Hopefully I've managed to get everyone's feedback
 
 Here's the change highlights from the whole patch set:
 
 (v8) I know it may not be the ideal time to submit a patch set right now, as
 it's the middle of the merge window, but things have calmed down quite a bit in
 the last month so I thought it would be good to get everyone on the same page.
 There's been a handful of changes since the last patch set, but most of them
 are fairly minor:
 
 * We changed PAGE_OFFSET to allowing mapping more physical memory on 64-bit
   systems.  This is user configurable, as it triggers a different code model
   that generates slightly less efficient code.
 * The device tree binding documentation is back, I'd managed to lose it at some
   point.
 * We now pass the atomic64 test suite.  The SBI timer driver has been
 * refactored.
 
 (v7) It's been a while since my last patch set, but the changes han been fairly
 minimal:
 
  * The PCI cleanup patches have been dropped, we'll do them as a separate patch
    set later.
  * We've the Kconfig entries from CONFIG_ISA_* to CONFIG_RISCV_ISA_*, to make
    grep easier.
  * There have been a handful of memory model related tweaks in I/O land,
    particularly relating the PCI and the upcoming platform specification.
    There are significant comments in the relevant files.  This is still a WIP,
    but I think we're close to getting as good as we're going to get until we
    end up with some more specifications.
 
 (v6) As it's been only a day since the v5 patch set, the changes are pretty
 minimal:
 
  * The patch set is now based on linux-next/master, which I believe is a better
    base now that we're getting closer to upstream.
  * EARLY_PRINTK is no longer an option.  Since the SBI console is reasonable,
    there's no penalty to enabling it (and thus no benefit to disabling it).
  * The mmap syscalls were refactored a bit.
 
 (v5) Things have really started to calm down, so this is fairly similar to the
 v4 patch set.  The most interesting changes include:
 
  * We've moved back to a single patch set.
 
  * SMP support has been fixed, I was accidentally running on a non-SMP
    configuration.  There were various mistakes all over the tree as a result of
    this.
 
  * The cmpxchg syscalls have been removed, as they were deemed a bad idea.  As
    a result, RISC-V Linux systems mandate the A extension.  The corresponding
    Kconfig entry to enable builds on non-A systems has been removed.
 
  * A few more atomic fixes: mostly fence changes, but those resulted in a
    handful of additional macros that were no longer necessary.
 
  * riscv_early_sie has been removed.
 
 (v4) There have only been a few changes since the v3 patch set:
 
  * The cmpxchg64 syscall is no longer enabled on 32-bit systems.  It's not
    possible to provide this on SMP systems, and it's not necessary as glibc
    knows not to call it.
 
  * We provide a ELF_HWCAP so users can determine the ISA of the machine the
    kernel is running on.
 
  * The multi-line comments are in a better form.
 
  * There were a handful of headers that could be replaced with the asm-generic
    versions, and a few unnecessary definitions.
 
  * We no longer use printk, but instead use pr_*.
 
  * A few Kconfig and defconfig entries have been cleaned up.
 
 (v3) A highlight of the changes since the v2 patch set includes:
 
  * We've split out all our drivers into separate patch sets, which I've already
    sent out to the relevant maintainers.  I haven't included those patches in
    this patch set, but some of them are necessary to build our port.  A git
    tree that contains all our patch sets merged together lives at
    <https://github.com/riscv/riscv-linux/tree/riscv-for-submission-v3>.
 
  * The patch set is now split up differently: rather than being split per
    directory it is split per topic.  Hopefully this will make it easier to
    review the port on the mailing list.  The split is a bit rough, so you
    probably still want to look at the patch set as a whole.
 
  * atomic.h has been completely rewritten and is hopefully now correct.  I've
    attempted to sanitize the various other memory model related code as well,
    and I think it should all be sane now aside from a handful of FIXMEs
    commented in the code.
 
  * We've changed the cmpexchg syscall to always exist and to not be
    multiplexed.  There is also a VDSO entry for compare and exchange, which
    allows kernels with the A extension to execute user code without the A
    extension reasonably fast.
 
  * Our user-visible register state now contains enough space for the Q
    extension for 128-bit floating point, as well as a few words to allow
    extensibility to future ISA extensions like the eventual V extension for
    vectors.
 
  * A handful of driver cleanups, but these have been split into separate patch
    sets now so I won't duplicate them here.
 
 (v2) A highlight of the changes since the v1 patch set includes:
 
   * We've split out our drivers into the right places, which means now there's
     a lot more patches.  I'll be submitting these patches to various subsystem
     maintainers and including them in any future RISC-V patch sets until
     they've been merged.
 
   * The SBI console driver has been completely rewritten to use the HVC helpers
     and is now significantly smaller.
 
   * We've begun to use weaker barriers as opposed to just the big "fence".
     There's still some work to do here, specifically:
     - We need fences in the relaxed MMIO functions.
     - The non-relaxed MMIO functions are missing R/W bits on their fences.
     - Many AMOs need the aq and rl bits set.
 
   * We now have thread_info in task_struct.  As a result, sscratch now contains
     TP instead of SP.  This was necessary because thread_info is no longer on
     the stack.
 
   * A few shared routines have been added that we use instead of creating
     another arch copy.
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Merge tag 'riscv-for-linus-4.15-arch-v9-premerge' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/linux

Pull RISC-V architecture support from Palmer Dabbelt:
 "This contains the core RISC-V Linux port, which has been through nine
  rounds of review on various mailing lists. The port is not complete:
  there's some cleanup patches moving through the review process, a
  whole bunch of drivers that need some work, and a lot of feature
  additions that will be needed.

  The patches contained in this tag have been through nine rounds of
  review on the various mailing lists. I have some outstanding cleanup
  patches, but since there's been so much review on these patches I
  thought it would be best to submit them as-is and then submit explicit
  cleanup patches so everyone can review them. This first patch set is
  big enough that it's a bit of a pain to constantly rewrite, and it's
  caused a few headaches with various contributors.

  The port is definately a work in progress. While what's there builds
  and boots with 4.14, it's a bit hard to actually see anything happen
  because there are no device drivers yet. I maintain a staging branch
  that contains all the device drivers and cleanup that actually works,
  but those patches won't all be ready for a while. I'd like to get what
  we currently have into your tree so everyone can start working from a
  single base -- of particular importance is allowing the glibc
  upstreaming process to proceed so we can sort out any possibly
  lingering user-visible ABI problems we might have.

  Copied below is the ChangeLog that contains the history of this patch
  set:

   (v9) As per suggestions on our v8 patch set, I've split the core
        architecture code out from our drivers and would like to submit
        this patch set to be included into linux-next, with the goal
        being to be merged in during the next merge window. This patch
        set is based on 4.14-rc2, but if it's better to have it based on
        something else then I can change it around.

        This patch set contains just the core arch code for RISC-V, so
        while it builds an nominally boots, you can't print or take an
        interrupt so it's not that useful. If you're looking to actually
        boot a system it would probably be better to use the full patch
        set listed below.

        We've collected a handful of tags from reviewers, and the
        remainder of the patch set only got minimal feedback last time.
        Here's what changed:

         - We now use the device tree to initialize the timer driver so
           it's less tighly coupled with the arch port.

         - I cleaned up the defconfigs -- there's actually now just one,
           and it's empty. For now I think we're OK with what the kernel
           sets as defaults, but I anticipate we'll begin to expand this
           as people start to use the port more.

         - The VDSO symbols version is sane.

         - We WFI while spinning in the boot loop.

         - A handful of comments have been added.

        While there are still a handful of FIXMEs in this patch set,
        we've started to get enough interest from various users and
        contributors that maintaining an out of tree patch set is
        starting to become a big burden. Hopefully the patches are good
        enough to merge now, which will at least get everyone working in
        a more reasonable manner as we clean up the remaining issues.

   (v8) I know it may not be the ideal time to submit a patch set right
        now, as it's the middle of the merge window, but things have
        calmed down quite a bit in the last month so I thought it would
        be good to get everyone on the same page. There's been a handful
        of changes since the last patch set, but most of them are fairly
        minor:

         - We changed PAGE_OFFSET to allowing mapping more physical
           memory on 64-bit systems. This is user configurable, as it
           triggers a different code model that generates slightly less
           efficient code.

         - The device tree binding documentation is back, I'd managed to
           lose it at some point.

         - We now pass the atomic64 test suite

         - The SBI timer driver has been refactored.

   (v7) It's been a while since my last patch set, but the changes han
        been fairly minimal:

         - The PCI cleanup patches have been dropped, we'll do them as a
           separate patch set later.

         - We've the Kconfig entries from CONFIG_ISA_* to
           CONFIG_RISCV_ISA_*, to make grep easier.

         - There have been a handful of memory model related tweaks in
           I/O land, particularly relating the PCI and the upcoming
           platform specification. There are significant comments in the
           relevant files. This is still a WIP, but I think we're close
           to getting as good as we're going to get until we end up with
           some more specifications.

   (v6) As it's been only a day since the v5 patch set, the changes are
        pretty minimal:

         - The patch set is now based on linux-next/master, which I
           believe is a better base now that we're getting closer to
           upstream.

         - EARLY_PRINTK is no longer an option. Since the SBI console is
           reasonable, there's no penalty to enabling it (and thus no
           benefit to disabling it).

         - The mmap syscalls were refactored a bit.

   (v5) Things have really started to calm down, so this is fairly
        similar to the v4 patch set. The most interesting changes
        include:

         - We've moved back to a single patch set.

         - SMP support has been fixed, I was accidentally running on a
           non-SMP configuration. There were various mistakes all over
           the tree as a result of this.

         - The cmpxchg syscalls have been removed, as they were deemed a
           bad idea. As a result, RISC-V Linux systems mandate the A
           extension. The corresponding Kconfig entry to enable builds
           on non-A systems has been removed.

         - A few more atomic fixes: mostly fence changes, but those
           resulted in a handful of additional macros that were no
           longer necessary.

         - riscv_early_sie has been removed.

   (v4) There have only been a few changes since the v3 patch set:

         - The cmpxchg64 syscall is no longer enabled on 32-bit systems.
           It's not possible to provide this on SMP systems, and it's
           not necessary as glibc knows not to call it.

         - We provide a ELF_HWCAP so users can determine the ISA of the
           machine the kernel is running on.

         - The multi-line comments are in a better form.

         - There were a handful of headers that could be replaced with
           the asm-generic versions, and a few unnecessary definitions.

         - We no longer use printk, but instead use pr_*.

         - A few Kconfig and defconfig entries have been cleaned up.

   (v3) A highlight of the changes since the v2 patch set includes:

         - We've split out all our drivers into separate patch sets,
           which I've already sent out to the relevant maintainers. I
           haven't included those patches in this patch set, but some of
           them are necessary to build our port.

         - The patch set is now split up differently: rather than being
           split per directory it is split per topic. Hopefully this
           will make it easier to review the port on the mailing list.
           The split is a bit rough, so you probably still want to look
           at the patch set as a whole.

         - atomic.h has been completely rewritten and is hopefully now
           correct. I've attempted to sanitize the various other memory
           model related code as well, and I think it should all be sane
           now aside from a handful of FIXMEs commented in the code.

         - We've changed the cmpexchg syscall to always exist and to not
           be multiplexed. There is also a VDSO entry for compare and
           exchange, which allows kernels with the A extension to
           execute user code without the A extension reasonably fast.

         - Our user-visible register state now contains enough space for
           the Q extension for 128-bit floating point, as well as a few
           words to allow extensibility to future ISA extensions like
           the eventual V extension for vectors.

         - A handful of driver cleanups, but these have been split into
           separate patch sets now so I won't duplicate them here.

   (v2) A highlight of the changes since the v1 patch set includes:

         - We've split out our drivers into the right places, which
           means now there's a lot more patches. I'll be submitting
           these patches to various subsystem maintainers and including
           them in any future RISC-V patch sets until they've been
           merged.

         - The SBI console driver has been completely rewritten to use
           the HVC helpers and is now significantly smaller.

         - We've begun to use weaker barriers as opposed to just the big
           "fence". There's still some work to do here, specifically:
            - We need fences in the relaxed MMIO functions.
            - The non-relaxed MMIO functions are missing R/W bits on their fences.
            - Many AMOs need the aq and rl bits set.

         - We now have thread_info in task_struct. As a result, sscratch
           now contains TP instead of SP. This was necessary because
           thread_info is no longer on the stack.

         - A few shared routines have been added that we use instead of
           creating another arch copy"

Reviewed-by: Arnd Bergmann <arnd@arndb.de>

* tag 'riscv-for-linus-4.15-arch-v9-premerge' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/linux:
  RISC-V: Build Infrastructure
  RISC-V: User-facing API
  RISC-V: Paging and MMU
  RISC-V: Device, timer, IRQs, and the SBI
  RISC-V: Task implementation
  RISC-V: ELF and module implementation
  RISC-V: Generic library routines and assembly
  RISC-V: Atomic and Locking Code
  RISC-V: Init and Halt Code
  dt-bindings: RISC-V CPU Bindings
  lib: Add shared copies of some GCC library routines
  MAINTAINERS: Add RISC-V
2017-11-15 10:49:15 -08:00
Palmer Dabbelt fbe934d69e RISC-V: Build Infrastructure
This patch contains all the build infrastructure that actually enables
the RISC-V port.  This includes Makefiles, linker scripts, and Kconfig
files.  It also contains the only top-level change, which adds RISC-V to
the list of architectures that need a sed run to produce the ARCH
variable when building locally.

Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
2017-09-26 15:26:49 -07:00
Palmer Dabbelt e2c0cdfba7 RISC-V: User-facing API
This patch contains code that is in some way visible to the user:
including via system calls, the VDSO, module loading and signal
handling.  It also contains some generic code that is ABI visible.

Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
2017-09-26 15:26:48 -07:00
Palmer Dabbelt 07037db5d4 RISC-V: Paging and MMU
This patch contains code to manage the RISC-V MMU, including definitions
of the page tables and the page walking code.

Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
2017-09-26 15:26:47 -07:00
Palmer Dabbelt 6d60b6ee0c RISC-V: Device, timer, IRQs, and the SBI
This patch contains code that interfaces with devices that are mandated
by the RISC-V supervisor specification and that don't have explicit
drivers anywhere else in the tree.  This includes the staticly defined
interrupts, the CSR-mapped timer, and virtualized SBI devices.

Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
2017-09-26 15:26:47 -07:00
Palmer Dabbelt 7db91e57a0 RISC-V: Task implementation
This patch contains the implementation of tasks on RISC-V, most of which
is involved in task switching.

Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
2017-09-26 15:26:46 -07:00
Palmer Dabbelt 2129a235c0 RISC-V: ELF and module implementation
This patch contains the code that interfaces with ELF objects on RISC-V
systems, the vast majority of which is present to load kernel modules.

Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
2017-09-26 15:26:46 -07:00
Palmer Dabbelt 5d8544e2d0 RISC-V: Generic library routines and assembly
This patch contains code that is more specific to the RISC-V ISA than it
is to Linux.  It contains string and math operations, C wrappers for
various assembly instructions, stack walking code, and uaccess.

Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
2017-09-26 15:26:45 -07:00
Palmer Dabbelt fab957c11e RISC-V: Atomic and Locking Code
This contains all the code that directly interfaces with the RISC-V
memory model.  While this code corforms to the current RISC-V ISA
specifications (user 2.2 and priv 1.10), the memory model is somewhat
underspecified in those documents.  There is a working group that hopes
to produce a formal memory model by the end of the year, but my
understanding is that the basic definitions we're relying on here won't
change significantly.

Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
2017-09-26 15:26:45 -07:00
Palmer Dabbelt 76d2a0493a RISC-V: Init and Halt Code
This contains the various __init C functions, the initial assembly
kernel entry point, and the code to reset the system.  When a file was
init-related this patch contains the entire file.

Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
2017-09-26 15:26:44 -07:00