We don't need to change those dividers if bclk and mclk remains the same
directions and values.
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
According to Reference Manual -- ESAI Initialization chapter, as the
standard procedure of ESAI personal reset, the PCRC and PRRC registers
should be remained in its reset value and then configured after T/RCCR
and T/RCR configurations's done but before TE/RE's enabling.
So this patch moves PCRC and PRRC settings to the end of hw_params().
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
ESAI can only output EXTAL clock source directly. But for FSYS clock source,
ESAI can not output it without getting through PSR PM dividers.
So this patch adds an extra check in the code.
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
The range here from 1 to 16 is confined to FP divider only while the
sck_div indicates if the calculation contains PSR and PM dividers. So
for the case using PSR and PM since the sck_div is true, the range of
ratio would simply become bigger than 16.
So this patch fixes the condition here and adds one line comments to
make the purpose here clear.
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Use the precise definition of 'ret', which will be used for
the error check.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Acked-by: Nicolin Chen <Guangyu.Chen@freescale.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
This patch add .xlate_tdm_slot_mask support for ESAI, and this will
generate the TDM slot TX and RX masks.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
For most platforms, the CPU and ESAI device is in the same endianess
mode. While for the LS1 platform, the CPU is in LE mode and the ESAI
is in BE mode.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Acked-by: Nicolin Chen <Guangyu.Chen@freescale.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
clk_prepare_enable() may fail, so let's check its return value and propagate it
in the case of error.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
This patch implements a device-tree-only CPU DAI driver for Freescale ESAI
controller that supports:
- 12 channels playback and 8 channels record.
[ Some of the inner transmitters and receivers are sharing same group of
pins. So the maxmium 12 output or 8 input channels are only valid if
there is no pin conflict occurring to it. ]
- Independent (asynchronous mode) or shared (synchronous mode) transmit and
receive sections with separate or shared internal/external clocks and frame
syncs, operating in Master or Slave mode.
[ Current ALSA seems not to allow CPU DAI drivers to configure DAI format
separately for PLAYBACK and CAPTURE. So this first version only supports
the case that uses the same DAI format for both directions. ]
- Various DAI formats: I2S, Left-Justified, Right-Justified, DSP-A and DSP-B.
- Programmable word length (8, 16, 20 or 24bits)
- Flexible selection between system clock or external oscillator as input
clock source, programmable internal clock divider and frame sync generation.
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Mark Brown