i.MX27 have only one PWM, so index from PWM devicetree node removed.
Signed-off-by: Alexander Shiyan <eagle.alexander923@gmail.com>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This patch adds the missing (Symmetric/Asymmetric Hashing and Random
Accelerator) SAHARA2 devicetree node for i.MX27 CPUs.
Signed-off-by: Alexander Shiyan <eagle.alexander923@gmail.com>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
- update codec, pmic, usb hub for Arndale
- add exynos4412-trats 2 board dt
- update camera, spi, sensor for Trats2
- update fimc, sensor for Trats
- add support tmu for exynos5440
- add support g2d for exynos5250
- correct camera pinctrl for exynos4x12
- add support camera subsystem for exynos4
- add support basic pm domain, fimd, dp for exynos5420
- add support secure-firmware for OrigenQuad
- update mfc and add support mfc for exynos5420
- add usb host node for exynos4
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Merge tag 'samsung-dt-1' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/dt
From Kukjin Kim:
Samsung Exynos DT updates for v3.12
- update codec, pmic, usb hub for Arndale
- add exynos4412-trats 2 board dt
- update camera, spi, sensor for Trats2
- update fimc, sensor for Trats
- add support tmu for exynos5440
- add support g2d for exynos5250
- correct camera pinctrl for exynos4x12
- add support camera subsystem for exynos4
- add support basic pm domain, fimd, dp for exynos5420
- add support secure-firmware for OrigenQuad
- update mfc and add support mfc for exynos5420
- add usb host node for exynos4
* tag 'samsung-dt-1' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: (38 commits)
ARM: dts: Add USB host node for Exynos4
ARM: dts: add audio clock controller for exynos5420
ARM: dts: Correct the /include entry on exynos5420 dtsi file
ARM: dts: Add MFC node for exynos 5420
ARM: dts: Update 5250 MFC node
ARM: dts: Remove unsused MFC clock from exynos4
ARM: dts: Update clocks entry in MFC binding documentation
ARM: dts: Hook up internal PHY on Arndale
ARM: dts: Enable USB hub on Arndale
ARM: dts: Add secure-firmware boot support for OrigenQaud board
ARM: dts: Add pin state information for DP HPD support to Exynos5420
ARM: dts: Add DP controller DT node to exynos5420 SoC
ARM: dts: Update DP controller DT Node for Exynos5 based SoCs
ARM: dts: Add FIMD DT node to exynos5420 DTS files
ARM: dts: Add basic PM domains for EXYNOS5420
ARM: dts: Update FIMD DT node for Exynos5 SoCs
ARM: dts: Move display-timing information inside FIMD DT node for exynos5250
ARM: dts: Add S5K5BA sensor regulator definitions for Trats board
ARM: dts: Add Exynos4210 SoC camera port pinctrl nodes
ARM: dts: Add FIMC nodes for Exynos4210 Trats board
...
Signed-off-by: Kevin Hilman <khilman@linaro.org>
This fixes a regression exposed during the merge window by commit
9f310de "ARM: tegra: fix VBUS regulator GPIO polarity in DT"; namely that
USB VBUS doesn't get turned on, so USB devices are not detected. This
affects the internal USB port on TrimSlice (i.e. the USB->SATA bridge, to
which the SSD is connected) and the external port(s) on Seaboard/
Springbank and Whistler.
The Tegra DT as written in v3.11 allows two paths to enable USB VBUS:
1) Via the legacy DT binding for the USB controller; it can directly
acquire a VBUS GPIO and activate it.
2) Via a regulator for VBUS, which is referenced by the new DT binding
for the USB controller.
Those two methods both use the same GPIO, and hence whichever of the
USB controller and regulator gets probed first ends up owning the GPIO.
In practice, the USB driver only supports path (1) above, since the
patches to support the new USB binding are not present until v3.12:-(
In practice, the regulator ends up being probed first and owning the
GPIO. Since nothing enables the regulator (the USB driver code is not
yet present), the regulator ends up being turned off. This originally
caused no problem, because the polarity in the regulator definition was
incorrect, so attempting to turn off the regulator actually turned it
on, and everything worked:-(
However, when testing the new USB driver code in v3.12, I noticed the
incorrect polarity and fixed it in commit 9f310de "ARM: tegra: fix VBUS
regulator GPIO polarity in DT". In the context of v3.11, this patch then
caused the USB VBUS to actually turn off, which broke USB ports with VBUS
control. I got this patch included in v3.11-rc1 since it fixed a bug in
device tree (incorrect polarity specification), and hence was suitable to
be included early in the rc series. I evidently did not test the patch at
all, or correctly, in the context of v3.11, and hence did not notice the
issue that I have explained above:-(
Fix this by making the USB VBUS regulators always enabled. This way, if
the regulator owns the GPIO, it will always be turned on, even if there
is no USB driver code to request the regulator be turned on. Even
ignoring this bug, this is a reasonable way to configure the HW anyway.
If this patch is applied to v3.11, it will cause a couple pretty trivial
conflicts in tegra20-{trimslice,seaboard}.dts when creating v3.12, since
the context right above the added lines changed in patches destined for
v3.12.
Reported-by: Kyle McMartin <kmcmarti@redhat.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
The Cubieboard2 is the successor of the first Cubieboard, and shares the
same hardware, except that the Allwinner A10 found initially has been
replaced by an Allwinner A20.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The A20-olinuxino Micro has a LED connected to the PH2 pin. Use the
gpio-led driver to enable the control over this LED.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Instead of relying on the bootloader to mux the UART pins properly, do
it on our own and register the rightful pins for the A20-olinuxino in
the DT using pinctrl.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The UARTs on the A20 can be muxed to several pins. Add a few options to
the DTSI so that we can start using them in the boards' DT.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The PIO controller is responsible for the GPIO/muxing/external
interrupts handling. Now that we have support for the A20 pin set in the
pinctrl driver, we can start using it in the DTSI.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The A31 has a different set of pins than the one found on the A10 and
A13. Now that we have support for the A31 pin set in the pinctrl driver,
we can enable it in the DTSI with its own compatible.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
- Cleanups and few fixes to the DTSI
- A few additions to the A10s olinuxino board
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Merge tag 'sunxi-dt-for-3.12' of https://github.com/mripard/linux into next/dt
Allwinner sunXi DT additions for 3.12
- Cleanups and few fixes to the DTSI
- A few additions to the A10s olinuxino board
* tag 'sunxi-dt-for-3.12' of https://github.com/mripard/linux:
ARM: sunxi: dt: Add device tree for Mele A1000
ARM: sun5i: dt: Fix A13 SoC bus base address
ARM: sun5i: a13: Remove useless simple-bus reg property
ARM: sun5i: dt: Fix A10s SoC bus base address
ARM: sun5i: a10s: Remove useless simple-bus reg property
ARM: sun4i: dt: Fix A10 SoC bus base address
ARM: sun4i: a10: Remove useless simple-bus reg property
ARM: sunxi: make the leds' names conform to the current naming convention
ARM: sun5i: dt: Add AT24 device on A10S-OLinuXino-Micro
ARM: sun5i: dt: Enable I2C controllers on A10S-OLinuXino-Micro
ARM: sun5i: dt: Add I2C controller nodes to the A10S dtsi
ARM: sun5i: dt: Add I2C muxings for sun5i A10S
Signed-off-by: Kevin Hilman <khilman@linaro.org>
DT kernel on da850-evm comes up with garbled UART logs. This is because
of mismatch in actual module clock rate and rate specified(clock-frequency)
in DT blob. kernel should not assume or depend on bootloaders clock
configuration, instead let it find the clock rate at runtime.
Issue discussed here before arriving on this implementation:
"ARM: davinci: da850 evm: update clock rate for UART 1/2 DT nodes"
https://patchwork.kernel.org/patch/2162271/
Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Add ethernet device tree node information and pinmux for mii to da850 by
providing interrupt details and local mac address.
Signed-off-by: Lad, Prabhakar <prabhakar.csengg@gmail.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Add mdio device tree node information to da850 by
providing register details and bus frequency of mdio.
Signed-off-by: Lad, Prabhakar <prabhakar.csengg@gmail.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
The sam9x5ek board has 2 jacks:
headphone wired on RHPOUT/LHPOUT of the wm8731
line in wired on LLINEIN/RLINEIN of the wm8731
Signed-off-by: Richard Genoud <richard.genoud@gmail.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Enable the SSC needed for the WM8731 codec
Signed-off-by: Richard Genoud <richard.genoud@gmail.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
The WM8731 codec on sam9x5ek board is on i2c, address 1A
Signed-off-by: Richard Genoud <richard.genoud@gmail.com>
Acked-by: Mark Brown <broonie@linaro.org>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
The PQFP version have only 3 gpio banks (A, B & C).
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
[nicolas.ferre@atmel.com: correct typo in "status" property]
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Correct pin number of gpio-key for at91sam9n12ek board.
The pioB4 is connect to LED, the pioB3 use as gpio-key.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
ARM Performance Monitor Units are available on the sama5d3, add the support in
the dtsi.
Tested with perf and oprofile on the sama5d31ek.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
pinctrl-names was missing causing mmc pinctrl to never be requested.
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com>
[nicolas.ferre@atmel.com: added a commit message taken from Ludovic]
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Add DT property to tell the regulator to register pm_power_off to make
"shutdown" work.
Signed-off-by: Bill Huang <bilhuang@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Kevin Hilman <khilman@linaro.org>
This branch contains all *.dts (device tree) changes for Tegra.
New features enabled are:
* PMICs on Dalmore
* CPU power-gating on Dalmore
* HDMI output on Beaver
* LP1 system suspend mode on almost all boards
* PCIe support on numerous Tegra20/30 boards
* USB support on Tegra30/114 boards
* Audio capture on Beaver and Dalmore
* Temperature sensor on Cardhu.
... along with a few DT cleanups.
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Merge tag 'tegra-for-3.12-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/dt
From: Stephen Warren:
ARM: tegra: device tree changes for 3.12
This branch contains all *.dts (device tree) changes for Tegra.
New features enabled are:
* PMICs on Dalmore
* CPU power-gating on Dalmore
* HDMI output on Beaver
* LP1 system suspend mode on almost all boards
* PCIe support on numerous Tegra20/30 boards
* USB support on Tegra30/114 boards
* Audio capture on Beaver and Dalmore
* Temperature sensor on Cardhu.
... along with a few DT cleanups.
* tag 'tegra-for-3.12-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: (25 commits)
ARM: tegra: add Mic Jack to Dalmore device tree
ARM: tegra: add Mic Jack to Beaver device tree
ARM: tegra: add USB DT entries for Tegra114, Dalmore
ARM: tegra: add USB DT entries for Tegra30
ARM: dts: tegra: Increase prefetchable PCI memory space
ARM: tegra: Fix Beaver's PCIe lane configuration
ARM: tegra: Enable PCIe controller on Beaver
ARM: tegra: Enable PCIe controller on Cardhu
ARM: tegra: Add Tegra30 PCIe support
ARM: tegra: trimslice: Initialize PCIe from DT
ARM: tegra: harmony: Initialize PCIe from DT
ARM: tegra: tec: Add PCIe support
ARM: tegra: tamonten: Add PCIe support
ARM: tegra: Add Tegra20 PCIe support to DT
ARM: tegra: enable LP1 suspend mode
ARM: tegra: beaver: Enable HDMI output
ARM: tegra: use TEGRA_GPIO() in a couple more places
ARM: tegra: dalmore: fix the irq trigger type of Palmas MFD device
ARM: tegra: define valid function names in DT document
ARM: tegra: dalmore: add PM configurations for PMC
...
development cycle:
- Various cleanups like remove non-existant hardware from
the Snowball device tree, prefix all files with "ste-*"
- External regulators
- Documentation updates
- Delete some minor dangling platform data
- Pin control settings for U8540 through DT
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Merge tag 'ux500-devicetree-for-v3.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson into next/dt
From: Linus Walleij:
Ux500 device tree enablement base for the v3.12
development cycle:
- Various cleanups like remove non-existant hardware from
the Snowball device tree, prefix all files with "ste-*"
- External regulators
- Documentation updates
- Delete some minor dangling platform data
- Pin control settings for U8540 through DT
* tag 'ux500-devicetree-for-v3.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson: (22 commits)
ARM: ux500: fix devicetree builds
ARM: ux500: Remove u9540.dts as it's been replaced
ARM: ux500: Apply a ste-* prefix onto dbx5x0.dtsi
ARM: ux500: Apply a ste-* prefix onto stuib.dtsi
ARM: ux500: Apply a ste-* prefix onto hrefv60plus.dts
ARM: ux500: Apply a ste-* prefix onto hrefprev60.dts Signed-off-by: Lee Jones <lee.jones@linaro.org>
ARM: ux500: Apply a ste-* prefix onto href.dtsi
ARM: ux500: Apply a ste-* prefix onto ccu9540.dts
ARM: ux500: Apply a ste-* prefix onto ccu8540.dts
ARM: ux500: Apply a ste-* prefix onto snowball.dts
ARM: ux500: Remove Snowball DTS entry for ROHM BH1780GLI ambient light sensor
ARM: ux500: Remove Snowball DTS entry for TPS61052 chip
ARM: ux500: Remove Snowball DTS entry for National Semiconductor LP5521 LED chip
ARM: ux500: Remove Toshiba TC35892 I/O Expander's DT entry from Snowball's DTS
ARM: u8540: DT: Set pinctrl mapping to i2c0,1,2,4 & 5
ARM: u8540: Add Pinctrl Device Tree settings for uart0, uart2
ARM: ux500: Stop passing MMC's platform data for Device Tree boots
Documentation: Update binding for Nomadik and DBx5x based platforms
ARM: ux500: Supply external regulator names for Snowball's DT
ARM: ux500: Provide a supply name for the AB8500 AUX regulators to use
...
[ this is a follow-up to this discussion:
http://archive.arm.linux.org.uk/lurker/message/20130730.230827.a1ceb12a.en.html ]
This patchset renames all uses of "bcm," name bindings to
"brcm," as they were done prior to knowing that brcm had
already been standardized as Broadcom vendor prefix
(in Documentation/devicetree/bindings/vendor-prefixes.txt).
This will not cause any churn on devices because none of
these bindings have made it into production yet.
Also rename the the following dt binding docs that had "bcm,"
in their name for consistency:
- bcm,kona-sdhci.txt -> kona-sdhci.txt
- bcm,kona-timer.txt -> kona-timer.txt
Signed-off-by: Christian Daudt <csd@broadcom.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Enable sdio for bcm28155 AP board
Signed-off-by: Christian Daudt <csd@broadcom.com>
Reviewed-by: Alex Elder <elder@linaro.org>
Reviewed-by: Markus Mayer <markus.mayer@linaro.org>
Clean up the sdio numbering to be 1-base as defined in HW spec,
instead of the current 0-base
Signed-off-by: Christian Daudt <csd@broadcom.com>
Reviewed-by: Alex Elder <elder@linaro.org>
The Olimex A20-Olinuxino is an open-hardware board based on the
Allwinner A20 SoC, with most of the pins exported on headers, a 10/100M
ethernet port, SATA, SD and uSD slots, etc.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The Allwinner A20 SoC is based on 2 Cortex A7, an ARM Mali GPU, and is
built to be pin-compatible with the older Allwinner A10.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Merge tag 'omap-for-v3.12/dra7xx' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc
From Tony Lindgren:
Minimal DRA7xx based SoC core support via Rajendra Nayak <rnayak@ti.com>
* tag 'omap-for-v3.12/dra7xx' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (849 commits)
ARM: DRA7: Add the build support in omap2plus
ARM: DRA7: hwmod: Reuse the soc_ops used for OMAP4/5
ARM: DRA7: id: Add cpu detection support for DRA7xx based SoCs'
ARM: DRA7: Kconfig: Make ARCH_NR_GPIO default to 512
ARM: DRA7: board-generic: Add basic DT support
ARM: DRA7: Resue the clocksource, clockevent support
ARM: DRA7: Reuse io tables and add a new .init_early
ARM: DRA7: Reuse all of PRCM and MPUSS SMP infra
Linux 3.11-rc5
btrfs: don't loop on large offsets in readdir
Btrfs: check to see if root_list is empty before adding it to dead roots
Btrfs: release both paths before logging dir/changed extents
Btrfs: allow splitting of hole em's when dropping extent cache
Btrfs: make sure the backref walker catches all refs to our extent
Btrfs: fix backref walking when we hit a compressed extent
Btrfs: do not offset physical if we're compressed
Btrfs: fix extent buffer leak after backref walking
Btrfs: fix a bug of snapshot-aware defrag to make it work on partial extents
btrfs: fix file truncation if FALLOC_FL_KEEP_SIZE is specified
dlm: kill the unnecessary and wrong device_close()->recalc_sigpending()
...
Signed-off-by: Kevin Hilman <khilman@linaro.org>
From Jason Cooper, mvebu fixes-non-critical for v3.12 (round 2):
- fix the memory node (2 by 2) in skeleton64.dtsi
* tag 'fixes-non-3.12-2' of git://git.infradead.org/linux-mvebu:
ARM: dts: Fix memory node in skeleton64.dtsi
This patch adds EHCI and OHCI host device nodes for Exynos4.
Signed-off-by: Dongjin Kim <tobetter@gmail.com>
Acked-by: Jingoo Han <jg1.han@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This adds device-tree bindings for the audio subsystem clock controller
on Exynos 5420.
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/57712
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch corrects the /include to #include on exynos5420
Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The patch adds the MFC clock entry for the 5250 SoC.
Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Removes the unused sclk_mfc from exynos4 dtsi file.
Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
While the Linux driver stack is capable of figuring this out for itself
document the fact that we really do use the internal PHY even with the
directly wired hub on the board to save anyone else having to work this
out for themselves.
Signed-off-by: Mark Brown <broonie@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The Arndale has a SMSC USB3503 connected in hardware only mode like a PHY,
support it using the usb-nop-xceiv binding.
Note that due to a regrettable decision to use a regulator to represent
the reset signal this uses a fixed voltage regulator to do that, there
is a plan to use the reset controller binding once that is merged so it
does not seem worthwhile to fix the usb-nop-xceiv driver at this point.
Signed-off-by: Mark Brown <broonie@linaro.org>
Tested-by: Tushar Behera <tushar.behera@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
OrigenQuad board boots with secure firmware support. Enable support for
reading smc commands.
The binding has been updated as per the documentation provided in
Documentation/devicetree/bindings/arm/samsung-boards.txt.
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Add pin state information for DP HPD support that requires pin configuration
support using pinctrl interface.
Signed-off-by: Vikas Sajjan <vikas.sajjan@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Moves the properties of DP controller to exynos5.dtsi which are common
across exynos5 SoCs like Exynos5250 and Exynos5420.
The PHY DP Node is based on Jingoo Han's <jg1.han@samsung.com> patch
at https://patchwork.linuxtv.org/patch/19189/
Signed-off-by: Vikas Sajjan <vikas.sajjan@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Adds FIMD DT node to exynos5420 based SMDK. Also adds display-timimg
information node.
Signed-off-by: Vikas Sajjan <vikas.sajjan@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Moves the properties of FIMD DT node which are common across Exynos5 based
SoCs like Exynos5250 and Exynos5420 to exynos5.dtsi
Signed-off-by: Vikas Sajjan <vikas.sajjan@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
As the display-timing information is parsed by FIMD driver, it makes
sense to move the display-timing DT node inside FIMD DT node for exynos5250
Signed-off-by: Vikas Sajjan <vikas.sajjan@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This platform from WITS is the evaluation board for the Allwinner A31.
It features a quad-Cortex A7, 2048MB of RAM, NAND, USB, MMC, several
UART, HDMI, a 2048 x 1536 10" screen, powered by a PowerVR, etc.
Of course, most of these peripherals aren't supported yet, but support
for those will come eventually.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The "marvell,armada-370-xp-timer" compatible string, together with
the "marvell,timer-25Mhz" property are deprecated and should be
removed from current DT.
Instead, the timer DT nodes are now required to have an appropriate
compatible string, which should be either "marvell,armada-370-timer"
or "marvell,armada-xp-timer", depending on SoC.
The clock property is now required only for Armada 370 so move it accordingly.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The Device Tree information for the GPIO banks of the Armada 370 and
Armada XP SOCs was incorrectly using #interrupts-cells instead of
controller when using GPIO interrupts, since the GPIO bank DT node
wasn't recognized as a valid interrupt controller by the OF code.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This patch removes quirks from i2s node and change the i2s
compatible names.
Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
After providing spi alias, we can get the following message during probe:
m25p80 spi1.0: sst25vf016b (2048 Kbytes)
,which looks better than the original one:
m25p80 spi32766.0: sst25vf016b (2048 Kbytes)
While at it, keep the alias entries in alphabetical order.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The i.MX23 has a internal Low Resolution ADC; this enables the support
for this device.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The i.MX23 has a internal Low Resolution ADC; this enables the support
for this device.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The i.MX23EVK board provides a USB port so the USB PHY and controller
need to be enabled for it to be usable.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
After mxs-dma driver adopts generic DMA device tree binding, channel
interrupt number is defined in DMA controller node, and channel ID is
listed in "dmas" property. So the DMA channel interrupt number in
client nodes' "interrupts" property and fsl,<module>-dma-channel which
are used by old customized DMA binding can be removed now.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Necessary pins are now grabbed by respective drivers. Unecessary hogpins are
simply removed.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The CFA-10058 is a breakout board for the CFA-10036 that has Ethernet, USB and a
5" LCD screen on it.
Signed-off-by: Brian Lilly <brian@crystalfontz.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The CFA-10056 is a breakout board for the CFA-10036, and is
basically a CFA-10037, with a 4.3" screen.
Signed-off-by: Brian Lilly <brian@crystalfontz.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
- kirkwood
- convert Dockstar, Guruplug, mv88f6281gtw_ge to DT
- remove legacy boards (which have DT support) sheevaplug, lacie boards
- ARRAY_AND_SIZE() cleanup
- dove
- some DT node updates (depends on irqchip/clocksource DT changes earlier)
- add the D2Plug board
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Merge tag 'boards-3.12-2' of git://git.infradead.org/linux-mvebu into next/boards
From Jason Cooper, mvebu boards changes for v3.12:
- kirkwood
- convert Dockstar, Guruplug, mv88f6281gtw_ge to DT
- remove legacy boards (which have DT support) sheevaplug, lacie boards
- ARRAY_AND_SIZE() cleanup
- dove
- some DT node updates (depends on irqchip/clocksource DT changes earlier)
- add the D2Plug board
* tag 'boards-3.12-2' of git://git.infradead.org/linux-mvebu:
ARM: dove: add initial DT file for Globalscale D2Plug
ARM: dove: add GPIO IR receiver node to SolidRun CuBox
ARM: dove: add common pinmux functions to DT
ARM: dove: add cpu device tree node
arch/arm/mach-kirkwood: Avoid using ARRAY_AND_SIZE(e) as a function argument
ARM: kirkwood: fix DT building and update defconfig
ARM: kirkwood: Remove all remaining trace of DNS-320/325 platform code
ARM: kirkwood: use dts pre-processor for mv88f6281gtw-ge
ARM: kirkwood: convert the mv88f6281gtw_ge board to DT
ARM: kirkwood: remove LaCie boards that are supported through DT
ARM: kirkwood: remove support for legacy booting of Sheevaplug
ARM: kirkwood: remove support for legacy booting of Guruplug
ARM: kirkwood: remove support for legacy booting of Dockstar
Signed-off-by: Olof Johansson <olof@lixom.net>
- MBus devicetree bindings
- devbus update for address decoding window, cleanup
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Merge tag 'drivers-3.12' of git://git.infradead.org/linux-mvebu into next/soc
From Jason Cooper:
mvebu drivers changes for v3.12
- MBus devicetree bindings
- devbus update for address decoding window, cleanup
* tag 'drivers-3.12' of git://git.infradead.org/linux-mvebu: (35 commits)
memory: mvebu-devbus: Remove unused variable
ARM: mvebu: Relocate PCIe node in Armada 370 RD board
ARM: mvebu: Fix AXP-WiFi-AP DT for MBUS DT binding
ARM: mvebu: add support for the AXP WiFi AP board
ARM: mvebu: use dts pre-processor for mv78230
PCI: mvebu: Adapt to the new device tree layout
bus: mvebu-mbus: Add devicetree binding
ARM: kirkwood: Relocate PCIe device tree nodes
ARM: kirkwood: Introduce MBUS_ID
ARM: kirkwood: Introduce MBus DT node
ARM: kirkwood: Use the preprocessor on device tree files
ARM: kirkwood: Split DT and legacy MBus initialization
ARM: mvebu: Relocate Armada 370/XP PCIe device tree nodes
ARM: mvebu: Relocate Armada 370/XP DeviceBus device tree nodes
ARM: mvebu: Add BootROM to Armada 370/XP device tree
ARM: mvebu: Add MBus to Armada 370/XP device tree
ARM: mvebu: Use the preprocessor on Armada 370/XP device tree files
ARM: mvebu: Initialize MBus using the DT binding
ARM: mvebu: Remove the harcoded BootROM window allocation
bus: mvebu-mbus: Factorize Armada 370/XP data structures
...
Signed-off-by: Olof Johansson <olof@lixom.net>
- USB host numbering for 9x5 which was preventing from using all ports
- a missing UART (not USART) clock lookup table was preventing from using
them on 9x5
- too large amount of memory was specified for 9n12ek
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Merge tag 'at91-fixes' of git://github.com/at91linux/linux-at91 into fixes
From Nicolas Ferre:
Device tree related fixes:
- USB host numbering for 9x5 which was preventing from using all ports
- a missing UART (not USART) clock lookup table was preventing from using
them on 9x5
- too large amount of memory was specified for 9n12ek
* tag 'at91-fixes' of git://github.com/at91linux/linux-at91:
ARM: at91/DT: fix at91sam9n12ek memory node
ARM: at91: add missing uart clocks DT entries
ARM: at91/DT: at91sam9x5ek: fix USB host property to enable port C
Signed-off-by: Olof Johansson <olof@lixom.net>
Revert "ARM: dts: Change i2s compatible string on exynos5250" (c7f7e6)
and "ARM: dts: exynos5250: move common i2s properties to exynos5 dtsi"
618728) since they reference DMA controller nodes that don't exist
causing DT build issues.
Reported-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Mark Brown <broonie@linaro.org>
This enables the microphone input jack, and hence allows audio to be
captured as well as played back.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
This enables the microphone input jack, and hence allows audio to be
captured as well as played back.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
The patch set beginning with commit:
"ARM: ux500: Apply a ste-* prefix onto snowball.dts"
thru commit:
"ARM: ux500: Remove u9540.dts as it's been replaced"
altered the names of the ux500 device tree files but forgot
to:
- Rename the ccu8540-pinctrl.dtsi file
- Update #include statements from files using these
files, so the build broke.
- Update the Makefile for the device trees so the build
broke.
Fix it up so we can build them all again.
Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
This adds a device tree usable on Mele A1000 (and A2000, as it
apparently is the same device except for the case). This device features
one UART port, Ethernet, an AXP209 PMU on i2c0 and two user configurable
LEDs.
Signed-off-by: Emilio López <emilio@elopez.com.ar>
[maxime: fixed the soc node address]
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Move Renesas ARM based SoCs a little closer to using
multiplatform by adding ARCH_SHMOBILE_MULTI and only
building clocks when COMMON_CLK=n.
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Merge tag 'renesas-multiplatform-for-v3.12' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt
From Simon Horman:
Renesas ARM based SoC multiplatform updates for v3.12
Move Renesas ARM based SoCs a little closer to using
multiplatform by adding ARCH_SHMOBILE_MULTI and only
building clocks when COMMON_CLK=n.
* tag 'renesas-multiplatform-for-v3.12' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: Allow ARCH_SHMOBILE_MULTI timer configuration
ARM: shmobile: Add EMEV2 and KZM9D to ARCH_SHMOBILE_MULTI
ARM: shmobile: Introduce ARCH_SHMOBILE_MULTI
ARM: shmobile: Only build clocks when COMMON_CLK=n
Signed-off-by: Olof Johansson <olof@lixom.net>
SH Mobile pinctrl DT support
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Merge tag 'renesas-pinmux-for-v3.12' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt
From Simon Horman:
Renesas ARM based SoC pinmux updates for v3.12
SH Mobile pinctrl DT support
* tag 'renesas-pinmux-for-v3.12' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: kzm9g-reference: Add LED1-LED4 to the device tree
ARM: shmobile: kzm9g-reference: Move SDHI regulators to DT
ARM: shmobile: kzm9g-reference: Move pinctrl mappings to device tree
ARM: shmobile: marzen-reference: Add LED2-LED4 to the device tree
ARM: shmobile: marzen-reference: Move pinctrl mappings to device tree
ARM: shmobile: armadillo-reference: Add LED1-LED4 to the device tree
ARM: shmobile: armadillo-reference: Move st1232 reset GPIO to DT
ARM: shmobile: armadillo-reference: Add st1232 pin mappings
ARM: shmobile: armadillo-reference: Move pinctrl mappings to device tree
ARM: shmobile: sh73a0: Add pin control device to device tree
ARM: shmobile: sh7372: Add pin control device to device tree
ARM: shmobile: r8a7790: Add GPIO controller devices to device tree
ARM: shmobile: r8a7790: Add pin control device to device tree
ARM: shmobile: r8a7779: Add GPIO controller devices to device tree
ARM: shmobile: r8a7779: Add pin control device to device tree
ARM: shmobile: r8a7778: Add GPIO controller devices to device tree
ARM: shmobile: r8a7778: Add pin control device to device tree
ARM: shmobile: r8a7740: Add pin control device to device tree
ARM: shmobile: r8a73a4: Add pin control device to device tree
Signed-off-by: Olof Johansson <olof@lixom.net>
Conflicts:
arch/arm/boot/dts/r8a73a4.dtsi
arch/arm/boot/dts/r8a7790.dtsi
The gpio controller node inherited from pxa2xx.dtsi won't work for
pxa3xx SoCs, so let's override it in pxa3xx.dtsi.
Signed-off-by: Daniel Mack <zonque@gmail.com>
Cc: Haojian Zhuang <haojian.zhuang@linaro.org>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Device tree entries for the three EHCI controllers on Tegra114.
Enables the the third controller (USB host) on Dalmore.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Add device tree entries for the 3 USB controllers and PHYs and
enable the third controller on Cardhu and Beaver boards.
Fix VBUS regulator entries on Beaver. The GPIO pins were wrong.
Also, internal pullups need to be enabled on those pins.
Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
This patch removes quirks from i2s node and change the i2s
compatible names.
Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
I2S nodes shares some properties across exynos5 SoCs (exynos5250
and exyno5420). Common code is moved to exynos5.dtsi which is
included in exyno5250 and exynos5420 SoC files.
Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
This adds an initial DT file for the Globalscale D2Plug with Dove SoC.
Currently, one LED is missing and I have not been able to get SD8787 driver
working. Those will be taken care of later.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This adds a node for the IR receiver connected to a GPIO pin on the
SolidRun CuBox.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This adds common dedicated and gpio pinmux functions to SoC pinctrl
node. It also relocates pinctrl references to corresponding DT nodes.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This adds a node for the Marvell Sheeva PJ4A CPU found on Dove SoCs.
While at it, also move the l2-cache node out of internal registers and
consistently name different nodes.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Conflicts:
arch/arm/boot/dts/dove.dtsi
Instead of evenly splitting the 512 MiB area between prefetchable and
non-prefetchable memory spaces, increase the prefetchable memory space
to 384 MiB while at the same time decreasing the non-prefetchable memory
space to 128 MiB. This is a more useful default as most PCIe devices
require more prefetchable than non-prefetchable memory.
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Beaver's PCIe lane configuration most closely matches x2 x2 x2 rather
than x4 x1 x1, since clocks 0 and 2 are used, and lanes 0 and 5 are used,
and the only way those align is with a x2 x2 x2 configuration.
Also, disable root port 1; there's nothing connected to it. Root port 0
is the on-board PCIe Ethernet, and port 2 is the mini-PCIe slot.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
PCIe lane 0 is connected to an onboard Gigabit Ethernet (RTL8168evl) and
lane 4 is routed to the board's miniPCIe slot.
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Root port 2 is routed to the bottom connector on Cardhu and is used by
the development dock to provide gigabit ethernet and USB functionality.
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Add the top-level pcie-controller node for the Tegra30 SoC. Tegra30 has
three root ports that can use different lane layouts.
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
With the device tree support in place, probe the PCIe controller from
the device tree and remove the corresponding workaround in the board
file.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
With the device tree support in place, probe the PCIe controller from
the device tree and remove the corresponding workaround in the board
file.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Enable the first PCIe root port which is connected to an FPGA on the
Tamonten Evaluation Carrier and add device nodes for each of the PCI
endpoints available in the standard configuration.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Add properties common to all Tamonten-derived boards to the Tamonten
DTSI and add the fixed 1.05 V regulator.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Add the top-level pcie-controller node for the Tegra20 SoC. Tegra20 has
two root ports that can use different lane layouts.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
[swarren: split DT changes into a separate patch from the main driver]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Enabling the LP1 suspend mode for Tegra devices.
Tested-by: Marc Dietrich <marvin24@gmx.de> # paz00 board
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Exynos PCIe IP consists of Synopsys specific part and Exynos
specific part. Only core block is a Synopsys Designware part;
other parts are Exynos specific.
Also, the Synopsys Designware part can be shared with other
platforms; thus, it can be split two parts such as Synopsys
Designware part and Exynos specific part.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Pratyush Anand <pratyush.anand@st.com>
Cc: Mohit KUMAR <Mohit.KUMAR@st.com>
Enable the HDMI output as well as DDC and hotplug detection on Beaver.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
There was a typo in the base address used for the soc node in the A13
device tree. Fix it with the proper base address.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The reg property of the simple-bus driver is completely useless. Remove
it from the DTSI.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
There was a typo in the base address used for the soc node in the A10s
device tree. Fix it with the proper base address.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The reg property of the simple-bus driver is completely useless. Remove
it from the DTSI.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
There was a typo in the base address used for the soc node in the A10
device tree. Fix it with the proper base address.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The reg property of the simple-bus driver is completely useless. Remove
it from the DTSI.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This driver is currently used by musb' cppi41 couter part. I may merge
both dma engine user of musb at some point but not just yet.
The driver seems to work in RX/TX mode in host mode, tested on mass
storage. I increaed the size of the TX / RX transfers and waited for the
core code to cancel a transfers and it seems to recover.
v2..3:
- use mall transfers on RX side and check data toggle.
- use rndis mode on tx side so we haveon interrupt for 4096 transfers.
- remove custom "transferred" hack and use dmaengine_tx_status() to
compute the total amount of data that has been transferred.
- cancel transfers and reclaim descriptors
v1..v2:
- RX path added
- dma mode 0 & 1 is working
- device tree nodes re-created.
Cc: Vinod Koul <vinod.koul@intel.com>
Cc: Dan Williams <djbw@fb.com>
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Felipe Balbi <balbi@ti.com>
This moves the two instances from the big node into two child nodes. The
glue layer ontop does almost nothing.
There is one devices containing the control module for USB (2) phy,
(2) usb and later the dma engine. The usb device is the "glue device"
which contains the musb device as a child. This is what we do ever since.
The new file musb_am335x is just here to prob the new bus and populate
child devices.
There are a lot of changes to the dsps file as a result of the changes:
- musb_core_offset
This is gone. The device tree provides memory ressources information
for the device there is no need to "fix" things
- instances
This is gone as well. If we have two instances then we have have two
child enabled nodes in the device tree. For instance the SoC in beagle
bone has two USB instances but only one has been wired up so there is
no need to load and init the second instance since it won't be used.
- dsps_glue is now per glue device
In the past there was one of this structs but with an array of two and
each instance accessed its variable depending on the platform device
id.
- no unneeded copy of structs
I do not know why struct dsps_musb_wrapper is copied but it is not
necessary. The same goes for musb_hdrc_platform_data which allocated
on demand and then again by platform_device_add_data(). One copy is
enough.
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Felipe Balbi <balbi@ti.com>
The pcie-controller node needs to be relocated according the MBus
DT binding, since it's now a child of the mbus-compatible node.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
There are a number of variants of the ZyXEL NSA310, with slightly
different LEDs, buttons and i2c devices. Add a DTS file to support one
more of these variants.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Tibor Hársszegi <tibor@harsszegi.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The ranges property needs to be changed to use the new MBus DT binding.
Also, the pcie-controller node needs to be relocated as according the MBus
DT binding, it's now a child of the mbus-compatible node.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The AXP WiFi AP board is a Marvell platform based on the Armada XP
MV78230 SoC. It has two mini-PCIe connectors, one USB 3.0 port powered
by a USB 3.0 controller on PCIe, two Ethernet ports, 1 GB of RAM, 1 GB
of NAND, 16 MB of SPI flash, one SATA port and one button, two UARTs
Successfully tested: USB 3.0 port, the mini-PCIe connectors, SPI
flash, Ethernet ports, SATA port, button, UART.
Untested: NAND flash, due to lack of mainline support for the Armada
370/XP NAND controller for now.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Seif Mazareeb <seif@marvell.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Update the reg property of the memory node in
skeleton64.dtsi to reflect the fact that the root node uses
address-cells=2 and size-cells=2.
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
SCC (Serial Configuration Controller) is used to set initial
conditions for the test chip (TC2). Its registers are also mapped
in normal address space and used to obtain runtime information
and for power management.
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
This must have been a merge error. There was a patch which renamed the
u9540.dts to ccu9540.dts, however the u9540.dts was reincarnate with
the same patches which created it in the first place. Let's kill it
once and for all.
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
It doesn't exist on the Snowball development board.
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
TPS61052 is a; boost converter, LED driver, LED flash driver and
simple GPIO pin chip. It has no use here however, as it is not
found on the Snowball development board.
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
It doesn't exist on the Snowball development board.
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
It doesn't exist on this development board.
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
Instead of using bit-banged I2C, let's use the actual I2C
driver in the kernel. Since the I2C block may be communicating
with things like the PMIC, we need to select it from the Kconfig
just like the bit-banged adapter is selected today. The rest of
the configuration for this driver can be done from the device
tree.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This patch adds the device tree bindings for the bcm281xx reboot code.
Signed-off-by: Markus Mayer <markus.mayer@linaro.org>
Reviewed-by: Tim Kryger <tim.kryger@linaro.org>
Acked-by: Christian Daudt <csd@broadcom.com>
This patch configures pin map in device tree of i2c0,
1,2,4 & 5 for ccu8540 board.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This patch adds pinctrl device tree settings for uart0 and uart2
for ccu8540 board.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Regulator names are platform independent, so they need to be applied to
the base level platform DTS files *.dts. Here we're supplying the names
for the newly described AB8500 external regulators.
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
AB8500 AUX regulators are supplied by EXT3 on some boards. This supply
phandle lookup will enable the regulator core to search for and locate
the EXT3 supply at registration time.
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The AB8500 has 3 external regulators which are used to control outside
voltage sources. Some of the core AB8500 use these external regulators
as a supply, so they must be obtainable via Device Tree.
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit converts the mv88f6281gtw_ge Kirkwood board to use a
Device Tree representation, except for the Ethernet devices and the
DSA switch. Even though the mv643xx_eth driver has a DT binding,
converting this board to use it is for now left on the side because it
doesn't use a simple PHY, but a DSA switch instead.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Add MAX8998 LDO12 and fixed voltage regulator nodes. While at it,
all fixed voltage regulator nodes are grouped in a 'regulators' node.
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Add pinctrl nodes for the camera parallel port CAM_A data bus
and the CAM_A_CLKOUT clock output pin.
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Enable FIMC devices on the Trats board. This allows using the
device in memory-to-memory mode only. The camera port pinctrl
property is now empty and will be updated while support for the
camera sensors is added.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Add common camera node and detailed properties for
the Exynos4210 FIMC devices.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch add dts entries required for the SPI bus used for
firware upload by the S5C73M3 camera.
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Now that mbus has been added to the device tree, it's possible to
move the PCIe nodes out of the ocp node, placing it directly
below the mbus. This is a more accurate representation of the hardware.
Moving the PCIe nodes, we now need to introduce an extra cell to
encode the window target ID and attribute. Since this depends on
the PCIe port, we split the ranges translation entries, to
correspond to each MBus window.
In addition, we encode the PCIe memory and I/O apertures in the MBus
node, according to the MBus DT binding specification. The choice made
is 0xe0000000-0xf0000000 for memory space, and 0xf200000-0xf2100000 for
I/O space. These apertures can be changed in each per-board DT file.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This macro is used to define window's target ID and attribute cells
for the MBus ranges entries.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Add a minimal MBus node, just to allow the MBus driver to probe.
Follow-up patches will migrate the rest of the nodes appropriately.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Now that mbus has been added to the device tree, it's possible to
move the PCIe nodes out of internal registers, placing it directly
below the mbus. This is a more accurate representation of the
hardware.
Moving the PCIe nodes, we now need to introduce an extra cell to
encode the window target ID and attribute. Since this depends on
the PCIe port, we split the ranges translation entries, to correspond
to each MBus window.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Now that mbus has been added to the device tree, it's possible to
move the DeviceBus out of internal registers, placing it directly
below the mbus. This is a more accurate representation of the hardware.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
In order to access the SoC BootROM, we need to declare a mapping
(through a ranges property). The mbus driver will use this property
to allocate a suitable address decoding window.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The Armada 370/XP SoC family has a completely configurable address
space handled by the MBus controller.
This patch introduces the device tree layout of MBus, making the
'soc' node as mbus-compatible.
Since every peripheral/controller is a child of this 'soc' node,
this makes all of them sit behind the mbus, thus describing the
hardware accurately.
A translation entry has been added for the internal-regs mapping.
This can't be done in the common armada-370-xp.dtsi because A370
and AXP have different addressing width.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
NFS detail settings like "nfsroot=,rsize=4096,wsize=4096" are no longer needed
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
NFS detail settings like "nfsroot=,rsize=4096,wsize=4096" are no longer needed
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Now that Ether support has been added to the lager board
it is possible to use nfsroot. This configuration is
in line with that of other shmobile boards.
Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
... for the sake of consistency and assumed convention.
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Acked-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch enables the front camera using the internal
camera ISP (FIMC-IS).
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds AK8975 magnetometer node and corresponding
i2c-gpio bus node for TRATS2 board.
Signed-off-by: Jacek Anaszewski <j.anaszewski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Add common camera node and Exynos4212/4412 specific nodes for
FIMC, MIPI-CSIS, FIMC-LITE and FIMC-IS devices.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds common Exynos4 SoC series FIMC and MIPI CSIS
device nodes.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The Exynos4 SPI controller has migrated to the generic DMA bindings
since commit b5be04d35dbb("spi: s3c64xx: Modify SPI driver to use
generic DMA DT support"). Use the generic bindings to specify the
corresponding DMA to make the SPI usable again on Exynos4x12 SoCs.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The ISP power domain is a common power domain for FIMC-LITE
and FIMC-IS (camera ISP) devices.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Add pinctrl nodes for the ISP I2C0, ISP I2C1 and ISP UART devices.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Add separate nodes for the CAMCLK pin and turn off pull-up on camera
ports A, B. The video bus pins and the clock output (CAMCLK) pin need
separate nodes since full camera port is not used in some configurations,
e.g. for MIPI CSI-2 bus only CAMCLK is required and data/clock signal
use separate dedicated pins.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
All hardware parts of the (Armada 370 based) NETGEAR ReadyNAS 102 are
supported by mainline kernel (USB 3.0 rear ports, USB 2.0 front port,
Gigabit controller and PHY, serial port, leds, buttons, SATA ports,
G762 fan controller) except for:
- the Intersil ISL12057 I2C RTC Chip,
- the Armada NAND controller.
Support for both of those is currently work in progress and does not
prevent boot.
Signed-off-by: Arnaud Ebalard <arno@natisbad.org>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Alexander Shiyan