Commit Graph

6 Commits

Author SHA1 Message Date
Geert Uytterhoeven 83fab8ea62 clk: renesas: r8a7745: Fix LB clock divider
The CLK_TYPE_GEN2_LB clock type is meant for SoCs like R-Car H2, where
the LB clock divider depends on the value of the MD18 pin.

On RZ/G1E, the LB clock divider is fixed to 24.  Hence model the clock
as a fixed factor clock instead.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
2018-04-16 13:39:45 +02:00
Fabrizio Castro e0c0a2c4a2 clk: renesas: r8a7745: Add rwdt clock
Add "rwdt" clock to r8a7745_mod_clks. Also, since we may need to access
the watchdog registers at any time, declare the clock as critical.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-02-20 13:35:13 +01:00
Fabrizio Castro 9dc0ddee8d clk: renesas: cpg-mssr: Add du1 clock to R8A7745
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-10-20 11:00:02 +02:00
Geert Uytterhoeven 5ed793b3b2 clk: renesas: r8a7745: Remove PLL configs for MD19=0
According to tables 7.5b and 7.6b of the RZ/G Series Hardware User's
Manual Rev.1.00, MD19=0 is a prohibited setting.

Hence stop looking at MD19, and remove all PLL configurations for
MD19=0.

Fixes: 9127d54bb8 ("clk: renesas: cpg-mssr: Add R8A7745 support")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-15 09:46:31 +02:00
Geert Uytterhoeven b93e7eb5ed clk: renesas: r8a7745: Remove nonexisting scu-src[0789] clocks
RZ/G1E does not have the SCU-SRC[0789] modules and module clocks.

Fixes: 9127d54bb8 ("clk: renesas: cpg-mssr: Add R8A7745 support")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-15 09:46:31 +02:00
Sergei Shtylyov 9127d54bb8 clk: renesas: cpg-mssr: Add R8A7745 support
Add RZ/G1E (R8A7745) Clock Pulse Generator / Module Standby and Software
Reset support, using the CPG/MSSR driver core and the common R-Car Gen2
(and RZ/G) code.

Based on the proof-of-concept R8A7791 CPG/MSSR patch by Geert
Uytterhoeven <geert+renesas@glider.be>.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-11-10 15:29:30 +01:00