Commit Graph

4238 Commits

Author SHA1 Message Date
Krzysztof Kozlowski 5bb4053b59 clk: samsung: audss: Fix silent hang on Exynos4412 due to disabled EPLL
Similarly to commit f1e9203e23 ("clk: samsung: Fix Exynos 5420 pinctrl
setup and clock disable failure due to domain being gated") for
Exynos5420, the Exynos4412 also requires that EPLL is not disabled.
Otherwise any access to MAUDIO block will silently halt.

This was not visible before because EPLL on Exynos4 could not be
disabled before commit 6edfa11cb3 ("clk: samsung:
Add enable/disable operation for PLL36XX clocks").  After this commit,
on Odroid U3 board one can see silent hang, usually with last (but
unrelated) messages:

	[    2.382741] input: gpio_keys as /devices/platform/gpio_keys/input/input0
	[    2.405686] usb 1-3: new high-speed USB device number 3 using exynos-ehci
	[    2.419843] max77686-rtc max77686-rtc: setting system clock to 2017-06-21 17:04:13 UTC (1498064653)

Mark Exynos4 variant as also needed EPLL to be enabled all the time.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-22 14:55:35 -07:00
Masahiro Yamada 72d0d8672c clk: uniphier: provide NAND controller clock rate
This allows the NAND driver to get the clock rate via clk_get_rate().

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-21 10:47:27 -07:00
Jiancheng Xue 0d84659619 clk: hisilicon: add usb2 clocks for hi3798cv200 SoC
Add usb2 clocks for hi3798cv200 SoC.

Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-21 10:46:45 -07:00
Linus Walleij 846423f967 clk: Add Gemini SoC clock controller
The Cortina Systems Gemini (SL3516/CS3516) has an on-chip clock
controller that derive all clocks from a single crystal, using some
documented and some undocumented PLLs, half dividers, counters and
gates. This is a best attempt to construct a clock driver for the
clocks so at least we can gate off unused hardware and driver the
PCI bus clock.

Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
[sboyd@codeaurora.org: Fix devm_ioremap_resource() return value
checking]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-21 10:45:54 -07:00
Stephen Boyd e293915a6e clk: iproc: Remove __init marking on iproc_pll_clk_setup()
Now that this function is called from driver probe routines, it
needs to drop the __init marking because it isn't just called
from init code.

Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
Cc: Sandeep Tripathy <sandeep.tripathy@broadcom.com>
Cc: Anup Patel <anup.patel@broadcom.com>
Cc: Ray Jui <ray.jui@broadcom.com>
Cc: Scott Branden <scott.branden@broadcom.com>
Fixes: 654cdd3229 ("clk: bcm: Add clocks for Stingray SOC")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-21 09:12:57 -07:00
Sandeep Tripathy 654cdd3229 clk: bcm: Add clocks for Stingray SOC
This patch adds support for Stingray clocks in iproc
ccf. The Stingray SOC has various plls based on iproc
pll architecture.

Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com>
Signed-off-by: Anup Patel <anup.patel@broadcom.com>
Reviewed-by: Ray Jui <ray.jui@broadcom.com>
Reviewed-by: Scott Branden <scott.branden@broadcom.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-19 19:02:45 -07:00
Sean Wang 567bf2ed86 clk: mediatek: export cpu multiplexer clock for MT8173 SoCs
The patch enables CPU multiplexer clock on MT8173 SoC which fixes up
cpufreq driver fails at acquiring intermediate clock source when driver
probe is called.

Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-19 19:02:44 -07:00
Sean Wang 43ed50ee5a clk: mediatek: export cpu multiplexer clock for MT2701/MT7623 SoCs
The patch enables CPU multiplexer clock on MT2701/MT7623 SoC which fixes
up cpufreq driver fails at acquiring intermediate clock source when driver
probe is called.

Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-19 19:02:44 -07:00
Sean Wang 1e17de9049 clk: mediatek: add missing cpu mux causing Mediatek cpufreq can't work
This patch adds CPU multiplexer clocks which are essential for Mediatek
cpufreq driver. It would use the CPU clock multiplexer to switch to the
intermediate clock source temporarily and then wait for the primary clock
changing getting stable.

Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-19 19:02:43 -07:00
Geert Uytterhoeven 34deaff763 clk: renesas: cpg-mssr: Use of_device_get_match_data() helper
If CONFIG_OF=n:

    drivers/clk/renesas/renesas-cpg-mssr.c: In function ‘cpg_mssr_probe’:
    drivers/clk/renesas/renesas-cpg-mssr.c:702: warning: dereferencing ‘void *’ pointer
    drivers/clk/renesas/renesas-cpg-mssr.c:702: error: request for member ‘data’ in something not a structure or union

To fix this, use the of_device_get_match_data() helper, for which a
dummy version is provided if CONFIG_OF=n.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-19 19:02:43 -07:00
Zhangfei Gao 3ff77275f7 clk: hi6220: add acpu clock
Add acpu clock, including sft clock controlling hi6220 coresight module

Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: Li Pengcheng <lipengcheng8@huawei.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-19 19:02:42 -07:00
Shawn Guo 6454504c80 clk: zx296718: export I2S mux clocks
Export I2S mux clocks, so that device tree can refer to them for setting
a better parent clock for I2S work clock.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-19 19:02:42 -07:00
Stefan Agner 22039d150f clk: imx7d: create clocks behind rawnand clock gate
The rawnand clock gate gates two clocks, NAND_USDHC_BUS_CLK_ROOT
and NAND_CLK_ROOT. However, the gate has been in the chain of the
latter only. This does not allow to use the NAND_USDHC_BUS_CLK_ROOT
only, e.g. as required by APBH-Bridge-DMA.

Add new clocks which represent the clock after the gate, and use a
shared clock gate to correctly model the hardware.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Han Xu <han.xu@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-19 19:02:41 -07:00
Zhong Kaihua 2a8e44dffb clk: hi3660: Set PPLL2 to 2880M
Set PPLL2 to 2880M. With this patch, we saw better compatibility
on various 1080p HDMI monitors.

Signed-off-by: Zhong Kaihua <zhongkaihua@huawei.com>
Signed-off-by: Zheng Shaobo <zhengshaobo1@huawei.com>
Acked-by: Zhangfei Gao <zhangfei.gao@linaro.org>
[sboyd@codeaurora.org: Add UL to long number to silence C90
warning]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-19 19:02:41 -07:00
Chen Jun 9357c150e6 clk: hi3660: add clocks for video encoder, decoder and ISP
This patch adds more clocks for hi3660, including:
 - video encoder and decoder
 - ISP (Image Signal Processing)

Signed-off-by: Chen Jun <chenjun14@huawei.com>
Signed-off-by: Zhong Kaihua <zhongkaihua@huawei.com>
Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
Reviewed-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Acked-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-19 18:00:34 -07:00
Chen Jun 73908acb1e clk: hi3660: fix wrong parent name of clk_mux_sysbus
Parent name of clk_mux_sysbus is not correct. This patch fixes it.

Signed-off-by: Chen Jun <chenjun14@huawei.com>
Signed-off-by: John Stultz <john.stultz@linaro.org>
Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
Acked-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-19 18:00:20 -07:00
Srinivas Kandagatla a94fafb7be clk: gcc-msm8916: add support to 9.6MHz codec clk
MCLK for internal audio codec is expected to be at 9.6MHz by default.
This patch adds support to 9.6MHz to make the default case possible.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-19 17:43:49 -07:00
Abhishek Sahu 371a950745 clk: qcom: Add ipq8074 Global Clock Controller support
This patch adds support for the global clock controller found on
the ipq8074 based devices. This includes UART, I2C, SPI etc.

Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-19 17:29:41 -07:00
Stephen Boyd 4a5aa06960 clk: mvebu: cp110: Minor cleanups
Mark an array of strings static const and remove the dereference
of a function pointer when assigning to the platform driver probe
struct member.

drivers/clk/mvebu/cp110-system-controller.c:89:12:
warning: symbol 'gate_base_names' was not declared. Should it be static?
drivers/clk/mvebu/cp110-system-controller.c:447:18:
error: cannot dereference this type

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-19 17:14:11 -07:00
Stephen Boyd 4d4f9a6a19 Merge branch 'clk-cp110' of git://git.infradead.org/linux-mvebu into clk-next
Pull improved Marvel Armada 7K/8K cp110 clk support from Gregory CLEMENT:

We got more information about the clock controllers and the clock tree
of the CP110 part that we find in the Marvell Armada 7K/8K SoCs. The
clk driver is modified accordingly from this new information.

* 'clk-cp110' of git://git.infradead.org/linux-mvebu:
  clk: mvebu: cp110: add sdio clock to cp-110 system controller
  clk: mvebu: cp110: introduce a new binding
  clk: mvebu: cp110: do not depend anymore of the *-clock-output-names
  clk: mvebu: cp110: make failure labels more meaningful
2017-06-19 17:06:46 -07:00
Dinh Nguyen b7f8101d6e clk: socfpga: Fix the smplsel on Arria10 and Stratix10
The smplsel bits for the SDMMC clock on Arria10 and Stratix10 platforms are
offset by 1 additional bit.

Add a new macro SYSMGR_SDMMC_CTRL_SET_AS10 for usage on the Arria10 and
Stratix10 platforms.

Fixes: 5611a5ba8e ("clk: socfpga: update clk.h so for Arria10 platform to use")
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-19 17:01:55 -07:00
Leo Yan a925810f6e clk: Hi3660: register fixed_rate_clks with CLK_OF_DECLARE_DRIVER
The timer will register into system at very early phase at kernel boot;
if timer needs to use clock, the clock should be get ready in function
of_clk_init() so later the timer driver probe can retrieve clock
successfully. This is finished in below flow on arm64:

  start_kernel()
    `-> time_init()
          `-> of_clk_init(NULL)    => register timer's clock
          `-> clocksource_probe()  => register timer

On Hi3660 the sp804 timer uses clock "osc32k", this clock is registered
as platform driver rather than CLK_OF_DECLARE_DRIVER method. As result,
sp804 timer probe returns failure due if cannot bind clock properly.

To fix the failure, this patch is to split crgctrl clocks into two
subsets. One part is for fixed_rate_clks which includes pre-defined
fixed rate clocks, and "osc32k" clock is in this category; So we change
their registration to CLK_OF_DECLARE_DRIVER method, as result the clocks
can be registered ahead with function of_clk_init() and timer driver can
bind timer clock successfully; the rest of the crgctrl clocks are still
registered by the probe of the platform driver.

This patch also adds checking for all crgctrl clocks registration and
print out log if any clock has failure.

Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-19 16:36:48 -07:00
Konstantin Porotchkin a45af6d3a9 clk: mvebu: cp110: add sdio clock to cp-110 system controller
This commit updates the CP110 system controller driver to add the
definition for a missing clock.

The SDIO clock is dedicated driving the SDHCI interface and its frequency
is 400MHz (2/5 of PLL source clock).

The SDIO interface should be bound to this clock and not the core clock
as in the older code.
Using the wrong clock lead to a maximum SDHCI frequency of 250 Mhz, while
the HW really supports up to 400 Mhz.

This patch also fixes the NAND clock relationship documentation.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
[gregory.clement@free-electrons.com:
- use sdio instead of emmc to name the clock]
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-06-19 17:22:23 +02:00
Gregory CLEMENT 5ffeb5f5a7 clk: mvebu: cp110: introduce a new binding
The initial intent when the binding of the cp110 system controller was to
have one flat node. The idea being that what is currently a clock-only
driver in drivers would become a MFD driver, exposing the clock, GPIO and
pinctrl functionality. However, after taking a step back, this would lead
to a messy binding. Indeed, a single node would be a GPIO controller,
clock controller, pinmux controller, and more.

This patch adopts a more classical solution of a top-level syscon node
with sub-nodes for the individual devices. The main benefit will be to
have each functional block associated to its own sub-node where we can
put its own properties.

The introduction of the Armada 7K/8K is still in the early stage so the
plan is to remove the old binding. However, we don't want to break the
device tree compatibility for the few devices already in the field. For
this we still keep the support of the legacy compatible string with a big
warning in the kernel about updating the device tree.

Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-06-19 17:22:22 +02:00
Gregory CLEMENT f5667274ba clk: mvebu: cp110: do not depend anymore of the *-clock-output-names
Using the *-clock-output-names property was a convenient way to have a
unique name for each clock even when there are multiple cp110 blocks
as we can find on Armada 8K.

However it has some drawbacks: the main one being a stronger link than
necessary between the driver and the device tree. For example the clock
name can't be changed, removed or moved. It is still the early stage of
introduction of the Armada 7K/8K and the hardware is still not totally
documented, especially for the clock part. By removing the use of
*-clock-output-names it will be easier to add new clocks without breaking
the compatibility.

The name of each clock is now created by using its physical address as a
prefix (as it was done for the platform device names). Thanks to this we
have an automatic way to compute a unique name.

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-06-19 17:22:21 +02:00
Stephen Boyd 4dea04c1f1 * Expose more clock gate on meson8 (SAR ADC, RNG, USB, SDIO, ETH)
* Add new compatible to the meson8 clock controller for meson8b
 * Add missing parents to gxbb clk81
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Merge tag 'meson-clk-for-4.13-2' of git://github.com/BayLibre/clk-meson into clk-next

Pull Amlogic clk driver updates from Jerome Brunet:

 * Expose more clock gate on meson8 (SAR ADC, RNG, USB, SDIO, ETH)
 * Add new compatible to the meson8 clock controller for meson8b
 * Add missing parents to gxbb clk81

* tag 'meson-clk-for-4.13-2' of git://github.com/BayLibre/clk-meson:
  clk: meson: gxbb: add all clk81 parents
  clk: meson: meson8b: add compatibles for Meson8 and Meson8m2
  clk: meson8b: export the ethernet gate clock
  clk: meson8b: export the USB clocks
  clk: meson8b: export the gate clock for the HW random number generator
  clk: meson8b: export the SDIO clock
  clk: meson8b: export the SAR ADC clocks
2017-06-16 15:01:46 -07:00
Stephen Boyd ef748cb39d Merge branch 'for-4.13-ti-clkctrl' of https://github.com/t-kristo/linux-pm into clk-next
* 'for-4.13-ti-clkctrl' of https://github.com/t-kristo/linux-pm:
  clk: ti: omap4: add clkctrl clock data
  dt-bindings: clk: add omap4 clkctrl definitions
  clk: ti: add support for clkctrl clocks
  Documentation: dt-bindings: Add binding documentation for TI clkctrl clocks
2017-06-16 14:52:02 -07:00
Stephen Boyd 4dc6e1a356 clk: sunxi-ng: Staticize ccu_mux_helper_unapply_prediv()
It isn't used outside of this file right now.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-16 14:51:36 -07:00
Stephen Boyd 8a02fcf8a0 Allwinner clock patches for 4.13
Some new clock units are supported, for the display clocks unsed in the
 newer SoCs, and the A83T PRCM.
 
 There is also a bunch of minor fixes for clocks that are not used by
 anyone, and reworks needed by drivers that will land in 4.13.
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Merge tag 'sunxi-clk-for-4.13' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-next

Pull Allwinner clock patches from Maxime Ripard:

Some new clock units are supported, for the display clocks unsed in the
newer SoCs, and the A83T PRCM.

There is also a bunch of minor fixes for clocks that are not used by
anyone, and reworks needed by drivers that will land in 4.13.

* tag 'sunxi-clk-for-4.13' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: (21 commits)
  clk: sunxi-ng: Move all clock types to a library
  clk: sunxi-ng: a83t: Add support for A83T's PRCM
  dt-bindings: clock: sunxi-ccu: Add compatible string for A83T PRCM
  clk: sunxi-ng: select SUNXI_CCU_MULT for sun8i-a83t
  clk: sunxi-ng: a83t: Fix audio PLL divider offset
  clk: sunxi-ng: a83t: Fix PLL lock status register offset
  clk: sunxi-ng: Add driver for A83T CCU
  clk: sunxi-ng: Support multiple variable pre-dividers
  dt-bindings: clock: sunxi-ccu: Add compatible string for A83T CCU
  clk: sunxi-ng: de2: fix wrong pointer passed to PTR_ERR()
  clk: sunxi-ng: sun5i: Export video PLLs
  clk: sunxi-ng: mux: Re-adjust parent rate
  clk: sunxi-ng: mux: Change pre-divider application function prototype
  clk: sunxi-ng: mux: split out the pre-divider computation code
  clk: sunxi-ng: mux: Don't just rely on the parent for CLK_SET_RATE_PARENT
  clk: sunxi-ng: div: Switch to divider_round_rate
  clk: sunxi-ng: Pass the parent and a pointer to the clocks round rate
  clk: divider: Make divider_round_rate take the parent clock
  clk: sunxi-ng: explicitly include linux/spinlock.h
  clk: sunxi-ng: add support for DE2 CCU
  ...
2017-06-16 14:45:27 -07:00
Jerome Brunet 215c80a7d6 clk: meson: gxbb: add all clk81 parents
Remove the FIXME on clk81 mux and add all the documented parents

Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2017-06-16 18:51:42 +00:00
Jerome Brunet 46460a6be9 Merge branch 'next/headers' into next/drivers 2017-06-16 18:32:36 +00:00
Tero Kristo 1c881b5a4f clk: ti: omap4: add clkctrl clock data
Add data for omap4 clkctrl clocks, and register it within the clkctrl
driver.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
2017-06-15 10:48:08 +03:00
Tero Kristo 88a172526c clk: ti: add support for clkctrl clocks
Previously, hwmod core has been used for controlling the hwmod level
clocks directly. This has certain drawbacks, like being unable to share
the clocks for multiple users, missing usecounting and generally being
totally incompatible with the common clock framework.

This patch adds support for clkctrl clocks for addressing the above
issues. These support the modulemode handling, which will replace the
direct hwmod clkctrl linkage. Any optional clocks are also supported,
gate, mux and divider.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
2017-06-15 10:47:43 +03:00
Stephen Boyd 9c861f3328 Merge branch 'clk-fixes' into clk-next
* clk-fixes:
  clk: sunxi-ng: a64: Export PLL_PERIPH0 clock for the PRCM
  clk: sunxi-ng: h3: Export PLL_PERIPH0 clock for the PRCM
  dt-bindings: clock: sunxi-ccu: Add pll-periph to PRCM's needed clocks
  clk: sunxi-ng: enable SUNXI_CCU_MP for PRCM
  clk: sunxi-ng: v3s: Fix usb otg device reset bit
  clk: sunxi-ng: a31: Correct lcd1-ch1 clock register offset
2017-06-14 16:48:21 -07:00
Stephen Boyd 949bdfed4b Allwinner clock fixes for 4.12
Some fixes that fix some bindings that went in 4.12, fix a few reset and
 clock offsets and a build error fix
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Merge tag 'sunxi-clk-fixes-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-fixes

Allwinner clock fixes for 4.12

Some fixes that fix some bindings that went in 4.12, fix a few reset and
clock offsets and a build error fix

* tag 'sunxi-clk-fixes-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  clk: sunxi-ng: a64: Export PLL_PERIPH0 clock for the PRCM
  clk: sunxi-ng: h3: Export PLL_PERIPH0 clock for the PRCM
  dt-bindings: clock: sunxi-ccu: Add pll-periph to PRCM's needed clocks
  clk: sunxi-ng: enable SUNXI_CCU_MP for PRCM
  clk: sunxi-ng: v3s: Fix usb otg device reset bit
  clk: sunxi-ng: a31: Correct lcd1-ch1 clock register offset
2017-06-14 16:48:03 -07:00
Stephen Boyd 7f274d54bb clk/samsung updates for 4.13
- conversion to the clk_hw API
  - definitions and fixes of exynos5420 SoC audio subsystem
    related clocks
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Merge tag 'clk-v4.13-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk into clk-next

Pull samsung clk driver updates from Sylwester Nawrocki

 - conversion to the clk_hw API
 - definitions and fixes of exynos5420 SoC audio subsystem
   related clocks

* tag 'clk-v4.13-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk:
  clk: samsung: exynos542x: Add EPLL rate table
  clk: samsung: Add missing exynos5420 audio related clocks
  clk: samsung: Add enable/disable operation for PLL36XX clocks
  clk: samsung: s5pv210-audss: Convert to the new clk_hw API
  clk: samsung: exynos-clkout: Convert to the new clk_hw API
  clk: samsung: exynos-audss: Convert to the new clk_hw API
  clk: samsung: Convert common drivers to the new clk_hw API
  clk: samsung: Add local variable to match its purpose
  clk: samsung: Remove dead code
2017-06-14 10:36:30 -07:00
Stephen Boyd c96da4dd39 One new clock controller for the rk3128 soc, a fixup for the rk3228 cpuclk
table and the usual bunch of some new clock-ids and some clocks marked as
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Merge tag 'v4.13-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next

Pull rockchip clk driver updates from Heiko Stuebner:

One new clock controller for the rk3128 soc, a fixup for the rk3228 cpuclk
table and the usual bunch of some new clock-ids and some clocks marked as
critical.

* tag 'v4.13-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  clk: rockchip: mark some special clk as critical on rk3368
  clk: rockchip: mark noc and some special clk as critical on rk3288
  clk: rockchip: mark noc and some special clk as critical on rk3228
  clk: rockchip: mark pclk_ddrupctl as critical_clock on rk3036
  clk: rockchip: add clock controller for rk3128
  dt-bindings: add bindings for rk3128 clock controller
  clk: rockchip: export more rk3228 clocks ids
  clk: rockchip: add ids for rk3399 testclks used for camera handling
  clk: rockchip: add dt-binding header for rk3128
  clk: rockchip: fix up the RK3228 clk cpu setting table
  clk: rockchip: add clock-ids for more rk3228 clocks
  clk: rockchip: add ids for camera on rk3399
2017-06-14 10:33:04 -07:00
Tero Kristo b745c0794e clk: keystone: Add sci-clk driver support
In K2G, the clock handling is done through firmware executing on a
separate core. Linux kernel needs to communicate to the firmware
through TI system control interface to access any power management
related resources, including clocks.

The keystone sci-clk driver does this, by communicating to the
firmware through the TI SCI driver. The driver adds support for
registering clocks through DT, and basic required clock operations
like prepare/get_rate, etc.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
[sboyd@codeaurora.org: Make ti_sci_init_clocks() static]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-14 09:05:07 -07:00
Martin Blumenstingl 855f06a100 clk: meson: meson8b: add compatibles for Meson8 and Meson8m2
The clock controller on Meson8, Meson8b and Meson8m2 is very similar
based on the code from the Amlogic GPL kernel sources. Add separate
compatibles for each SoC to make sure that we can easily implement
all the small differences for each SoC later on.

In general the Meson8 and Meson8m2 seem to be almost identical as they
even share the same mach-meson8 directory in Amlogic's GPL kernel
sources.
The main clocks on Meson8, Meson8b and Meson8m2 are very similar,
because they are all using the same PLL values, 90% of the clock gates
are the same (the actual diffstat of the mach-meson8/clock.c and
mach-meson8b/clock.c files is around 30 to 40 lines, when excluding
all commented out code).
The difference between the Meson8 and Meson8b clock gates seem to be:
- Meson8 has AIU_PCLK, HDMI_RX, VCLK2_ENCT, VCLK2_ENCL, UART3,
  CSI_DIG_CLKIN gates which don't seem to be available on Meson8b
- the gate on Meson8 for bit 7 seems to be named "_1200XXX" instead
  of "PERIPHS_TOP" (on Meson8b)
- Meson8b has a SANA gate which doesn't seem to exist on Meson8 (or
  on Meson8 the same bit is used by the UART3 gate in Amlogic's GPL
  kernel sources)
None of these gates is added for now, since it's unclear whether these
definitions are actually correct (the VCLK2_ENCT gate for example is
defined, but only used in some commented block).

The main difference between all three SoCs seem to be the video (VPU)
clocks. Apart from different supported clock rates (according to vpu.c
in mach-meson8 and mach-meson8b from Amlogic's GPL kernel sources) the
most notable difference is that Meson8m2 has a GP_PLL clock and a mux
(probably the same as on the Meson GX SoCs) to support glitch-free
(clock rate) switching.
None of these VPU clocks are not supported by our mainline meson8b
clock driver yet though.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2017-06-12 07:33:08 +00:00
Martin Blumenstingl c22f06d3c0 clk: meson8b: export the ethernet gate clock
Export the ethernet gate clock to the dt-bindings.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2017-06-12 07:30:45 +00:00
Martin Blumenstingl 677f6af5d6 clk: meson8b: export the USB clocks
Export the USB related clocks (for the USB controller and the USB2 PHYs)
so they can be used in the dt-bindings.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2017-06-12 07:30:44 +00:00
Martin Blumenstingl 06eff6a792 clk: meson8b: export the gate clock for the HW random number generator
This exports the clock so it can be used in the dt-bindings.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2017-06-12 07:30:43 +00:00
Martin Blumenstingl e2e5f3211f clk: meson8b: export the SDIO clock
Export the SDIO clock so it can be used in the dt-bindings.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2017-06-12 07:30:42 +00:00
Martin Blumenstingl 70ad0d0351 clk: meson8b: export the SAR ADC clocks
Export the clocks for the SAR ADC so they can be used in the
dt-bindings.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2017-06-12 07:30:41 +00:00
Sylwester Nawrocki 9842452acd clk: samsung: exynos542x: Add EPLL rate table
A specific clock rate table is added for EPLL so it is possible
to set frequency of the EPLL output clock as multiple of various
audio sampling rates.

Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2017-06-09 13:12:55 +02:00
Sylwester Nawrocki 8a9cf26e30 clk: samsung: Add missing exynos5420 audio related clocks
This patch adds missing definitions of mux clocks required for using
EPLL as the audio subsystem root clock on exynos5420/exynos5422 SoCs.

Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Tested-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2017-06-09 13:12:54 +02:00
Sylwester Nawrocki 6edfa11cb3 clk: samsung: Add enable/disable operation for PLL36XX clocks
The existing enable/disable ops for PLL35XX are made more generic
and used also for PLL36XX. This fixes issues in the kernel with
PLL36XX PLLs when the PLL has not been already enabled by bootloader.

Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Tested-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2017-06-09 13:12:42 +02:00
Marek Szyprowski ce3bb8f554 clk: samsung: s5pv210-audss: Convert to the new clk_hw API
Clock providers should use the new struct clk_hw based API, so convert
Samsung S5PV210 Audio Subsystem clock provider to the new approach.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
2017-06-09 12:27:49 +02:00
Marek Szyprowski cf1395143f clk: samsung: exynos-clkout: Convert to the new clk_hw API
Clock providers should use the new struct clk_hw based API, so convert
Exynos CLKOUT clock provider to the new approach.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2017-06-09 11:10:47 +02:00
Marek Szyprowski 5b2c3da14c clk: samsung: exynos-audss: Convert to the new clk_hw API
Clock providers should use the new struct clk_hw based API, so convert
Exynos Audio Subsystem clock provider to the new approach.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
2017-06-09 11:10:40 +02:00
Marek Szyprowski ecb1f1f731 clk: samsung: Convert common drivers to the new clk_hw API
Clock providers should use the new struct clk_hw based API, so convert
Samsung clock providers and their helper functions to the new approach.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2017-06-07 22:47:57 +02:00
Marek Szyprowski 7288de7451 clk: samsung: Add local variable to match its purpose
Add new variable to avoid using clk pointer for different purposes across
the exynos_register_cpu_clock() function. This will help in future rewrite
for the new clk_hw API.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2017-06-07 22:47:56 +02:00
Marek Szyprowski 9f57fd6ee4 clk: samsung: Remove dead code
samsung_clk_register_pll2550x() function is not used anymore,
so remove its declaration.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2017-06-07 22:47:55 +02:00
Stephen Boyd 06e226c7fb clk: sunxi-ng: Move all clock types to a library
We've run into kconfig missing dependency errors in the sunxi-ng
code a couple times now. Each time the fix is to find the missing
select statement and add it to the Kconfig entry for a particular
SoC driver. Given that all this code is builtin (non-modular) we
don't need to do this complicated dependency tracking in Kconfig.
Instead we can move all the "library"ish code to be compiled as
lib-y instead of obj-y, let the linker throw away unused code in
the resulting vmlinux, and drop all the Kconfig stuff we use to
track clock types.

Suggested-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
[Maxime: added lib.a to obj-y, added the comment]
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-06-07 15:33:39 +02:00
Chen-Yu Tsai 5a90c14c0b clk: sunxi-ng: a83t: Add support for A83T's PRCM
The A83T's PRCM has the same set of clocks and resets as the A64.
However, a few dividers are different. And due to the lack of a low
speed 32.768 kHz oscillator, a few of the clock parents are different.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-06-07 15:33:06 +02:00
Arnd Bergmann b5e53469f3 clk: sunxi-ng: select SUNXI_CCU_MULT for sun8i-a83t
We get a link error when CCU_MULT is not set with the
newly added driver:

drivers/clk/sunxi-ng/ccu-sun8i-a83t.o:(.data.__compound_literal.1+0x4): undefined reference to `ccu_mult_ops'
drivers/clk/sunxi-ng/ccu-sun8i-a83t.o:(.data.__compound_literal.3+0x4): undefined reference to `ccu_mult_ops'

Fixes: 46b492116666 ("clk: sunxi-ng: Add driver for A83T CCU")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2017-06-07 15:32:16 +02:00
Chen-Yu Tsai f2fe1b640f clk: sunxi-ng: a83t: Fix audio PLL divider offset
The divider of the audio PLL has an offset of 1.
Fix this in the driver.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-06-07 15:32:16 +02:00
Chen-Yu Tsai faea8b0e33 clk: sunxi-ng: a83t: Fix PLL lock status register offset
The offset for the PLL lock status register was incorrectly set to
0x208, which actually points to an unused register. The correct
register offset is 0x20c.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-06-07 15:32:16 +02:00
Chen-Yu Tsai 05359be117 clk: sunxi-ng: Add driver for A83T CCU
The A83T clock control unit is a hybrid of some new style clock designs
from the A80, and old style layout from the other Allwinner SoCs.

Like the A80, the SoC does not have a low speed 32.768 kHz oscillator.
Unlike the A80, there is no clock input either. The only low speed clock
available is the internal oscillator which runs at around 16 MHz,
divided by 512, yielding a low speed clock around 31.250 kHz.

Also, the MMC2 module clock supports switching to a "new timing" mode.
This mode divides the clock output by half, and disables the CCU based
clock delays. The MMC controller must be configure to the same mode,
and then use its internal clock delays.

This driver does not support runtime switching of the timing modes.
Instead, the new timing mode is enforced at probe time. Consumers can
check which mode is active by trying to get the current phase delay
of the MMC2 phase clocks, which will return -ENOTSUPP if the new
timing mode is active.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-06-07 15:32:16 +02:00
Chen-Yu Tsai 13e0dde8b2 clk: sunxi-ng: Support multiple variable pre-dividers
On the A83T, the AHB1 clock has a shared pre-divider on the two
PLL-PERIPH clock parents. To support such instances of shared
pre-dividers, this patch extends the mux clock type to support
multiple variable pre-dividers.

As the pre-dividers are only used to calculate the rate, but
do not participate in the factorization process, this is fairly
straightforward.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-06-07 15:32:15 +02:00
Wei Yongjun 1f6d640cad clk: sunxi-ng: de2: fix wrong pointer passed to PTR_ERR()
PTR_ERR should access the value just tested by IS_ERR, otherwise
the wrong error code will be returned.

Fixes: b0d9a4bd52bd ("clk: sunxi-ng: add support for DE2 CCU")
Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-06-07 15:32:14 +02:00
Maxime Ripard 0adad031ef clk: sunxi-ng: sun5i: Export video PLLs
The video PLLs are used directly by the HDMI controller. Export them so
that we can use them in our DT node.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2017-06-07 15:32:14 +02:00
Maxime Ripard abea24218a clk: sunxi-ng: mux: Re-adjust parent rate
Currently, the parent rate given back to the clock framework in our
request is the original parent rate we calculated before trying to round
the rate of our clock.

This works fine unless our clock also changes its parent rate, in which
case we will simply ignore that change and still use the previous parent
rate.

Create a new function to re-adjust the parent rate to take the pre-dividers
into account, and give that back to the clock framework.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2017-06-07 15:32:14 +02:00
Maxime Ripard d754b15951 clk: sunxi-ng: mux: Change pre-divider application function prototype
The current function name is a bit confusing, and doesn't really allow to
create an explicit function to reverse the operation.

We also for now change the parent rate through a pointer, while we don't
return anything.

In order to be less confusing, and easier to use for downstream users,
change the function name to something hopefully clearer, and return the
adjusted rate instead of changing the pointer.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2017-06-07 15:32:13 +02:00
Maxime Ripard ea8edcded5 clk: sunxi-ng: mux: split out the pre-divider computation code
The pre-divider retrieval code was merged into the function to apply the
current pre-divider onto the parent clock rate so that we can use that
adjusted value to do our factors computation.

However, since we'll need to do the reverse operation, we need to split out
that code into a function that will be shared.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2017-06-07 15:32:13 +02:00
Maxime Ripard 73e3e04fc0 clk: sunxi-ng: mux: Don't just rely on the parent for CLK_SET_RATE_PARENT
The current code only rely on the parent to change its rate in the case
where CLK_SET_RATE_PARENT is set.

However, some clock rates might be obtained only through a modification of
the parent and the clock divider. Just rely on the round rate of the clocks
to give us the best computation that might be achieved for a given rate.

round_rate functions now need to honor CLK_SET_RATE_PARENT, but either the
functions already do that if they modify the parent, or don't modify the
praents at all.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2017-06-07 15:32:13 +02:00
Maxime Ripard e69b2afa87 clk: sunxi-ng: div: Switch to divider_round_rate
divider_round_rate_parent already evaluates changing the parent rate if
CLK_SET_RATE_PARENT is set. Now that we can do that on muxes too, let's
just use it.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2017-06-07 15:32:13 +02:00
Maxime Ripard 10a8d9b906 clk: sunxi-ng: Pass the parent and a pointer to the clocks round rate
The clocks might need to modify their parent clocks. In order to make that
possible, give them access to the parent clock being evaluated, and to a
pointer to the parent rate so that they can modify it if needed.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2017-06-07 15:32:13 +02:00
Maxime Ripard 22833a9165 clk: divider: Make divider_round_rate take the parent clock
So far, divider_round_rate only considers the parent clock returned by
clk_hw_get_parent.

This works fine on clocks that have a single parents, this doesn't work on
muxes, since we will only consider the first parent, while other parents
may totally be able to provide a better combination.

Clocks in that case cannot use divider_round_rate, so would have to come up
with a very similar logic to work around it. Instead of having to do
something like this, and duplicate that logic everywhere, create a
divider_round_rate parent to allow caller to give an additional parameter
for the parent clock to consider.

Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2017-06-07 15:32:12 +02:00
Tobias Klauser b042e42fee clk: sunxi-ng: explicitly include linux/spinlock.h
ccu_reset.h and ccu_reset.c use spinlock_t and associated functions but
rely on implict inclusion of linux/spinlock.h which means that changes
in other headers could break the build. Thus, add an explicit include.

Signed-off-by: Tobias Klauser <tklauser@distanz.ch>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-06-07 15:32:12 +02:00
Icenowy Zheng 763c5bd045 clk: sunxi-ng: add support for DE2 CCU
The "Display Engine 2.0" in Allwinner newer SoCs contains a clock
management unit for its subunits, like the DE CCU in A80.

Add a sunxi-ng style driver for it.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-06-07 15:32:12 +02:00
Fabio Estevam b608a89221 clk: imx7d: Fix the DDR PLL enable bit
Commit ad14972422 ("clk: imx7d: Fix the powerdown bit location
of PLL DDR") used the incorrect bit for the IMX_PLLV3_DDR_IMX7 case.

Fix it accordingly to avoid a kernel hang.

Reported-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-06 17:42:41 -07:00
Alexandre Belloni 4a5f06a01c clk: at91: fix clk-generated compilation
Fix missing }

Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-05 12:56:47 -07:00
Linus Walleij cfe76a28e3 clk: versatile: delete old RealView clock implementation
The old RealView clock implementation is not used anymore
(nothing in the kernel calls realview_clk_init()) as we have
moved all clocks over to device tree. Delete it.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-02 16:27:17 -07:00
Phil Elwell 3542976d85 clk: bcm2835: Minimise clock jitter for PCM clock
Fractional clock dividers generate accurate average frequencies but
with jitter, particularly when the integer divisor is small.

Introduce a new metric of clock accuracy to penalise clocks with a good
average but worse jitter compared to clocks with an average which is no
better but with lower jitter. The metric is the ideal rate minus the
worse deviation from that ideal using the nearest integer divisors.

Use this metric for parent selection for clocks requiring low jitter
(currently just PCM).

Signed-off-by: Phil Elwell <phil@raspberrypi.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Acked-by: Stefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-02 15:42:21 -07:00
Phil Elwell 8c0de581c4 clk: bcm2835: Limit PCM clock to OSC and PLLD_PER
Restrict clock sources for the PCM peripheral to the oscillator and
PLLD_PER because other source may have varying rates or be switched off.
Prevent other sources from being selected by replacing their names in
the list of potential parents with dummy entries (entry index is
significant).

Signed-off-by: Phil Elwell <phil@raspberrypi.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Acked-by: Stefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-02 15:42:19 -07:00
Phil Elwell e45098d703 clk: bcm2835: Correct the prediv logic
If a clock has the prediv flag set, both the integer and fractional
parts must be scaled when calculating the resulting frequency.

Signed-off-by: Phil Elwell <phil@raspberrypi.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-02 15:41:49 -07:00
Stephen Boyd 887541159c Merge branch 'clk-bulk-get' into clk-next
* clk-bulk-get:
  clk: add managed version of clk_bulk_get
  clk: add clk_bulk_get accessories
2017-06-02 15:39:32 -07:00
Dong Aisheng 618aee02e2 clk: add managed version of clk_bulk_get
This patch introduces the managed version of clk_bulk_get.

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: "Rafael J. Wysocki" <rjw@rjwysocki.net>
Cc: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Mark Brown <broonie@kernel.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Anson Huang <anson.huang@nxp.com>
Cc: Robin Gong <yibin.gong@nxp.com>
Cc: Bai Ping <ping.bai@nxp.com>
Cc: Leonard Crestez <leonard.crestez@nxp.com>
Cc: Octavian Purdila <octavian.purdila@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-02 15:37:49 -07:00
Dong Aisheng 266e4e9d91 clk: add clk_bulk_get accessories
These helper function allows drivers to get several clk consumers in
one operation. If any of the clk cannot be acquired then any clks
that were got will be put before returning to the caller.

This can relieve the driver owners' life who needs to handle many clocks,
as well as each clock error reporting.

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: "Rafael J. Wysocki" <rjw@rjwysocki.net>
Cc: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Mark Brown <broonie@kernel.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Anson Huang <anson.huang@nxp.com>
Cc: Robin Gong <yibin.gong@nxp.com>
Cc: Bai Ping <ping.bai@nxp.com>
Cc: Leonard Crestez <leonard.crestez@nxp.com>
Cc: Octavian Purdila <octavian.purdila@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-02 15:37:45 -07:00
Stephen Boyd c3c4cb8d62 clk: meson-gxbb: Add const to some parent name arrays
These can be marked as const * const.

Cc: Neil Armstrong <narmstrong@baylibre.com>
Cc: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-02 10:57:50 -07:00
Stephen Boyd f6b3130919 Amlogic clock driver updates for 4.13
* Expose more i2s and spdif output clocks
 * Expose EE uart and SPICC gate clocks
 * Remove cpu_clk from to gxbb
 * Mark clk81 as critical on gxbb
 * Add CEC EE clocks
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Merge tag 'meson-clk-for-4.13' of git://github.com/BayLibre/clk-meson into clk-next

Pull Amlogic clock driver updates from Jerome Brunet:

 * Expose more i2s and spdif output clocks
 * Expose EE uart and SPICC gate clocks
 * Remove cpu_clk from to gxbb
 * Mark clk81 as critical on gxbb
 * Add CEC EE clocks

* tag 'meson-clk-for-4.13' of git://github.com/BayLibre/clk-meson:
  clk: meson-gxbb: Add EE 32K Clock for CEC
  clk: gxbb: remove CLK_IGNORE_UNUSED from clk81
  clk: meson: meson8b: mark clk81 as critical
  clk: meson: gxbb: remove the "cpu_clk" from the GXBB and GXL driver
  clk: meson-gxbb: un-export the CPU clock
  clk: meson-gxbb: expose UART clocks
  clk: meson-gxbb: expose SPICC gate
  clk: meson-gxbb: expose spdif master clock
  clk: meson-gxbb: expose i2s master clock
  clk: meson-gxbb: expose spdif clock gates
2017-06-02 10:51:41 -07:00
Arvind Yadav 8fedfee49f clk: palmas: undo preparation of a clock source.
Undo preparation of a clock source, if palmas_clks_init_configure is not
successful.

Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-02 10:51:34 -07:00
Elaine Zhang 223c24be74 clk: rockchip: mark some special clk as critical on rk3368
The jtag clk no driver to handle them.
But this clk need enable,so make it as critical.

The ddrphy/ddrupctl clks no driver to handle them,
Chip design requirements for these clock to always on,

The pmu_hclk_otg0 is Chip design defect, must be always on,

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-06-02 15:57:32 +02:00
Elaine Zhang 55bb6a633c clk: rockchip: mark noc and some special clk as critical on rk3288
The atclk/dbg/jtag/hsic-xin12m/pclk_core clks no driver to handle them.
But this clks need enable,so make it as ignore_unused for now.

The ddrupctl0/ddrupctl1/publ0/publ1 clks no driver to handle them,
Chip design requirements for these clock to always on,

The pmu_hclk_otg0 is Chip design defect, must be always on,

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-06-02 15:54:20 +02:00
Elaine Zhang f18c0994cd clk: rockchip: mark noc and some special clk as critical on rk3228
The jtag/bus/peri/initmem/rom/stimer/phy clks no driver to handle them.
But this clks need enable,so make it as critical.

The ddrupctl/ddrmon/ddrphy clks no driver to handle them,
Chip design requirements for these clock to always on,

The hclk_otg_pmu is Chip design defect, must be always on,
The new document will update the description of this clock.

All these non-noc/non-arbi clocks,IC suggest always on,
Because it's have some order limitation, between the NOC clock switch
and bus IDLE(or pd on/off).

The software is not very good to solve this constraint.
Always on these clocks, has no effect on the system power consumption.
The new document will update the description of these clock.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-06-02 15:51:11 +02:00
Elaine Zhang f2893aaba4 clk: rockchip: mark pclk_ddrupctl as critical_clock on rk3036
No driver to handle this clk yet, but chip design requiress for this clock
supplying the ddr controller to be always on.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-06-02 15:42:38 +02:00
Elaine Zhang f6022e88fa clk: rockchip: add clock controller for rk3128
Add the clock tree definition for the new rk3128 SoC.
And it also applies to the RK3126 SoC.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-06-02 14:49:35 +02:00
Elaine Zhang 5d2595627e clk: rockchip: export more rk3228 clocks ids
This patch exports related BUS/VPU/RGA/HDCP/IEP/TSP/WIFI/
VIO/USB/EFUSE/GPU/CRYPTO clocks for dts reference.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-06-02 14:48:40 +02:00
Eddie Cai 25fb42b1cf clk: rockchip: add ids for rk3399 testclks used for camera handling
clk_testout1 and clk_testout2 are used for camera handling, so add their ids.

Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-06-02 14:48:38 +02:00
Michael Turquette 4e19dcd93b clk: renesas: Updates for v4.13
- Add more module clocks for R-Car H3 ES2.0 and M3-W,
   - Add CPG/MSSR drivers for all supported R-Car Gen2 SoCs, enabling support
     for module resets, which are not supported by the existing driver,
   - Rework Kconfig and Makefile logic,
   - Small fixes and cleanups.
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Merge tag 'clk-renesas-for-v4.13-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next

clk: renesas: Updates for v4.13

  - Add more module clocks for R-Car H3 ES2.0 and M3-W,
  - Add CPG/MSSR drivers for all supported R-Car Gen2 SoCs, enabling support
    for module resets, which are not supported by the existing driver,
  - Rework Kconfig and Makefile logic,
  - Small fixes and cleanups.
2017-06-02 14:03:59 +09:00
Gregory CLEMENT 29e6beb5a5 clk: mvebu: cp110: make failure labels more meaningful
In preparation to the addition of a new clock, rename the goto labels
used to handle the failure cases using a name related to the failure
cause. This will allow to insert additional failing cases without
renaming all the labels.

Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-06-01 16:07:35 +02:00
Bryan O'Donoghue ee177c5d63 clk: Fix __set_clk_rates error print-string
When failing to set a clock the printout emitted is incorrect.
"u32 rate" is formatted as %d and should be %u whereas "unsigned long
clk_set_rate()" is formatted as %ld and should be %lu as per
Documentation/printk-formats.txt.

Fixes: 2885c3b2a3 ("clk: Show correct information when fail to set clock rate")
Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-01 02:13:44 -07:00
Sudeep Holla 7374aec956 clk: scpi: fix return type of __scpi_dvfs_round_rate
The frequencies above the maximum value of signed integer(i.e. 2^31 -1)
will overflow with the current code.

This patch fixes the return type of __scpi_dvfs_round_rate from 'int'
to 'unsigned long'.

Fixes: cd52c2a4b5 ("clk: add support for clocks provided by SCP(System Control Processor)")
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-01 02:13:11 -07:00
Scott Wood 80b4ae7ace clk: qoriq: Separate root input clock for core PLLs on ls1012a
ls1012a has separate input root clocks for core PLLs versus the
platform PLL, with the latter described as sysclk in the hw docs.
If a second input clock, named "coreclk", is present, this clock will be
used for the core PLLs.

Signed-off-by: Scott Wood <oss@buserror.net>
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-01 01:24:13 -07:00
Alexandre Belloni 8e56133e5c clk: at91: fix clk-generated parenting
clk_generated_startup is called after clk_hw_register. So the first call to
get_parent will not have the correct value (i.e. 0) and because this is
cached, it may never be updated.

Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Fixes: df70aeef60 ("clk: at91: add generated clock driver")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-01 00:47:50 -07:00
Fabio Estevam ad14972422 clk: imx7d: Fix the powerdown bit location of PLL DDR
According to the MX7D Reference Manual the powerdown bit of
CCM_ANALOG_PLL_DDRn register is bit 20, so fix it accordingly.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-01 00:25:38 -07:00
Ralph Sennhauser 9593f4f56c clk: mvebu: armada-38x: add support for 1866MHz variants
The Linksys WRT3200ACM CPU is clocked at 1866MHz. Add 1866MHz to the
list of supported CPU frequencies. Also update multiplier and divisor
for the l2clk and ddrclk.

Noticed by the following warning:
[    0.000000] Selected CPU frequency (16) unsupported

Signed-off-by: Ralph Sennhauser <ralph.sennhauser@gmail.com>
Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-01 00:25:21 -07:00
Michael Turquette fca63efe6e Merge branch 'clk-ap806' into clk-next 2017-06-01 12:16:35 +09:00
Gregory CLEMENT b90da67543 clk: mvebu: ap806: introduce a new binding
As for cp110, the initial intent when the binding of the ap806 system
controller was to have one flat node. The idea being that what is
currently a clock-only driver in drivers would become a MFD driver,
exposing the clock, GPIO and pinctrl functionality. However, after taking
a step back, this would lead to a messy binding. Indeed, a single node
would be a GPIO controller, clock controller, pinmux controller, and
more.

This patch adopts a more classical solution of a top-level syscon node
with sub-nodes for the individual devices. The main benefit will be to
have each functional block associated to its own sub-node where we can
put its own properties.

The introduction of the Armada 7K/8K is still in the early stage so the
plan is to remove the old binding. However, we don't want to break the
device tree compatibility for the few devices already in the field. For
this we still keep the support of the legacy compatible string with a big
warning in the kernel about updating the device tree.

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/cc8c8c40fa4c4e71133033358992ec38e5aa2be5.1496239589.git-series.gregory.clement@free-electrons.com
2017-06-01 12:03:21 +09:00
Gregory CLEMENT 55de4d06b4 clk: mvebu: ap806: do not depend anymore of the *-clock-output-names
As it was done for the cp110, this patch modifies the way the clock names
are created. The name of each clock is now created by using its physical
address as a prefix (as it was done for the platform device
names). Thanks to this we have an automatic way to compute a unique name.

Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/e66cdd54d36c6bef78460a51e577f171b6ccb031.1496239589.git-series.gregory.clement@free-electrons.com
2017-06-01 12:03:17 +09:00
Gregory CLEMENT d9ff21eea1 clk: mvebu: ap806: cosmetic improvement
Instead of using &pdev->dev all over the place, introduce a pointer
variable for it.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/5a55e081d96fc6d2a28331b59df90f56d32a9f24.1496239589.git-series.gregory.clement@free-electrons.com
2017-06-01 12:03:11 +09:00
Chen-Yu Tsai d85da227c3 clk: sunxi-ng: a64: Export PLL_PERIPH0 clock for the PRCM
The PRCM takes PLL_PERIPH0 as one of its parents for the AR100 clock.
As such we need to be able to describe this relationship in the device
tree.

Export the PLL_PERIPH0 clock so we can reference it in the PRCM node.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-05-31 21:57:30 +02:00
Chen-Yu Tsai c4be8c68e6 clk: sunxi-ng: h3: Export PLL_PERIPH0 clock for the PRCM
The PRCM takes PLL_PERIPH0 as one of its parents for the AR100 clock.
As such we need to be able to describe this relationship in the device
tree.

Export the PLL_PERIPH0 clock so we can reference it in the PRCM node.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-05-31 21:57:27 +02:00
Neil Armstrong 14c735c8e3 clk: meson-gxbb: Add EE 32K Clock for CEC
On Amlogic GX SoCs, there is two CEC controllers :
- An Amlogic CEC custom in the AO domain
- The Synopsys HDMI-TX Controller in the EE domain

Each of these controllers needs a 32.768KHz clock, but there is two paths :
- In the EE domain, the "32k_clk" this patchs is adding
- In the AO domain, with a more complex dual divider more precise setup

The AO 32K clock support will be pushed later in the corresponding
gxbb-aoclk driver when the AE CEC driver is ready.

The EE 32k_clk must be pushed earlier since mainline support for CEC in the
Synopsys HDMI-TX controller is nearby.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
[Rebased patch on top of last changes]
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2017-05-29 12:34:23 +00:00
Jerome Brunet 39c42ca9b2 clk: gxbb: remove CLK_IGNORE_UNUSED from clk81
clk81 already has CLK_IS_CRITICAL so CLK_IGNORE_UNUSED is not
necessary

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-05-29 12:34:06 +00:00
Martin Blumenstingl be58e49669 clk: meson: meson8b: mark clk81 as critical
Disabling clk81 results in an immediate freeze of the whole system. This
can happen "accidentally" when the last child-clock of clk81 is disabled
(in this case the common clock framework also disables clk81, even if it
was only enabled indirectly before).

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-05-29 12:34:06 +00:00
Martin Blumenstingl 96b61c8d2e clk: meson: gxbb: remove the "cpu_clk" from the GXBB and GXL driver
It seems that the "cpu_clk" was carried over from the meson8b clock
controller driver. On Meson GX (GXBB/GXL/GXM) the registers which are
used by the cpu_clk have a different purpose (in other words: they don't
control the CPU clock anymore). HHI_SYS_CPU_CLK_CNTL1 bits 31:24 are
reserved according to the public S905 datasheet, while bit 23 is the
"A53_trace_clk_DIS" gate (which according to the datasheet should only
be used in case a silicon bug is discovered) and bits 22:20 are a
divider (A53_trace_clk). The meson clk-cpu code however expects that
bits 28:20 are reserved for a divider (according to the public S805
datasheet this "SCALE_DIV: This value represents an N+1 divider of the
input clock.").

The CPU clock on Meson GX SoCs is provided by the SCPI DVFS clock
driver instead. Two examples from a Meson GXL S905X SoC:
- vcpu (SCPI DVFS clock 0) rate: 1000000000 / cpu_clk rate: 708000000
- vcpu (SCPI DVFS clock 0) rate: 1512000000 / cpu_clk rate: 708000000

Unfortunately the CLKID_CPUCLK was already exported (but is currently
not used) to DT. Due to the removal of this clock definition there is
now a hole in the clk_hw_onecell_data (which is not a problem because
this case is already handled in gxbb_clkc_probe).

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2017-05-29 12:33:50 +00:00
Martin Blumenstingl f40a8ce96a clk: meson-gxbb: un-export the CPU clock
The CPU clock defined in the Meson GX clock driver is actually a
left-over from the Meson8b clock controller. Un-export the clock so we
can remove it from the driver.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2017-05-29 12:33:19 +00:00
Helmut Klein 9dc6bd7678 clk: meson-gxbb: expose UART clocks
Expose the clock ids of the three none AO uarts to the dt-bindings

Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Helmut Klein <hgkr.klein@gmail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
[tidy the commit message to match similar change]
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2017-05-29 12:33:08 +00:00
Neil Armstrong 34f267f162 clk: meson-gxbb: expose SPICC gate
Expose the SPICC gate clock to enable the SPICC controller.

Acked-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
[tidy commit message to match similar changes]
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2017-05-29 12:31:26 +00:00
Jerome Brunet 0420dbb5ac clk: meson-gxbb: expose spdif master clock
Expose the spdif master clock and the mux to select the appropriate spdif
clock parent depending on the data source.

Acked-by: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2017-05-29 12:15:22 +00:00
Jerome Brunet b4d44cdcaf clk: meson-gxbb: expose i2s master clock
Expose cts_amclk in the device tree bindings

Acked-by: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2017-05-29 12:15:11 +00:00
Jerome Brunet c5aee2bc99 clk: meson-gxbb: expose spdif clock gates
Expose the clock gates required for the spdif output

Acked-by: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2017-05-29 12:15:01 +00:00
Michael Turquette 658a756803 KConfig fix:
- clk: meson: gxbb: fix build error without RESET_CONTROLLER
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Merge tag 'meson-clk-fixes-for-4.12-rc2' of git://github.com/baylibre/clk-meson into clk-fixes

KConfig fix:
- clk: meson: gxbb: fix build error without RESET_CONTROLLER
2017-05-25 14:11:11 -07:00
Boris Brezillon 370d919271 clk: sunxi-ng: sun5i: Fix ahb_bist_clk definition
AHB BIST gate is actually controlled with bit 7.

This bug was detected while trying to use the NAND controller which is
using the DMA engine to transfer data to the NAND.
Since the ahb_bist_clk gate bit conflicts with the ahb_dma_clk gate bit,
the core was disabling the DMA engine clock as part of its 'disable
unused clks' procedure, which was causing all DMA transfers to fail after
this point.

Fixes: 5e73761786 ("clk: sunxi-ng: Add sun5i CCU driver")
Cc: stable@vger.kernel.org
Reported-by: Angus Ainslie <angus@akkea.ca>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Tested-by: Angus Ainslie <angus@akkea.ca>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/1495643669-28221-1-git-send-email-boris.brezillon@free-electrons.com
2017-05-25 14:04:19 -07:00
Geert Uytterhoeven 2d75588a28 clk: renesas: r8a7794: Add new CPG/MSSR driver
Add a new R-Car E2 Clock Pulse Generator / Module Standby and Software
Reset driver, using the CPG/MSSR driver core.  This will enable support
for module resets, which are not supported by the existing driver.

The old driver can still be used through a Kconfig option, to preserve
backward compatibility with old DTBs.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-24 10:20:03 +02:00
Geert Uytterhoeven fd3c2f3826 clk: renesas: r8a7792: Add new CPG/MSSR driver
Add a new R-Car V2H Clock Pulse Generator / Module Standby and Software
Reset driver, using the CPG/MSSR driver core.  This will enable support
for module resets, which are not supported by the existing driver.

The old driver can still be used through a Kconfig option, to preserve
backward compatibility with old DTBs.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-24 10:20:01 +02:00
Geert Uytterhoeven 6449ab8141 clk: renesas: r8a7791/r8a7793: Add new CPG/MSSR driver
Add a new R-Car M2-W/N Clock Pulse Generator / Module Standby and
Software Reset driver, using the CPG/MSSR driver core.  This will enable
support for module resets, which are not supported by the existing
driver.

The old driver can still be used through a Kconfig option, to preserve
backward compatibility with old DTBs.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-24 10:19:59 +02:00
Geert Uytterhoeven d4e59f108e clk: renesas: r8a7790: Add new CPG/MSSR driver
Add a new R-Car H2 Clock Pulse Generator / Module Standby and Software
Reset driver, using the CPG/MSSR driver core.  This will enable support
for module resets, which are not supported by the existing driver.

The old driver can still be used through a Kconfig option, to preserve
backward compatibility with old DTBs.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-24 10:19:56 +02:00
Geert Uytterhoeven 80978a4be2 clk: renesas: Rework Kconfig and Makefile logic
The goals are to:
  - Allow precise control over and automatic selection of which
    (sub)drivers are used for which SoC (which may change in the
    future),
  - Allow adding support for new SoCs easily,
  - Allow compile-testing of all (sub)drivers,
  - Keep driver selection logic in the subsystem-specific Kconfig,
    independent from the architecture-specific Kconfig (i.e. no "select"
    from arch/arm64/Kconfig.platforms), to avoid dependencies.

This is implemented by:
  - Introducing Kconfig symbols for all drivers and sub-drivers,
  - Introducing the Kconfig symbol CLK_RENESAS, which is enabled
    automatically when building for a Renesas ARM platform, and which
    enables all required drivers without interaction of the user, based
    on SoC-specific ARCH_* symbols,
  - Allowing the user to enable any Kconfig symbol manually if
    COMPILE_TEST is enabled,
  - Using the new Kconfig symbols instead of the ARCH_* symbols to
    control compilation in the Makefile,
  - Always entering drivers/clk/renesas/ during the build.

Note that currently not all (sub)drivers are enabled for
compile-testing, as they depend on independent fixes in other
subsystems.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
2017-05-24 10:19:28 +02:00
Geert Uytterhoeven 76394a36ef clk: renesas: cpg-mssr: Initialize error pointer using ERR_PTR()
Coccinelle warns:

    drivers/clk/renesas/renesas-cpg-mssr.c:323:14-21: ERROR: PTR_ERR applied after initialization to constant on line 260

Initialize clk using ERR_PTR(-ENOTSUPP) instead of NULL to fix this.

Reported-by: kbuild test robot <fengguang.wu@intel.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-24 10:19:24 +02:00
Arnd Bergmann f36afd38c5 clk: sunxi-ng: enable SUNXI_CCU_MP for PRCM
The newly added PRCM CCU driver uses SUNXI_CCU_MP_WITH_MUX_GATE, which causes
a link error when no other driver enables SUNXI_CCU_MP:

drivers/clk/built-in.o:(.data+0x5c8c8): undefined reference to `ccu_mp_ops'

This adds an explicit 'select' statement for it.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-05-18 08:49:18 +02:00
Elaine Zhang f88b8e7365 clk: rockchip: fix up the RK3228 clk cpu setting table
support more cpu freq, and add armcore div setting.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-05-17 19:50:37 +02:00
Tobias Regnery dbed87a9d3 clk: meson: gxbb: fix build error without RESET_CONTROLLER
With CONFIG_RESET_CONTROLLER=n we see the following link error in the
meson gxbb clk driver:

drivers/built-in.o: In function 'gxbb_aoclkc_probe':
drivers/clk/meson/gxbb-aoclk.c:161: undefined reference to 'devm_reset_controller_register'

Fix this by selecting the reset controller subsystem.

Fixes: f8c11f7991 ("clk: meson: Add GXBB AO Clock and Reset controller driver")
Signed-off-by: Tobias Regnery <tobias.regnery@gmail.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
[narmstrong: Added fixes-by tag]
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-05-16 11:05:01 +02:00
Geert Uytterhoeven c5c3bdaace clk: renesas: r8a7795: Correct pwm, gpio, and i2c parent clocks on ES2.0
Cfr. the errata of April 14, 2017, for the R-Car Gen3 Hardware Manual
Rev. 0.53E.

These have no user-visible effect, as the clock frequencies stay the
same.

Fixes: 5573d19412 ("clk: renesas: r8a7795: Add support for R-Car H3 ES2.0")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2017-05-15 09:46:31 +02:00
Geert Uytterhoeven e05e853e2c clk: renesas: Use pm_clk_no_clocks() helper i.s.o. direct access
The pm_subsys_data.clock_list member exists only if CONFIG_PM_CLK=y.
Hence direct accesses to this field break compile-testing on platforms
where CONFIG_PM_CLK=n.

To fix this, use the pm_clk_no_clocks() helper instead, for which a
dummy version is provided if CONFIG_PM_CLK=n.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <simon.horman@netronome.com>
2017-05-15 09:46:31 +02:00
Geert Uytterhoeven dcf6a00dff clk: renesas: Do not build clk-div6 for R8A7792
R-Car V2H does not have "DIV6" programmable clocks, hence there is no
need to build clk-div6.o.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2017-05-15 09:46:31 +02:00
Takeshi Kihara 8a187f0c62 clk: renesas: r8a7796: Add INTC-EX clock
Add the "intc-ex" clock to the R8A7796 CPG MSSR driver.

According to information from the hardware team the INTC-EX
parent clock is CP. The next data sheet version will include
this information.

[takeshi.kihara.df: Ported from commit f099aa0757 ("clk: shmobile:
 r8a7795: Add INTC-EX clock") to drivers/clk/renesas/r8a7796-cpg-mssr.c]
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-15 09:46:31 +02:00
Harunobu Kurokawa 9097f5e3c2 clk: renesas: r8a7796: Add PCIe clocks
This patch adds PCIEC{0,1} clocks for R8A7796 SoC.

Signed-off-by: Harunobu Kurokawa <harunobu.kurokawa.dn@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-15 09:46:31 +02:00
Ryo Kodama a0b381faff clk: renesas: r8a7796: Add PWM clock
This patch adds PWM clock for PWM.

Signed-off-by: Ryo Kodama <ryo.kodama.vz@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
[geert: Correct parent clock]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-15 09:46:31 +02:00
Kazuya Mizuguchi a703e11f41 clk: renesas: r8a7796: Add HS-USB clock
This patch adds HS-USB-IF clock for R8A7796 SoC.

Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-15 09:46:31 +02:00
Kazuya Mizuguchi 60c2db767a clk: renesas: r8a7796: Add Sound DVC clocks
This patch adds adds SCU(DVC{0,1}) clocks for R8A7796 SoC.

Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-15 09:46:31 +02:00
Kazuya Mizuguchi df42e584f2 clk: renesas: r8a7796: Add Sound SRC clock
This patch adds SCU(all), SCU(SRC{0,1,2,3,4,5,6,7,8,9}), SCU(CTU00,
CTU01, CTU02, CTU03, MIX0) and SCU (CTU10, CTU11, CTU12, CTU13, MIX1)
clocks for R8A7796 SoC.

Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-15 09:46:31 +02:00
Kazuya Mizuguchi 8fe3574280 clk: renesas: r8a7796: Add Sound SSI clock
This patch adds SSI(all) and SSI{0,1,2,3,4,5,6,7,8,9} clocks for R8A7796
SoC.

Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-15 09:46:31 +02:00
Hiromitsu Yamasaki 7cb1ce2688 clk: renesas: r8a7796: Add USB-DMAC clocks
This patch adds USB-DMAC{0,1} clocks for R8A7796 SoC.

Signed-off-by: Hiromitsu Yamasaki <hiromitsu.yamasaki.ym@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-15 09:46:31 +02:00
Hiromitsu Yamasaki c1da6b4b84 clk: renesas: r8a7796: Add Audio-DMAC clocks
This patch adds A-DMAC{0,1} clocks for R8A7796 SoC.

Signed-off-by: Hiromitsu Yamasaki <hiromitsu.yamasaki.ym@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
[geert: Correct parent clocks, preserve sort order]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-15 09:46:31 +02:00
Kazuya Mizuguchi f4c542923d clk: renesas: r8a7796: Add EHCI/OHCI clocks
This patch adds EHCI/OHCI{0,1} clocks for R8A7796 SoC.

Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-15 09:46:31 +02:00
Koji Matsuoka 12390605ac clk: renesas: r8a7796: Add HDMI clock
This patch adds HDMI-IF0 clock for R8A7796 SoC.

Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-15 09:46:31 +02:00
Takeshi Kihara f5ca01141c clk: renesas: r8a7795: Add HS-USB ch3 clock
This patch adds valid HS-USB ch3 clock from R8A7795 ES2.0 SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-15 09:46:31 +02:00
Takeshi Kihara 0a12c4400c clk: renesas: r8a7795: Add USB-DMAC ch3 clock
This patch supports the clock of USB-DMAC ch3 module added from R8A7795
ES2.0 SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-15 09:46:31 +02:00
Takeshi Kihara 66fbee35d5 clk: renesas: r8a7795: Add EHCI/OHCI ch3 clock
This patch supports the clock of EHCI/OHCI ch3 module added from R8A7795
ES2.0 SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-15 09:46:31 +02:00
Geert Uytterhoeven 5ed793b3b2 clk: renesas: r8a7745: Remove PLL configs for MD19=0
According to tables 7.5b and 7.6b of the RZ/G Series Hardware User's
Manual Rev.1.00, MD19=0 is a prohibited setting.

Hence stop looking at MD19, and remove all PLL configurations for
MD19=0.

Fixes: 9127d54bb8 ("clk: renesas: cpg-mssr: Add R8A7745 support")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-15 09:46:31 +02:00
Geert Uytterhoeven b93e7eb5ed clk: renesas: r8a7745: Remove nonexisting scu-src[0789] clocks
RZ/G1E does not have the SCU-SRC[0789] modules and module clocks.

Fixes: 9127d54bb8 ("clk: renesas: cpg-mssr: Add R8A7745 support")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-15 09:46:31 +02:00
Geert Uytterhoeven b7c563c489 clk: renesas: rcar-gen2: Fix PLL0 on R-Car V2H and E2
R-Car V2H and E2 do not have the PLL0CR register, but use a fixed
multiplier (depending on mode pins) and divider.

This corrects the clock rate of "pll0" (PLL0 VCO after post divider) on
R-Car V2H and E2 from 1.5 GHz to 1 GHz.

Inspired by Sergei Shtylyov's work for the common R-Car Gen2 and RZ/G
Clock Pulse Generator support core.

Fixes: 7c4163aae3 ("ARM: dts: r8a7792: initial SoC device tree")
Fixes: 0dce5454d5 ("ARM: shmobile: Initial r8a7794 SoC device tree")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-15 09:46:31 +02:00
Yong Deng 7ffc781ec4 clk: sunxi-ng: v3s: Fix usb otg device reset bit
V3S's usb otg device reset bit should be 24, not 23.

Cc: stable@vger.kernel.org
Signed-off-by: Yong Deng <iemdey@gmail.com>
Reviewed-By: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-05-14 08:27:17 +02:00
Chen-Yu Tsai 38b8f82386 clk: sunxi-ng: a31: Correct lcd1-ch1 clock register offset
The register offset for the lcd1-ch1 clock was incorrectly pointing to
the lcd0-ch1 clock. This resulted in the lcd0-ch1 clock being disabled
when the clk core disables unused clocks. This then stops the simplefb
HDMI output path.

Reported-by: Bob Ham <rah@settrans.net>
Fixes: c6e6c96d8f ("clk: sunxi-ng: Add A31/A31s clocks")
Cc: stable@vger.kernel.org # 4.9.x-
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-05-14 08:27:17 +02:00
Linus Torvalds b5a53b61a2 Sort of on the quieter side this time, which is probably due more
to me not catching up as quickly on patch review than anything else.
 Overall it seems normal though, a few small changes to the core, mostly
 small non-critical fixes here and there as well as driver updates for new
 and existing hardware support. The biggest things are the TI clk driver
 rework to lay the groundwork for clkctrl support in the next merge window
 and the AmLogic audio/graphics clk support.
 
 Core:
  * clk_possible_parents debugfs file so we know which parents a clk
    could possibly have
  * Fix to make clk rate change notifiers stop on the first failure instead
    of continuing
 
 New Drivers:
  * Mediatek MT6797 SoCs
  * hi655x PMIC clks
  * AmLogic Meson SoC i2s and spdif audio clks and Mali graphics clks
  * Allwinner H5 SoCs and PRCM hardware
 
 Updates:
  * Nvidia Tegra T210 cleanups and non-critical fixes
  * TI OMAP cleanups in preparation for clkctrl support
  * Trivial fixes like kcalloc(), devm_* conversions, and seq_puts()
  * ZTE zx296718 SoC VGA clks
  * Rockchip clk-ids, fixups, and rename of rk1108 to rv1108
  * Support for IDT VersaClock 5P49V5935
  * Renesas R-Car H3 and M3-W IMR clks and ES2.0 rev of R-Car H3 support
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
 "Sort of on the quieter side this time, which is probably due more to
  me not catching up as quickly on patch review than anything else.
  Overall it seems normal though, a few small changes to the core,
  mostly small non-critical fixes here and there as well as driver
  updates for new and existing hardware support.

  The biggest things are the TI clk driver rework to lay the groundwork
  for clkctrl support in the next merge window and the AmLogic
  audio/graphics clk support.

  Core:
   - clk_possible_parents debugfs file so we know which parents a clk
     could possibly have
   - Fix to make clk rate change notifiers stop on the first failure
     instead of continuing

  New Drivers:
   - Mediatek MT6797 SoCs
   - hi655x PMIC clks
   - AmLogic Meson SoC i2s and spdif audio clks and Mali graphics clks
   - Allwinner H5 SoCs and PRCM hardware

  Updates:
   - Nvidia Tegra T210 cleanups and non-critical fixes
   - TI OMAP cleanups in preparation for clkctrl support
   - trivial fixes like kcalloc(), devm_* conversions, and seq_puts()
   - ZTE zx296718 SoC VGA clks
   - Rockchip clk-ids, fixups, and rename of rk1108 to rv1108
   - IDT VersaClock 5P49V5935 support
   - Renesas R-Car H3 and M3-W IMR clks and ES2.0 rev of R-Car H3
     support"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (151 commits)
  clk: x86: pmc-atom: Checking for IS_ERR() instead of NULL
  clk: ti: divider: try to fix ti_clk_register_divider
  clk: mvebu: Use kcalloc() in two functions
  clk: mvebu: Use kcalloc() in of_cpu_clk_setup()
  clk: nomadik: Delete error messages for a failed memory allocation in two functions
  clk: nomadik: Use seq_puts() in nomadik_src_clk_show()
  clk: Improve a size determination in two functions
  clk: Replace four seq_printf() calls by seq_putc()
  clk: si5351: Delete an error message for a failed memory allocation in si5351_i2c_probe()
  clk: si5351: Use devm_kcalloc() in si5351_i2c_probe()
  clk: at91: Use kcalloc() in of_at91_clk_pll_get_characteristics()
  reset: mediatek: Add MT2701 ethsys reset controller include file
  clk: mediatek: add mt2701 ethernet reset
  clk: hi6220: Add the hi655x's pmic clock
  clk: ti: fix building without legacy omap3
  clk: ti: fix linker error with !SOC_OMAP4
  clk: hi3620: Fix a typo in one variable name
  clk: hi3620: Delete error messages for a failed memory allocation in two functions
  clk: hi3620: Use kcalloc() in hi3620_mmc_clk_init()
  clk: hisilicon: Delete error messages for failed memory allocations in hisi_clk_init()
  ...
2017-05-10 13:38:18 -07:00
Linus Torvalds c6778ff813 ARM: 64-bit DT updates
Device-tree updates for arm64 platforms. Just as with 32-bit, a bunch of smaller
 changes, but also some new platforms that are worth mentioning:
 
  * Rockchip RK3399 platforms for Chromebooks, including Samsung Chromebook
    Plus (Kevin)
  * Orange Pi PC2 (Allwinner H5)
  * Freescale LS2088A and LS1088A SoCs
  * Expanded support for Nvidia Tegra186 (and Jetson TX2)
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Merge tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM 64-bit DT updates from Olof Johansson:
 "Device-tree updates for arm64 platforms. Just as with 32-bit, a bunch
  of smaller changes, but also some new platforms that are worth
  mentioning:

   - Rockchip RK3399 platforms for Chromebooks, including Samsung
     Chromebook Plus (Kevin)

   - Orange Pi PC2 (Allwinner H5)

   - Freescale LS2088A and LS1088A SoCs

   - Expanded support for Nvidia Tegra186 (and Jetson TX2)"

* tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (180 commits)
  arm64: dts: Add basic DT to support Spreadtrum's SP9860G
  arm64: dts: exynos: Use - instead of @ for DT OPP entries
  arm64: dts: exynos: Add support for s6e3hf2 panel device on TM2e board
  arm64: dts: juno: add information about L1 and L2 caches
  arm64: dts: juno: fix few unit address format warnings
  arm64: marvell: dts: enable the crypto engine on the Armada 8040 DB
  arm64: marvell: dts: enable the crypto engine on the Armada 7040 DB
  arm64: marvell: dts: add crypto engine description for 7k/8k
  arm64: dts: marvell: add sdhci support for Armada 7K/8K
  arm64: dts: marvell: add eMMC support for Armada 37xx
  arm64: dts: hisi: add pinctrl dtsi file for HiKey960 development board
  arm64: dts: hisi: add drive strength levels of the pins for Hi3660 SoC
  arm64: dts: hisi: enable the NIC and SAS for the hip07-d05 board
  arm64: dts: hisi: add SAS nodes for the hip07 SoC
  arm64: dts: hisi: add RoCE nodes for the hip07 SoC
  arm64: dts: hisi: add network related nodes for the hip07 SoC
  arm64: dts: hisi: add mbigen nodes for the hip07 SoC
  arm64: dts: rockchip: fix the memory size of PX5 Evaluation board
  arm64: dts: hisilicon: add dts files for hi3798cv200-poplar board
  dt-bindings: arm: hisilicon: add bindings for hi3798cv200 SoC and Poplar board
  ...
2017-05-09 10:07:33 -07:00
Linus Torvalds 0160e00ae8 ARM: SoC driver updates
Driver updates for ARM SoCs.
 
 * Reset subsystem, merged through arm-soc by tradition:
  - Make bool drivers explicitly non-modular
  - New support for i.MX7 and Arria10 reset controllers
 
 * PATA driver for Palmchip BK371 (acked by Tejun)
 
 * Power domain drivers for i.MX (GPC, GPCv2)
  - Moved out of mach-imx for GPC
  - Bunch of tweaks, fixes, etc
 
 * PMC support for Tegra186
 
 * SoC detection support for Renesas RZ/G1H and RZ/G1N
 
 * Move Tegra flow controller driver from mach directory to drivers/soc
  - (Power management / CPU power driver)
 
 * Misc smaller tweaks for other platforms
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Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC driver updates from Olof Johansson:
 "Driver updates for ARM SoCs:

  Reset subsystem, merged through arm-soc by tradition:
   - Make bool drivers explicitly non-modular
   - New support for i.MX7 and Arria10 reset controllers

  PATA driver for Palmchip BK371 (acked by Tejun)

  Power domain drivers for i.MX (GPC, GPCv2)
   - Moved out of mach-imx for GPC
   - Bunch of tweaks, fixes, etc

  PMC support for Tegra186

  SoC detection support for Renesas RZ/G1H and RZ/G1N

  Move Tegra flow controller driver from mach directory to drivers/soc
   - (Power management / CPU power driver)

  Misc smaller tweaks for other platforms"

* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (60 commits)
  soc: pm-domain: Fix the mangled urls
  soc: renesas: rcar-sysc: Add support for R-Car H3 ES2.0
  soc: renesas: rcar-sysc: Add support for fixing up power area tables
  soc: renesas: Register SoC device early
  soc: imx: gpc: add workaround for i.MX6QP to the GPC PD driver
  dt-bindings: imx-gpc: add i.MX6 QuadPlus compatible
  soc: imx: gpc: add defines for domain index
  soc: imx: Add GPCv2 power gating driver
  dt-bindings: Add GPCv2 power gating driver
  ARM/clk: move the ICST library to drivers/clk
  ARM: plat-versatile: remove stale clock header
  ARM: keystone: Drop PM domain support for k2g
  soc: ti: Add ti_sci_pm_domains driver
  dt-bindings: Add TI SCI PM Domains
  PM / Domains: Do not check if simple providers have phandle cells
  PM / Domains: Add generic data pointer to genpd data struct
  soc/tegra: Add initial flowctrl support for Tegra132/210
  soc/tegra: flowctrl: Add basic platform driver
  soc/tegra: Move Tegra flowctrl driver
  ARM: tegra: Remove unnecessary inclusion of flowctrl header
  ...
2017-05-09 10:01:15 -07:00
Stephen Boyd ad61dd303a scripts/spelling.txt: add regsiter -> register spelling mistake
This typo is quite common.  Fix it and add it to the spelling file so
that checkpatch catches it earlier.

Link: http://lkml.kernel.org/r/20170317011131.6881-2-sboyd@codeaurora.org
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2017-05-08 17:15:13 -07:00
Linus Torvalds be580e7522 MMC core:
- Continue to re-factor code to prepare for eMMC CMDQ and blkmq support
  - Introduce queue semantics to prepare for eMMC CMDQ and blkmq support
  - Add helper functions to manage temporary enable/disable of eMMC CMDQ
  - Improve wait-busy detection for SDIO
 
 MMC host:
  - cavium: Add driver to support Cavium controllers
  - cavium: Extend Cavium driver to support Octeon SOCs and ThunderX SOCs
  - bcm2835: Add new driver for Broadcom BCM2835 controller
  - sdhci-xenon: Add driver to support Marvell Xenon SDHCI controller
  - sdhci-tegra: Add support for the Tegra186 variant
  - sdhci-of-esdhc: Support for UHS-I SD cards
  - sdhci-of-esdhc: Support for eMMC HS200 cards
  - sdhci-cadence: Add eMMC HS400 enhanced strobe support
  - sdhci-esdhc-imx: Reset tuning circuit when needed
  - sdhci-pci: Modernize and clean-up some PM related code
  - sdhci-pci: Avoid re-tuning at runtime PM for some Intel devices
  - sdhci-pci|acpi: Use aggressive PM for some Intel BYT controllers
  - sdhci: Re-factoring and modernizations
  - sdhci: Optimize delay loops
  - sdhci: Improve register dump print format
  - sdhci: Add support for the Command Queue Engine
  - meson-gx: Various improvements and clean-ups
  - meson-gx: Add support for CMD23
  - meson-gx: Basic tuning support to avoid CRC errors
  - s3cmci: Enable probing via DT
  - mediatek: Improve tuning support for eMMC HS200 and HS400 mode
  - tmio: Improve DMA support
  - tmio: Use correct response for CMD12
  - dw_mmc: Minor improvements and clean-ups
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Merge tag 'mmc-v4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc

Pull MMC updates from Ulf Hansson:
 "MMC core:
   - Continue to re-factor code to prepare for eMMC CMDQ and blkmq support
   - Introduce queue semantics to prepare for eMMC CMDQ and blkmq support
   - Add helper functions to manage temporary enable/disable of eMMC CMDQ
   - Improve wait-busy detection for SDIO

  MMC host:
   - cavium: Add driver to support Cavium controllers
   - cavium: Extend Cavium driver to support Octeon and ThunderX SOCs
   - bcm2835: Add new driver for Broadcom BCM2835 controller
   - sdhci-xenon: Add driver to support Marvell Xenon SDHCI controller
   - sdhci-tegra: Add support for the Tegra186 variant
   - sdhci-of-esdhc: Support for UHS-I SD cards
   - sdhci-of-esdhc: Support for eMMC HS200 cards
   - sdhci-cadence: Add eMMC HS400 enhanced strobe support
   - sdhci-esdhc-imx: Reset tuning circuit when needed
   - sdhci-pci: Modernize and clean-up some PM related code
   - sdhci-pci: Avoid re-tuning at runtime PM for some Intel devices
   - sdhci-pci|acpi: Use aggressive PM for some Intel BYT controllers
   - sdhci: Re-factoring and modernizations
   - sdhci: Optimize delay loops
   - sdhci: Improve register dump print format
   - sdhci: Add support for the Command Queue Engine
   - meson-gx: Various improvements and clean-ups
   - meson-gx: Add support for CMD23
   - meson-gx: Basic tuning support to avoid CRC errors
   - s3cmci: Enable probing via DT
   - mediatek: Improve tuning support for eMMC HS200 and HS400 mode
   - tmio: Improve DMA support
   - tmio: Use correct response for CMD12
   - dw_mmc: Minor improvements and clean-ups"

* tag 'mmc-v4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc: (148 commits)
  mmc: sdhci-of-esdhc: limit SD clock for ls1012a/ls1046a
  mmc: sdhci-of-esdhc: poll ESDHC_CLOCK_STABLE bit with udelay
  mmc: sdhci-xenon: Fix default value of LOGIC_TIMING_ADJUST for eMMC5.0 PHY
  mmc: sdhci-xenon: Fix the work flow in xenon_remove().
  MIPS: Octeon: cavium_octeon_defconfig: Enable Octeon MMC
  mmc: sdhci-xenon: Remove redundant dev_err call in get_dt_pad_ctrl_data()
  mmc: cavium: Use module_pci_driver to simplify the code
  mmc: cavium: Add MMC support for Octeon SOCs.
  mmc: cavium: Fix detection of block or byte addressing.
  mmc: core: Export API to allow hosts to get the card address
  mmc: sdio: Fix sdio wait busy implement limitation
  mmc: sdhci-esdhc-imx: reset tuning circuit when power on mmc card
  clk: apn806: fix spelling mistake: "mising" -> "missing"
  mmc: sdhci-of-esdhc: add delay between tuning cycles
  mmc: sdhci: Control the delay between tuning commands
  mmc: sdhci-of-esdhc: add tuning support
  mmc: sdhci-of-esdhc: add support for signal voltage switch
  mmc: sdhci-of-esdhc: add peripheral clock support
  mmc: sdhci-pci: Allow for 3 bytes from Intel DSM
  mmc: cavium: Fix a shift wrapping bug
  ...
2017-05-02 17:34:32 -07:00
Linus Torvalds 5a0387a8a8 Merge branch 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6
Pull crypto updates from Herbert Xu:
 "Here is the crypto update for 4.12:

  API:
   - Add batch registration for acomp/scomp
   - Change acomp testing to non-unique compressed result
   - Extend algorithm name limit to 128 bytes
   - Require setkey before accept(2) in algif_aead

  Algorithms:
   - Add support for deflate rfc1950 (zlib)

  Drivers:
   - Add accelerated crct10dif for powerpc
   - Add crc32 in stm32
   - Add sha384/sha512 in ccp
   - Add 3des/gcm(aes) for v5 devices in ccp
   - Add Queue Interface (QI) backend support in caam
   - Add new Exynos RNG driver
   - Add ThunderX ZIP driver
   - Add driver for hardware random generator on MT7623 SoC"

* 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: (101 commits)
  crypto: stm32 - Fix OF module alias information
  crypto: algif_aead - Require setkey before accept(2)
  crypto: scomp - add support for deflate rfc1950 (zlib)
  crypto: scomp - allow registration of multiple scomps
  crypto: ccp - Change ISR handler method for a v5 CCP
  crypto: ccp - Change ISR handler method for a v3 CCP
  crypto: crypto4xx - rename ce_ring_contol to ce_ring_control
  crypto: testmgr - Allow ecb(cipher_null) in FIPS mode
  Revert "crypto: arm64/sha - Add constant operand modifier to ASM_EXPORT"
  crypto: ccp - Disable interrupts early on unload
  crypto: ccp - Use only the relevant interrupt bits
  hwrng: mtk - Add driver for hardware random generator on MT7623 SoC
  dt-bindings: hwrng: Add Mediatek hardware random generator bindings
  crypto: crct10dif-vpmsum - Fix missing preempt_disable()
  crypto: testmgr - replace compression known answer test
  crypto: acomp - allow registration of multiple acomps
  hwrng: n2 - Use devm_kcalloc() in n2rng_probe()
  crypto: chcr - Fix error handling related to 'chcr_alloc_shash'
  padata: get_next is never NULL
  crypto: exynos - Add new Exynos RNG driver
  ...
2017-05-02 15:53:46 -07:00
Dan Carpenter 0119dc6132 clk: x86: pmc-atom: Checking for IS_ERR() instead of NULL
clkdev_hw_create() returns NULLs on error, it doesn't return error
pointers.

Fixes: 41ee7caf59 ("clk: x86: add "mclk" alias for Baytrail/Cherrytrail")
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Acked-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-05-01 11:13:25 -07:00
Arnd Bergmann 3417f3528a clk: ti: divider: try to fix ti_clk_register_divider
Commit 6c0afb5039 ("clk: ti: convert to use proper register
definition for all accesses") converted all register accesses in
the TI clk driver to use a proper struct instead of a void
pointer casted struct that fits into a u32. Unfortunately, it
missed a conversion here in the didivder code, leading to a
compiler warning like so:

drivers/clk/ti/divider.c: In function 'ti_clk_register_divider':
drivers/clk/ti/divider.c:460:8: error: 'reg' may be used uninitialized in this function [-Werror=maybe-uninitialized]

Treating a 'u32' variable as a structure leads to a stack
overflow here, and the register address we pass down is never
initialized. Convert this part of the code as well so things
work properly.

Fixes: 6c0afb5039 ("clk: ti: convert to use proper register definition for all accesses")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
[sboyd@codeaurora.org: Fixed fixes tag, rewrote commit message,
s/reg_setup/reg/]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-04-28 11:07:09 -07:00
Arnd Bergmann 36c02d0be4 clk: sunxi-ng: always select CCU_GATE
When the base driver is enabled but all SoC specific drivers are turned
off, we now get a build error after code was added to always refer to the
clk gates:

drivers/clk/built-in.o: In function `ccu_pll_notifier_cb':
:(.text+0x154f8): undefined reference to `ccu_gate_helper_disable'
:(.text+0x15504): undefined reference to `ccu_gate_helper_enable'

This changes the Kconfig to always require the gate code to be built-in
when CONFIG_SUNXI_CCU is set.

Fixes: 02ae2bc6fe ("clk: sunxi-ng: Add clk notifier to gate then ungate PLL clocks")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-04-28 10:47:21 -07:00
Colin Ian King a82d12b8d5 clk: apn806: fix spelling mistake: "mising" -> "missing"
trivial fix to spelling mistake in dev_warn message

Signed-off-by: Colin Ian King <colin.king@canonical.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-04-24 21:42:28 +02:00
Gregory CLEMENT b92a3bcc7c clk: apn806: Turn the eMMC clock as optional for dts backwards compatible
First version of the binding didn't have the eMMC clock. This patch
allows to not registering the eMMC clock if it is not present in the
device tree. Then the device tree can be backwards compatible.

Suggested-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-04-24 21:42:13 +02:00
Konstantin Porotchkin a8309cedcd clk: apn806: Add eMMC clock to system controller driver
Add fixed clock of 400MHz to system controller driver.  This clock is
used as SD/eMMC clock source.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Omri Itach <omrii@marvell.com>
Reviewed-by: Hanna Hawa <hannah@marvell.com>
[fixed up conflicts, added error handling --rmk]
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-04-24 21:42:12 +02:00
Markus Elfring ee7d74339d clk: mvebu: Use kcalloc() in two functions
* Multiplications for the size determination of memory allocations
  indicated that array data structures should be processed.
  Thus use the corresponding function "kcalloc".

  This issue was detected by using the Coccinelle software.

* Replace the specification of data types by pointer dereferences
  to make the corresponding size determination a bit safer according to
  the Linux coding style convention.

Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-04-21 19:49:34 -07:00
Markus Elfring 23826e240a clk: mvebu: Use kcalloc() in of_cpu_clk_setup()
Multiplications for the size determination of memory allocations
indicated that array data structures should be processed.
Thus use the corresponding function "kcalloc".

This issue was detected by using the Coccinelle software.

Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-04-21 19:49:13 -07:00
Markus Elfring 24f8186eb8 clk: nomadik: Delete error messages for a failed memory allocation in two functions
The script "checkpatch.pl" pointed information out like the following.

WARNING: Possible unnecessary 'out of memory' message

Thus remove such statements here.

Link: http://events.linuxfoundation.org/sites/events/files/slides/LCJ16-Refactor_Strings-WSang_0.pdf
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-04-21 19:47:14 -07:00
Markus Elfring add3151133 clk: nomadik: Use seq_puts() in nomadik_src_clk_show()
A string which did not contain a data format specification should be put
into a sequence. Thus use the corresponding function "seq_puts".

This issue was detected by using the Coccinelle software.

Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-04-21 19:47:10 -07:00
Markus Elfring 1808a32019 clk: Improve a size determination in two functions
Replace the specification of two data structures by pointer dereferences
as the parameter for the operator "sizeof" to make the corresponding size
determination a bit safer according to the Linux coding style convention.

Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-04-21 19:47:02 -07:00
Markus Elfring 4d32758671 clk: Replace four seq_printf() calls by seq_putc()
Four single characters should be put into a sequence.
Thus use the corresponding function "seq_putc".

This issue was detected by using the Coccinelle software.

Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-04-21 19:45:24 -07:00
Markus Elfring 56f2150a84 clk: si5351: Delete an error message for a failed memory allocation in si5351_i2c_probe()
The script "checkpatch.pl" pointed information out like the following.

* CHECK: Comparison to NULL could be written "!drvdata"

  Thus adjust this expression.

* WARNING: Possible unnecessary 'out of memory' message

  Thus remove such a statement here.

Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-04-21 19:44:54 -07:00
Markus Elfring 9a78b16972 clk: si5351: Use devm_kcalloc() in si5351_i2c_probe()
Multiplications for the size determination of memory allocations
indicated that array data structures should be processed.
Thus use the corresponding function "devm_kcalloc".

This issue was detected by using the Coccinelle software.

Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-04-21 19:44:42 -07:00
Markus Elfring 1e5c844441 clk: at91: Use kcalloc() in of_at91_clk_pll_get_characteristics()
Multiplications for the size determination of memory allocations
indicated that array data structures should be processed.
Thus use the corresponding function "kcalloc".

This issue was detected by using the Coccinelle software.

Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-04-21 19:20:34 -07:00
John Crispin db9c4a1e65 clk: mediatek: add mt2701 ethernet reset
The ethernet clock core has a reset register that is currently not exposed
to the user. Fix this by adding the missing registration code.

Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-04-21 19:20:33 -07:00
Stephen Boyd de000a88c1 Allwinner clock changes, take 2
A few minor bug and comment fixes, plus some fixes for the PRCM CCU driver
 merged in the prior pull request
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Merge tag 'sunxi-clk-for-4.12-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into HEAD

Pull Allwinner clock changes, take 2 from Maxime Ripard:

A few minor bug and comment fixes, plus some fixes for the PRCM CCU driver
merged in the prior pull request

* tag 'sunxi-clk-for-4.12-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  clk: sunxi-ng: a80: Fix audio PLL comment not matching actual code
  clk: sunxi-ng: Fix round_rate/set_rate multiplier minimum mismatch
  clk: sunxi-ng: use 1 as fallback for minimum multiplier
  clk: sunxi-ng: fix PRCM CCU CLK_NUMBER value
  clk: sunxi-ng: fix PRCM CCU ir clk parent
2017-04-21 19:19:46 -07:00
Daniel Lezcano b68adc23bc clk: hi6220: Add the hi655x's pmic clock
The hi655x multi function device is a PMIC providing regulators.

The PMIC also provides a clock for the WiFi and the Bluetooth, let's implement
this clock in order to add it in the hi655x MFD and allow proper wireless
initialization.

Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
[sboyd@codeaurora.org: Remove clkdev usage]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-04-21 19:18:53 -07:00
Arnd Bergmann fc04f27dfc clk: ti: fix building without legacy omap3
When CONFIG_ATAGS or CONFIG_OMAP3 is disabled, we get a build error:

In file included from include/linux/clk-provider.h:15:0,
                 from drivers/clk/ti/clk.c:19:
drivers/clk/ti/clk.c: In function 'ti_clk_add_aliases':
drivers/clk/ti/clk.c:438:29: error: 'simple_clk_match_table' undeclared (first use in this function); did you mean 'simple_attr_write'?

Moving the match table down fixes it.

Fixes: c17435c56b ("clk: ti: add API for creating aliases automatically for simple clock types")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-04-21 19:01:39 -07:00
Arnd Bergmann 2158a09395 clk: ti: fix linker error with !SOC_OMAP4
When none of the OMAP4-generation SoCs are enabled, we run into a link
error for am43xx/am43xx:

drivers/clk/ti/dpll.o: In function `of_ti_am3_dpll_x2_setup':
dpll.c:(.init.text+0xd8): undefined reference to `clkhwops_omap4_dpllmx'

This is easily fixed by adding another #ifdef.

While looking at the code, I also spotted another problem with the
assignment of hw_ops variable that is not used again later. I'm
changing this to setting clk_hw->ops instead, which I guess is what
was intended here.

Fixes: 473adbf4e0 ("clk: ti: dpll44xx: fix clksel register initialization")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Tero Kristo <t-kristo@ti.com>
[sboyd@codeaurora.org: Replaced fixes tag with correct one]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-04-21 19:01:18 -07:00
Markus Elfring 34675d6703 clk: hi3620: Fix a typo in one variable name
The script "checkpatch.pl" pointed information out like the following.

CHECK: 'seperated' may be misspelled - perhaps 'separated'?

Thus rename the affected variable.

Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-04-19 11:29:49 -07:00
Markus Elfring 3cda284b77 clk: hi3620: Delete error messages for a failed memory allocation in two functions
The script "checkpatch.pl" pointed information out like the following.

WARNING: Possible unnecessary 'out of memory' message

Thus remove such statements here.

Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-04-19 11:28:04 -07:00
Markus Elfring 781de7ade6 clk: hi3620: Use kcalloc() in hi3620_mmc_clk_init()
* A multiplication for the size determination of a memory allocation
  indicated that an array data structure should be processed.
  Thus use the corresponding function "kcalloc".

  This issue was detected by using the Coccinelle software.

* Replace the specification of a data type by a pointer dereference
  to make the corresponding size determination a bit safer according to
  the Linux coding style convention.

Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-04-19 10:48:04 -07:00
Markus Elfring 840e56326f clk: hisilicon: Delete error messages for failed memory allocations in hisi_clk_init()
The script "checkpatch.pl" pointed information out like the following.

WARNING: Possible unnecessary 'out of memory' message

Thus remove such statements here.

Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-04-19 10:45:52 -07:00
Markus Elfring 8d9bdc46c7 clk: hisilicon: Use devm_kmalloc_array() in hisi_clk_alloc()
* A multiplication for the size determination of a memory allocation
  indicated that an array data structure should be processed.
  Thus use the corresponding function "devm_kmalloc_array".

  This issue was detected by using the Coccinelle software.

* Replace the specification of a data type by a pointer dereference
  to make the corresponding size determination a bit safer according to
  the Linux coding style convention.

Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-04-19 10:45:12 -07:00
Markus Elfring 7b9bae176a clk: hisilicon: Use kcalloc() in hisi_clk_init()
* A multiplication for the size determination of a memory allocation
  indicated that an array data structure should be processed.
  Thus use the corresponding function "kcalloc".

  This issue was detected by using the Coccinelle software.

* Replace the specification of a data type by a pointer dereference
  to make the corresponding size determination a bit safer according to
  the Linux coding style convention.

Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-04-19 10:20:14 -07:00
Kuninori Morimoto b3da896e2f clk: cs2000: select 12.20 High Accuracy on LFRatioCfg
cs2000 can select Static/Dynamic ratio based Frequency Synthesizer
Mode, it can select 20.12 High Multiplier interpret for 32-bit
User Defined Ratio if Dynamic ratio mode. Otherwise it should select
12.20 High Accuracy mode.
Current cs2000 is supporting Static ratio mode only, so it should
select 12.20 High Accuracy mode, not 20.12 High Multiplier mode.
This patch fixes it.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-04-19 10:18:55 -07:00
Kuninori Morimoto b295a015cd clk: cs2000: tidyup DEVICE_CFG2 settings
DEVICE_CFG2 can select ratio from user defined ratio and LOCKCLK is
for it. But current driver sets fixed 0 value. This patch fixes it.
Note is that current cs2000 driver is using/supporting only ratio0
(= ch0) now.

DEVICE_CFG2 can select STATIC/DYNAMIC ratio mode, and current cs2000
driver is selecting STATIC mode, but it was not understandable on
current code. This patch also solve this issue.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-04-19 10:18:53 -07:00
Kuninori Morimoto d127967a7b clk: cs2000: enable clock skipping mode
CLK_IN skipping mode allows the PLL to maintain lock even when the
CLK_IN signal has missing pulses for up to 20 ms (t CS) at a time.
This patch enables it

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-04-19 10:18:52 -07:00
Stanimir Varbanov 4a43e35d19 clk: qcom: add parent for venus core0 and core1 gdsc's
Make venus_gdsc parent of venus gdsc core0 and core1.

Signed-off-by: Stanimir Varbanov <stanimir.varbanov@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-04-19 09:55:58 -07:00
Pierre-Louis Bossart 41ee7caf59 clk: x86: add "mclk" alias for Baytrail/Cherrytrail
Due to timing requirements, TI and Conexant manage the audio
reference clock from their ASoC codec drivers using the "mclk"
string. This patch adds another lookup for the "pmc_plt_clk_3"
clock to avoid Intel-specific tests in those codec drivers and
use code as-is.

To avoid a leak, clk_add_alias() is not used in this patch.
Instead the lookup is created manually as part of the .probe()
step and dropped in the .remove() step.

"pmc_plt_clk_3" is used exclusively for audio on all known
Baytrail/CherryTrail designs and is e.g. routed on the MCLK
(pin 26) of the MinnowBoardMAX Turbot LSE connector.

Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-04-19 09:52:32 -07:00
Bharat Kumar Reddy Gooty 8973aa4aec clk: ns2: Correct SDIO bits
Corrected the bits for power and iso.

Signed-off-by: Bharat Kumar Reddy Gooty <bharat.gooty@broadcom.com>
Signed-off-by: Jon Mason <jon.mason@broadcom.com>
Fixes: f7225a83 ("clk: ns2: add clock support for Broadcom Northstar 2 SoC")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-04-19 09:50:39 -07:00
Srinivas Kandagatla 46a7253df4 clk: qcom: clk-smd-rpm: fix rate for branch clks during handoff
rpm branch clk rate should requested as either 0 or 1 but not INT_MAX.
This patch fixes rate request for branch clocks during clk handoff.

Suggested-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-04-19 09:50:26 -07:00
Stefan Agner e24f5287cd clk: imx7d: fix USDHC NAND clock
The USDHC NAND root clock is not gated by any CCM clock gate. Remove
the bogus gate definition.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Acked-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-04-19 09:44:14 -07:00
Thomas Petazzoni 1b21401307 clk: spear: fix ADC clock definition on SPEAr600
There is no SPEAr600 device named "adc". Instead, the description of the
ADC was recently added to the Device Tree, and the device name is
"d820b000.adc", so we should associate the ADC gatable clock to this
device name.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-04-19 09:27:52 -07:00
Kevin-CW Chen 96596aa066 clk: mediatek: add clk support for MT6797
Add MT6797 clock support, include topckgen, apmixedsys, infracfg
and subsystem clocks

Signed-off-by: Kevin-CW Chen <kevin-cw.chen@mediatek.com>
Signed-off-by: Mars Cheng <mars.cheng@mediatek.com>
Tested-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-04-19 09:20:21 -07:00
Dong Aisheng 40e00eff79 clk: imx7d: add the missing ipg_root_clk
Add the missing ipg_root_clk which actually is already used by many
orphan clks in current tree.

Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Stefan Agner <stefan@agner.ch>
Tested-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-04-19 09:10:23 -07:00
Dong Aisheng 9a6e904226 clk: clk-imx7d: fix ahb clk definition
MX7D ahb clk actually has no LPCG gate, current LPCG offset 0x4200
used actually is for adc, not ahb. After fix, correct ocram_s_clk
parent accordingly as well.

Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Stefan Agner <stefan@agner.ch>
Tested-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-04-19 09:10:12 -07:00
Alexey Firago 1193e14fdd clk: vc5: Add support for IDT VersaClock 5P49V5935
Update IDT VersaClock 5 driver to support 5P49V5935. This chip has
two clock inputs (internal XTAL or external CLKIN), four fractional
dividers (FODs) and five clock outputs (four universal clock outputs
and one reference clock output at OUT0_SELB_I2C).

Current driver supports up to 2 FODs and up to 3 clock outputs. This
patch sets max number of supported FODs to 4 and max number of supported
clock outputs to 5.

Signed-off-by: Alexey Firago <alexey_firago@mentor.com>
Reviewed-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-04-19 09:08:59 -07:00
Alexey Firago 9adddb01ce clk: vc5: Add structure to describe particular chip features
Introduce vc5_chip_info structure to describe features of a particular
VC5 chip (id, number of FODs, number of outputs, flags).
For now flags are only used to indicate if chip has internal XTAL.
vc5_chip_info is set on probe from the matched of_device_id->data.

Also add defines to specify maximum number of FODs and clock outputs
supported by the driver.

With these changes it should be easier to extend driver to support
more VC5 models.

Signed-off-by: Alexey Firago <alexey_firago@mentor.com>
Reviewed-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-04-19 09:08:29 -07:00
Stephen Boyd 8062b4aafc Allwinner clock patches for 4.12
Support for the new H5 SoC and the PRCM block found in a number of SoCs as
 well, plus the usual chunk of fixes and minor enhancements.
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Merge tag 'sunxi-clk-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-next

Pull Allwinner clock patches for 4.12 from Maxime Ripard:

Support for the new H5 SoC and the PRCM block found in a number of SoCs as
well, plus the usual chunk of fixes and minor enhancements.

* tag 'sunxi-clk-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  clk: sunxi-ng: Display index when clock registration fails
  clk: sunxi-ng: a33: Add offset and minimum value for DDR1 PLL N factor
  clk: sunxi-ng: a80: Remodel CPU cluster PLLs as N-type multiplier clocks
  clk: sunxi-ng: mult: Support PLL lock detection
  clk: sunxi-ng: add support for PRCM CCUs
  dt-bindings: update device tree binding for Allwinner PRCM CCUs
  clk: sunxi-ng: sun5i: Fix mux width for csi clock
  clk: sunxi-ng: tighten SoC deps on explicit AllWinner SoCs
  clk: sunxi-ng: add Allwinner H5 CCU support for H3 CCU driver
  clk: sunxi-ng: gate: Support common pre-dividers
2017-04-19 09:02:00 -07:00
Stephen Boyd e609f9f23e Merge branch 'clk-fixes' into clk-next
* clk-fixes:
  clk: sunxi-ng: a33: gate then ungate PLL CPU clk after rate change
  clk: sunxi-ng: Add clk notifier to gate then ungate PLL clocks
  clk: sunxi-ng: fix build failure in ccu-sun9i-a80 driver
  clk: sunxi-ng: fix build error without CONFIG_RESET_CONTROLLER
  clk: stm32f4: fix: exclude values 0 and 1 for PLLQ
2017-04-17 11:29:18 -07:00
Stephen Boyd e7590308d1 Allwinner clock fixes for 4.11
Two build errors fixes for the sunxi-ng drivers.
 
 The two other patches fix random CPU crashes happening on the A33 since
 CPUFreq has been enabled in 4.11.
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Merge tag 'sunxi-clk-fixes-for-4.11-2-bis' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-fixes

Pull Allwinner clock fixes for 4.11 from Maxime Ripard:

Two build errors fixes for the sunxi-ng drivers.

The two other patches fix random CPU crashes happening on the A33 since
CPUFreq has been enabled in 4.11.

* tag 'sunxi-clk-fixes-for-4.11-2-bis' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  clk: sunxi-ng: a33: gate then ungate PLL CPU clk after rate change
  clk: sunxi-ng: Add clk notifier to gate then ungate PLL clocks
  clk: sunxi-ng: fix build failure in ccu-sun9i-a80 driver
  clk: sunxi-ng: fix build error without CONFIG_RESET_CONTROLLER
2017-04-17 11:04:12 -07:00
Chen-Yu Tsai 7149c1becd clk: sunxi-ng: a80: Fix audio PLL comment not matching actual code
We ignore the d1 and d2 dividers in the audio PLL, and force them to
1 (register value 0) at probe time. However the comment preceding the
audio PLL definition says we enforce the default value, which is not
the same.

Fix the preceding comment to match what we do in code.

Fixes: b8eb71dcdd ("clk: sunxi-ng: Add A80 CCU")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-13 14:09:30 +02:00
Chen-Yu Tsai 95ad8ed9c8 clk: sunxi-ng: Fix round_rate/set_rate multiplier minimum mismatch
In commit 2beaa601c8 ("clk: sunxi-ng: Implement minimum for
multipliers"), the multiplier minimums in the set_rate callback
for NM and NKMP style clocks were not updated.

This patch fixes them to match their round_rate callbacks.

Fixes: 2beaa601c8 ("clk: sunxi-ng: Implement minimum for multipliers")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-13 14:09:28 +02:00
Chen-Yu Tsai 4162c5ce52 clk: sunxi-ng: use 1 as fallback for minimum multiplier
A zero multiplier does not make sense for clocks.

Use 1 as the minimum when a multiplier minimum isn't specified.

Fixes: 2beaa601c8 ("clk: sunxi-ng: Implement minimum for multipliers")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-13 14:09:25 +02:00
Chen-Yu Tsai 372fa10172 clk: sunxi-ng: a33: gate then ungate PLL CPU clk after rate change
This patch utilizes the new PLL clk notifier to gate then ungate the
PLL CPU clock after rate changes. This should mitigate the system
hangs observed after the introduction of cpufreq for the A33.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Tested-by: Quentin Schulz <quentin.schulz@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-13 11:22:04 +02:00