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Author SHA1 Message Date
Linus Torvalds c6ed444fd6 This is the bulk of pin control changes for v4.19: 
Core changes:
 
 - Augment pinctrl_generic_add_group() and pinmux_generic_add_function()
   to return the selector for the added group/function to the caller
   and augment (hopefully) all drivers to handle this.
 
 New subdrivers:
 
 - Qualcomm PM8998 and PM8005 are supported in the SPMI pin
   control and GPIO driver.
 
 - Intel Ice Lake PCH (platform controller hub) support.
 
 - NXP (ex Freescale) i.MX8MQ support.
 
 - Berlin AS370 support.
 
 Improvements to drivers:
 
 - Support interrupts on the Ocelot pin controller.
 
 - Add SPI pins to the Uniphier driver.
 
 - Define a GPIO compatible per SoC in the Tegra driver.
 
 - Push Tegra initialization down in the initlevels.
 
 - Support external wakeup interrupts on the Exynos.
 
 - Add generic clocks pins to the meson driver.
 
 - Add USB and HSCIF pins for some Renesas PFC chips.
 
 - Suspend/resume support in the armada-37xx.
 
 - Interrupt support for the Actions Semiconductor S900 also
   known as "owl".
 
 - Correct the pin ordering in Cedarfork.
 
 - Debugfs output for INTF in the mcp23s08 driver
 
 - Avoid divisions in context save/restore in pinctrl-single.
 
 The rest is minor bug fixes or cleanups.
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Merge tag 'pinctrl-v4.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij:
 "This is the bulk of pin control changes for v4.19:

  Core changes:

   - Augment pinctrl_generic_add_group() and pinmux_generic_add_function()
     to return the selector for the added group/function to the caller
     and augment (hopefully) all drivers to handle this

  New subdrivers:

   - Qualcomm PM8998 and PM8005 are supported in the SPMI pin control
     and GPIO driver

   - Intel Ice Lake PCH (platform controller hub) support

   - NXP (ex Freescale) i.MX8MQ support

   - Berlin AS370 support

  Improvements to drivers:

   - Support interrupts on the Ocelot pin controller

   - Add SPI pins to the Uniphier driver

   - Define a GPIO compatible per SoC in the Tegra driver

   - Push Tegra initialization down in the initlevels

   - Support external wakeup interrupts on the Exynos

   - Add generic clocks pins to the meson driver

   - Add USB and HSCIF pins for some Renesas PFC chips

   - Suspend/resume support in the armada-37xx

   - Interrupt support for the Actions Semiconductor S900 also known as
     "owl"

   - Correct the pin ordering in Cedarfork

   - Debugfs output for INTF in the mcp23s08 driver

   - Avoid divisions in context save/restore in pinctrl-single

  The rest is minor bug fixes or cleanups"

* tag 'pinctrl-v4.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (69 commits)
  pinctrl: nomadik: silence uninitialized variable warning
  pinctrl: axp209: Fix NULL pointer dereference after allocation
  pinctrl: samsung: Remove duplicated "wakeup" in printk
  pinctrl: ocelot: add support for interrupt controller
  pinctrl: intel: Don't shadow error code of gpiochip_lock_as_irq()
  pinctrl: berlin: fix 'pctrl->functions' allocation in berlin_pinctrl_build_state
  gpio: tegra: Move driver registration to subsys_init level
  pinctrl: tegra: Move drivers registration to arch_init level
  pinctrl: baytrail: actually print the apparently misconfigured pin
  MAINTAINERS: Replace Heikki as maintainer of Intel pinctrl
  pinctrl: freescale: off by one in imx1_pinconf_group_dbg_show()
  pinctrl: uniphier: add spi pin-mux settings
  pinctrl: cannonlake: Fix community ordering for H variant
  pinctrl: tegra: define GPIO compatible node per SoC
  pinctrl: intel: Do pin translation when lock IRQ
  pinctrl: imx: off by one in imx_pinconf_group_dbg_show()
  pinctrl: mediatek: include chained_irq.h header
  pinctrl/amd: only handle irq if it is pending and unmasked
  pinctrl/amd: fix gpio irq level in debugfs
  pinctrl: stm32: add syscfg mask parameter
  ...
 2018-08-14 12:31:27 -07:00
Takeshi Kihara a35f5c1ac2 pinctrl: sh-pfc: r8a77990: Add USB3.0 pins, groups and functions 
This patch adds USB30_{PWEN,OVC} and USB3HS0_ID pins, groups and functions
to the R8A77990 SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2018-07-16 14:46:38 +02:00
Takeshi Kihara d7b535f99b pinctrl: sh-pfc: r8a77990: Add USB2.0 pins, groups and functions 
This patch adds USB0_{PWEN,OVC}_{A,B} and USB0_ID pins, groups and
functions to the R8A77990 SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2018-07-16 14:46:31 +02:00
Yoshihiro Shimoda 747c541782 pinctrl: sh-pfc: r8a77990: Revise USB ID pin name 
Since the datasheet Rev.1.00 has an error about the USB ID pin name,
this patch revises it.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2018-07-16 14:46:27 +02:00
Takeshi Kihara 7628fa811b pinctrl: sh-pfc: r8a77965: Add HSCIF pins, groups, and functions 
This patch adds HSCIF{0,1,2,3,4} pins, groups and functions to
the R8A77965 SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2018-07-16 14:46:11 +02:00
Niklas Söderlund 550b6f7e8c pinctrl: sh-pfc: r8a77970: remove SH_PFC_PIN_CFG_DRIVE_STRENGTH flag 
The datasheet does not document any registers to control drive strength,
and no drive strength registers are for this reason described for this
SoC. The flags indicating that drive strength can be controlled are
however set for some pins in the driver.

This leads to a NULL pointer dereference when the sh-pfc core tries to
access the struct describing the drive strength registers, for example
when reading the sysfs file pinconf-pins.

Fix this by removing the SH_PFC_PIN_CFG_DRIVE_STRENGTH from all pins.

Fixes: b92ac66a18 ("pinctrl: sh-pfc: Add R8A77970 PFC support")
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2018-07-14 12:47:04 +02:00
Kees Cook a86854d0c5 treewide: devm_kzalloc() -> devm_kcalloc() 
The devm_kzalloc() function has a 2-factor argument form, devm_kcalloc().
This patch replaces cases of:

        devm_kzalloc(handle, a * b, gfp)

with:
        devm_kcalloc(handle, a * b, gfp)

as well as handling cases of:

        devm_kzalloc(handle, a * b * c, gfp)

with:

        devm_kzalloc(handle, array3_size(a, b, c), gfp)

as it's slightly less ugly than:

        devm_kcalloc(handle, array_size(a, b), c, gfp)

This does, however, attempt to ignore constant size factors like:

        devm_kzalloc(handle, 4 * 1024, gfp)

though any constants defined via macros get caught up in the conversion.

Any factors with a sizeof() of "unsigned char", "char", and "u8" were
dropped, since they're redundant.

Some manual whitespace fixes were needed in this patch, as Coccinelle
really liked to write "=devm_kcalloc..." instead of "= devm_kcalloc...".

The Coccinelle script used for this was:

// Fix redundant parens around sizeof().
@@
expression HANDLE;
type TYPE;
expression THING, E;
@@

(
  devm_kzalloc(HANDLE,
-	(sizeof(TYPE)) * E
+	sizeof(TYPE) * E
  , ...)
|
  devm_kzalloc(HANDLE,
-	(sizeof(THING)) * E
+	sizeof(THING) * E
  , ...)
)

// Drop single-byte sizes and redundant parens.
@@
expression HANDLE;
expression COUNT;
typedef u8;
typedef __u8;
@@

(
  devm_kzalloc(HANDLE,
-	sizeof(u8) * (COUNT)
+	COUNT
  , ...)
|
  devm_kzalloc(HANDLE,
-	sizeof(__u8) * (COUNT)
+	COUNT
  , ...)
|
  devm_kzalloc(HANDLE,
-	sizeof(char) * (COUNT)
+	COUNT
  , ...)
|
  devm_kzalloc(HANDLE,
-	sizeof(unsigned char) * (COUNT)
+	COUNT
  , ...)
|
  devm_kzalloc(HANDLE,
-	sizeof(u8) * COUNT
+	COUNT
  , ...)
|
  devm_kzalloc(HANDLE,
-	sizeof(__u8) * COUNT
+	COUNT
  , ...)
|
  devm_kzalloc(HANDLE,
-	sizeof(char) * COUNT
+	COUNT
  , ...)
|
  devm_kzalloc(HANDLE,
-	sizeof(unsigned char) * COUNT
+	COUNT
  , ...)
)

// 2-factor product with sizeof(type/expression) and identifier or constant.
@@
expression HANDLE;
type TYPE;
expression THING;
identifier COUNT_ID;
constant COUNT_CONST;
@@

(
- devm_kzalloc
+ devm_kcalloc
  (HANDLE,
-	sizeof(TYPE) * (COUNT_ID)
+	COUNT_ID, sizeof(TYPE)
  , ...)
|
- devm_kzalloc
+ devm_kcalloc
  (HANDLE,
-	sizeof(TYPE) * COUNT_ID
+	COUNT_ID, sizeof(TYPE)
  , ...)
|
- devm_kzalloc
+ devm_kcalloc
  (HANDLE,
-	sizeof(TYPE) * (COUNT_CONST)
+	COUNT_CONST, sizeof(TYPE)
  , ...)
|
- devm_kzalloc
+ devm_kcalloc
  (HANDLE,
-	sizeof(TYPE) * COUNT_CONST
+	COUNT_CONST, sizeof(TYPE)
  , ...)
|
- devm_kzalloc
+ devm_kcalloc
  (HANDLE,
-	sizeof(THING) * (COUNT_ID)
+	COUNT_ID, sizeof(THING)
  , ...)
|
- devm_kzalloc
+ devm_kcalloc
  (HANDLE,
-	sizeof(THING) * COUNT_ID
+	COUNT_ID, sizeof(THING)
  , ...)
|
- devm_kzalloc
+ devm_kcalloc
  (HANDLE,
-	sizeof(THING) * (COUNT_CONST)
+	COUNT_CONST, sizeof(THING)
  , ...)
|
- devm_kzalloc
+ devm_kcalloc
  (HANDLE,
-	sizeof(THING) * COUNT_CONST
+	COUNT_CONST, sizeof(THING)
  , ...)
)

// 2-factor product, only identifiers.
@@
expression HANDLE;
identifier SIZE, COUNT;
@@

- devm_kzalloc
+ devm_kcalloc
  (HANDLE,
-	SIZE * COUNT
+	COUNT, SIZE
  , ...)

// 3-factor product with 1 sizeof(type) or sizeof(expression), with
// redundant parens removed.
@@
expression HANDLE;
expression THING;
identifier STRIDE, COUNT;
type TYPE;
@@

(
  devm_kzalloc(HANDLE,
-	sizeof(TYPE) * (COUNT) * (STRIDE)
+	array3_size(COUNT, STRIDE, sizeof(TYPE))
  , ...)
|
  devm_kzalloc(HANDLE,
-	sizeof(TYPE) * (COUNT) * STRIDE
+	array3_size(COUNT, STRIDE, sizeof(TYPE))
  , ...)
|
  devm_kzalloc(HANDLE,
-	sizeof(TYPE) * COUNT * (STRIDE)
+	array3_size(COUNT, STRIDE, sizeof(TYPE))
  , ...)
|
  devm_kzalloc(HANDLE,
-	sizeof(TYPE) * COUNT * STRIDE
+	array3_size(COUNT, STRIDE, sizeof(TYPE))
  , ...)
|
  devm_kzalloc(HANDLE,
-	sizeof(THING) * (COUNT) * (STRIDE)
+	array3_size(COUNT, STRIDE, sizeof(THING))
  , ...)
|
  devm_kzalloc(HANDLE,
-	sizeof(THING) * (COUNT) * STRIDE
+	array3_size(COUNT, STRIDE, sizeof(THING))
  , ...)
|
  devm_kzalloc(HANDLE,
-	sizeof(THING) * COUNT * (STRIDE)
+	array3_size(COUNT, STRIDE, sizeof(THING))
  , ...)
|
  devm_kzalloc(HANDLE,
-	sizeof(THING) * COUNT * STRIDE
+	array3_size(COUNT, STRIDE, sizeof(THING))
  , ...)
)

// 3-factor product with 2 sizeof(variable), with redundant parens removed.
@@
expression HANDLE;
expression THING1, THING2;
identifier COUNT;
type TYPE1, TYPE2;
@@

(
  devm_kzalloc(HANDLE,
-	sizeof(TYPE1) * sizeof(TYPE2) * COUNT
+	array3_size(COUNT, sizeof(TYPE1), sizeof(TYPE2))
  , ...)
|
  devm_kzalloc(HANDLE,
-	sizeof(TYPE1) * sizeof(THING2) * (COUNT)
+	array3_size(COUNT, sizeof(TYPE1), sizeof(TYPE2))
  , ...)
|
  devm_kzalloc(HANDLE,
-	sizeof(THING1) * sizeof(THING2) * COUNT
+	array3_size(COUNT, sizeof(THING1), sizeof(THING2))
  , ...)
|
  devm_kzalloc(HANDLE,
-	sizeof(THING1) * sizeof(THING2) * (COUNT)
+	array3_size(COUNT, sizeof(THING1), sizeof(THING2))
  , ...)
|
  devm_kzalloc(HANDLE,
-	sizeof(TYPE1) * sizeof(THING2) * COUNT
+	array3_size(COUNT, sizeof(TYPE1), sizeof(THING2))
  , ...)
|
  devm_kzalloc(HANDLE,
-	sizeof(TYPE1) * sizeof(THING2) * (COUNT)
+	array3_size(COUNT, sizeof(TYPE1), sizeof(THING2))
  , ...)
)

// 3-factor product, only identifiers, with redundant parens removed.
@@
expression HANDLE;
identifier STRIDE, SIZE, COUNT;
@@

(
  devm_kzalloc(HANDLE,
-	(COUNT) * STRIDE * SIZE
+	array3_size(COUNT, STRIDE, SIZE)
  , ...)
|
  devm_kzalloc(HANDLE,
-	COUNT * (STRIDE) * SIZE
+	array3_size(COUNT, STRIDE, SIZE)
  , ...)
|
  devm_kzalloc(HANDLE,
-	COUNT * STRIDE * (SIZE)
+	array3_size(COUNT, STRIDE, SIZE)
  , ...)
|
  devm_kzalloc(HANDLE,
-	(COUNT) * (STRIDE) * SIZE
+	array3_size(COUNT, STRIDE, SIZE)
  , ...)
|
  devm_kzalloc(HANDLE,
-	COUNT * (STRIDE) * (SIZE)
+	array3_size(COUNT, STRIDE, SIZE)
  , ...)
|
  devm_kzalloc(HANDLE,
-	(COUNT) * STRIDE * (SIZE)
+	array3_size(COUNT, STRIDE, SIZE)
  , ...)
|
  devm_kzalloc(HANDLE,
-	(COUNT) * (STRIDE) * (SIZE)
+	array3_size(COUNT, STRIDE, SIZE)
  , ...)
|
  devm_kzalloc(HANDLE,
-	COUNT * STRIDE * SIZE
+	array3_size(COUNT, STRIDE, SIZE)
  , ...)
)

// Any remaining multi-factor products, first at least 3-factor products,
// when they're not all constants...
@@
expression HANDLE;
expression E1, E2, E3;
constant C1, C2, C3;
@@

(
  devm_kzalloc(HANDLE, C1 * C2 * C3, ...)
|
  devm_kzalloc(HANDLE,
-	(E1) * E2 * E3
+	array3_size(E1, E2, E3)
  , ...)
|
  devm_kzalloc(HANDLE,
-	(E1) * (E2) * E3
+	array3_size(E1, E2, E3)
  , ...)
|
  devm_kzalloc(HANDLE,
-	(E1) * (E2) * (E3)
+	array3_size(E1, E2, E3)
  , ...)
|
  devm_kzalloc(HANDLE,
-	E1 * E2 * E3
+	array3_size(E1, E2, E3)
  , ...)
)

// And then all remaining 2 factors products when they're not all constants,
// keeping sizeof() as the second factor argument.
@@
expression HANDLE;
expression THING, E1, E2;
type TYPE;
constant C1, C2, C3;
@@

(
  devm_kzalloc(HANDLE, sizeof(THING) * C2, ...)
|
  devm_kzalloc(HANDLE, sizeof(TYPE) * C2, ...)
|
  devm_kzalloc(HANDLE, C1 * C2 * C3, ...)
|
  devm_kzalloc(HANDLE, C1 * C2, ...)
|
- devm_kzalloc
+ devm_kcalloc
  (HANDLE,
-	sizeof(TYPE) * (E2)
+	E2, sizeof(TYPE)
  , ...)
|
- devm_kzalloc
+ devm_kcalloc
  (HANDLE,
-	sizeof(TYPE) * E2
+	E2, sizeof(TYPE)
  , ...)
|
- devm_kzalloc
+ devm_kcalloc
  (HANDLE,
-	sizeof(THING) * (E2)
+	E2, sizeof(THING)
  , ...)
|
- devm_kzalloc
+ devm_kcalloc
  (HANDLE,
-	sizeof(THING) * E2
+	E2, sizeof(THING)
  , ...)
|
- devm_kzalloc
+ devm_kcalloc
  (HANDLE,
-	(E1) * E2
+	E1, E2
  , ...)
|
- devm_kzalloc
+ devm_kcalloc
  (HANDLE,
-	(E1) * (E2)
+	E1, E2
  , ...)
|
- devm_kzalloc
+ devm_kcalloc
  (HANDLE,
-	E1 * E2
+	E1, E2
  , ...)
)

Signed-off-by: Kees Cook <keescook@chromium.org>
 2018-06-12 16:19:22 -07:00
Geert Uytterhoeven db701f4bea pinctrl: sh-pfc: rcar-gen3: Fix grammar in static pin comments 
The comment block explaining the rationale for static pins contains
grammar errors.  It appeared first in the pin control driver for R-Car
H3 ES1.x, and spread to R-Car M3-W, H3 ES2.0, and M3-N later.

Fix the grammar in all copies at once.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
 2018-05-23 14:43:49 +02:00
Niklas Söderlund 82540ebcc7 pinctrl: sh-pfc: r8a77965: Add I2C pin support 
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2018-05-23 14:43:49 +02:00
Takeshi Kihara 7cf9733f69 pinctrl: sh-pfc: r8a77990: Add EthernetAVB pins, groups and functions 
This patch adds group and function of AVB PHY, LINK, MAGIC, MII and PTP
pins for the R8A77990 SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2018-05-23 14:43:32 +02:00
Takeshi Kihara 33f8dadc27 pinctrl: sh-pfc: r8a77990: Add I2C{1,2,4,5,6,7} pins, groups and functions 
This patch adds I2C{1,2,4,5,6,7} pins, groups and functions to
the R8A77990 SoC.

NOTE: I2C0 and I2C3 are not pin multiplexed.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2018-05-23 14:43:32 +02:00
Takeshi Kihara 6d3789e705 pinctrl: sh-pfc: r8a77990: Add SCIF pins, groups and functions 
This patch adds SCIF{0,1,2,3,4,5} pins, groups and functions to R8A77990
SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2018-05-23 14:43:32 +02:00
Takeshi Kihara 83f6941a42 pinctrl: sh-pfc: r8a77990: Add bias pinconf support 
This patch implements control of pull-up and pull-down. On this SoC there
is no simple mapping of GP pins to bias register bits, so we need a table.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2018-05-23 14:43:32 +02:00
Takeshi Kihara 6d4036a1e3 pinctrl: sh-pfc: Initial R8A77990 PFC support 
This patch adds initial pinctrl driver to support for the R8A77990 SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2018-05-23 14:43:32 +02:00
Takeshi Kihara ec96db5868 pinctrl: sh-pfc: Add PORT_GP_11 helper macro 
This follows the style of existion PORT_GP_X macros and
will be used by a follow-up patch for the r8a77990 SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2018-05-23 14:43:32 +02:00
Biju Das 73dacc3403 pinctrl: sh-pfc: Add r8a77470 PFC support 
Add PFC support for the R8A77470 SoC including pin groups for
some on-chip devices such as SCIF and MMC.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2018-05-16 13:32:15 +02:00
Takeshi Kihara 16688c8b86 pinctrl: sh-pfc: r8a77965: Add SDHI pins, groups and functions 
This patch adds SDHI{0,1,2,3} pins, groups and functions to the R8A77965
SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Tested-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2018-05-16 13:32:06 +02:00
Kieran Bingham a73ab128c3 pinctrl: sh-pfc: r8a77965: Add DU RGB output pins, groups and functions 
This patch adds pins, groups and functions for parallel RGB output
signals from DU. The HDMI and TCON pins are added to separate groups.

Based on a similar patch of the R8A7796 PFC driver by Niklas Söderlund
<niklas.soderlund+renesas@ragnatech.se>.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[Kieran: Rebase on top of tree]
Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2018-05-16 13:31:53 +02:00
Thomas Gleixner 3a4d17457d pinctrl: sh-pfc: r8a77965: Fixup incorrect SPDX identifier 
GPL-2. is not a valid SPDX identifier. Make it GPL-2.0

Fixes: 490e687eb8 ("pinctrl: sh-pfc: Initial R-Car M3-N support")
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Jacopo Mondi <jacopo+renesas@jmondi.org>
Cc: Rob Herring <robh@kernel.org>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2018-05-16 13:31:46 +02:00
Sergei Shtylyov f9931a4d87 pinctrl: sh-pfc: r8a77970: Fix pin I/O voltage control support 
I've included the pin I/O voltage control into the R8A77970 PFC driver but
it was incomplete because:
- SH_PFC_PIN_CFG_IO_VOLTAGE pin flags weren't set properly;
- sh_pfc_soc_info::ioctrl_regs wasn't set at all...

Fixes: b92ac66a18 ("pinctrl: sh-pfc: Add R8A77970 PFC support")
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2018-05-16 13:31:42 +02:00
Sergei Shtylyov b374c90f0a pinctrl: sh-pfc: r8a77980: Add pin I/O voltage control support 
Add the pin I/O voltage level control support to the R8A77980 PFC driver.

Loosely based on the original (and large) patch by Vladimir Barinov.

Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2018-05-16 13:31:38 +02:00
Takeshi Kihara 54b7f2da97 pinctrl: sh-pfc: r8a77965: Add PWM pins, groups and functions 
This patch adds PWM{0,1,2,3,4,5,6} pins, groups and functions to
R8A77965 SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2018-05-16 13:31:31 +02:00
Geert Uytterhoeven fff8e331ef pinctrl: sh-pfc: r8a7796: Fix comment for MSIOF3 SS2_E pin 
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2018-05-16 13:31:27 +02:00
Geert Uytterhoeven 3788051285 pinctrl: sh-pfc: r8a7795: Fix comment for MSIOF3 SS2_E pin 
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2018-05-16 13:31:23 +02:00
Takeshi Kihara 2c77aa3d70 pinctrl: sh-pfc: r8a77965: Add MSIOF pins, groups and functions 
This patch adds MSIOF{0,1,2,3} pins, groups and functions to the
R8A77965 SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[geert: Correct MSIOF3 SS2_E comment]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2018-05-16 13:31:02 +02:00
Linus Torvalds 77624cd2a7 Pin control bulk changes for the v4.17 kernel cycle: 
New drivers:
 
 - Qualcomm SDM845: this is their new flagship SoC platform
   which seems to be targeted at premium mobile handsets.
 
 - Renesas R-Car M3-N SoC.
 
 - Renesas R8A77980 SoC.
 
 - NXP (ex Freescale) i.MX 6SLL SoC.
 
 - Mediatek MT2712 SoC.
 
 - Allwinner H6 SoC.
 
 Improvements:
 
 - Uniphier adds a few new functions and pins.
 
 - Renesas refactorings and additional pin definitions.
 
 - Improved pin groups for Axis Artpec6.
 
 Cleanup:
 
 - Drop the TZ1090 drivers. This platform is no longer
   maintained and is being deleted.
 
 - Drop ST-Ericsson U8540/U9540 support as this was never
   productified.
 
 - Overall minor fixes and janitorial.
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Merge tag 'pinctrl-v4.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control bulk updates from Linus Walleij:
 "New drivers:

   - Qualcomm SDM845: this is their new flagship SoC platform which
     seems to be targeted at premium mobile handsets.

   - Renesas R-Car M3-N SoC.

   - Renesas R8A77980 SoC.

   - NXP (ex Freescale) i.MX 6SLL SoC.

   - Mediatek MT2712 SoC.

   - Allwinner H6 SoC.

  Improvements:

   - Uniphier adds a few new functions and pins.

   - Renesas refactorings and additional pin definitions.

   - Improved pin groups for Axis Artpec6.

  Cleanup:

   - Drop the TZ1090 drivers. This platform is no longer maintained and
     is being deleted.

   - Drop ST-Ericsson U8540/U9540 support as this was never
     productified.

   - Overall minor fixes and janitorial"

* tag 'pinctrl-v4.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (82 commits)
  pinctrl: uniphier: add UART hardware flow control pin-mux settings
  pinctrl: sunxi: add support for the Allwinner H6 main pin controller
  pinctrl: sunxi: change irq_bank_base to irq_bank_map
  pinctrl: sunxi: introduce IRQ bank conversion function
  pinctrl: sunxi: refactor irq related register function to have desc
  pinctrl: msm8998: Remove owner assignment from platform_driver
  pinctrl: uniphier: divide I2S and S/PDIF audio out pin-mux group
  pinctrl: uniphier: add PXs2 Audio in/out pin-mux settings
  pinctrl/amd: poll InterruptEnable bits in enable_irq
  pinctrl: ocelot: fix gpio direction
  pinctrl: mtk: fix check warnings.
  pintcrl: mtk: support bias-disable of generic and special pins simultaneously
  pinctrl: add mt2712 pinctrl driver
  pinctrl: pinctrl-single: Fix pcs_request_gpio() when bits_per_mux != 0
  pinctrl: imx: Add pinctrl driver support for imx6sll
  dt-bindings: imx: update pinctrl doc for imx6sll
  pinctrl: intel: Implement intel_gpio_get_direction callback
  pinctrl: stm32: add 'depends on HAS_IOMEM' to fix unmet dependency
  pinctrl: mediatek: mtk-common: use true and false for boolean values
  pinctrl: sunxi: always look for apb block
  ...
 2018-04-03 12:20:54 -07:00
Ulrich Hecht a6fff41f41 pinctrl: sh-pfc: r8a77995: Deduplicate VIN4 pin definitions 
Use union vin_data and VIN_DATA_PIN_GROUP() to reduce redundancies
in pin definitions.

Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2018-03-21 18:25:48 +01:00
Ulrich Hecht a5c2949ff7 pinctrl: sh-pfc: r8a7796: Deduplicate VIN4 pin definitions 
Use union vin_data and VIN_DATA_PIN_GROUP() to reduce redundancies
in pin definitions.

Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2018-03-21 18:25:48 +01:00
Ulrich Hecht 9942a5b529 pinctrl: sh-pfc: r8a7795: Deduplicate VIN4 pin definitions 
Use union vin_data and VIN_DATA_PIN_GROUP() to reduce redundancies
in pin definitions.

Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2018-03-21 18:25:47 +01:00
Ulrich Hecht 4fd82963e1 pinctrl: sh-pfc: r8a77995: Correct VIN4 18-bit pins 
RGB666 has a pin assignment that differs from the other formats.

Fixes: fbd452aeb4 ("pinctrl: sh-pfc: r8a77995: Add VIN4 pins, groups and function")
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2018-03-21 18:25:22 +01:00
Ulrich Hecht a66b68ba7f pinctrl: sh-pfc: r8a7796: Correct VIN4 18-bit pins 
RGB666 has a pin assignment that differs from the other formats.

Fixes: 8db6cbabac ("pinctrl: sh-pfc: r8a7796: Add VIN4, VIN5 pins, groups and functions")
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2018-03-21 18:25:01 +01:00
Ulrich Hecht b538dc5bbb pinctrl: sh-pfc: r8a7795: Correct VIN4 18-bit pins 
RGB666 has a pin assignment that differs from the other formats.

Fixes: 6b4de40810 ("pinctrl: sh-pfc: r8a7795: Add VIN4, VIN5 pins, groups and functions")
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2018-03-21 18:24:16 +01:00
Geert Uytterhoeven 3b047a9597 pinctrl: sh-pfc: r8a77995: Rename EtherAVB "mdc" pin group to "mdio" 
On other Renesas SoCs, the pin group for the MDIO bus is named "mdio"
instead of "mdc".  Fix the inconsistency, while retaining backwards
compatibility with old DTBs using a pin group alias.

Fixes: 66abd968d0 ("pinctrl: sh-pfc: r8a77995: Add EthernetAVB pins, groups and functions")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
 2018-03-21 18:18:32 +01:00
Geert Uytterhoeven f7ce295cfd pinctrl: sh-pfc: r8a77965: Rename EtherAVB "mdc" pin group to "mdio" 
On other Renesas SoCs, the pin group for the MDIO bus is named "mdio"
instead of "mdc".  Fix the inconsistency, while retaining backwards
compatibility with old DTBs using a pin group alias.

Fixes: fa3e8b71b9 ("pinctrl: sh-pfc: r8a77965: Add EtherAVB groups/functions")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
 2018-03-21 18:18:30 +01:00
Geert Uytterhoeven 350aba9a74 pinctrl: sh-pfc: r8a7796: Rename EtherAVB "mdc" pin group to "mdio" 
On other Renesas SoCs, the pin group for the MDIO bus is named "mdio"
instead of "mdc".  Fix the inconsistency, while retaining backwards
compatibility with old DTBs using a pin group alias.

Fixes: 41397032c4 ("pinctrl: sh-pfc: r8a7796: Add group for AVB MDIO and MII pins")
Fixes: 9c99a63ec7 ("pinctrl: sh-pfc: r8a7796: Add EtherAVB pins, groups and functions")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
 2018-03-21 18:18:25 +01:00
Geert Uytterhoeven 24cfe1a970 pinctrl: sh-pfc: r8a7795-es1: Rename EtherAVB "mdc" pin group to "mdio" 
On other Renesas SoCs, the pin group for the MDIO bus is named "mdio"
instead of "mdc".  Fix the inconsistency, while retaining backwards
compatibility with old DTBs using a pin group alias.

Fixes: b25719eb93 ("pinctrl: sh-pfc: r8a7795: Add group for AVB MDIO and MII pins")
Fixes: 819fd4bfcc ("pinctrl: sh-pfc: r8a7795: add EtherAVB support")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
 2018-03-21 18:18:23 +01:00
Geert Uytterhoeven cbe0dd9ad5 pinctrl: sh-pfc: r8a7795: Rename EtherAVB "mdc" pin group to "mdio" 
On other Renesas SoCs, the pin group for the MDIO bus is named "mdio"
instead of "mdc".  Fix the inconsistency, while retaining backwards
compatibility with old DTBs using a pin group alias.

Fixes: 30c078de6f ("pinctrl: sh-pfc: r8a7795: Add EtherAVB pins, groups and function")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
 2018-03-21 18:18:18 +01:00
Geert Uytterhoeven 43a51cd5d6 pinctrl: sh-pfc: Add SH_PFC_PIN_GROUP_ALIAS() 
Add a macro to refer to another pin group with a different name.

This will be used to rename wrongly-named pin groups, while retaining
backwards compatibility with old DTBs.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
 2018-03-21 18:18:05 +01:00
Geert Uytterhoeven 66e9fe1ec7 pinctrl: sh-pfc: r8a7790: Add missing TX_ER pin to avb_mii group 
The pin controller drivers for all R-Car Gen2 SoCs have entries for the
EtherAVB TX_ER pins in their EtherAVB MII groups, except on R-Car H2.

Add the missing pin to restore consistency.

Note that technically TX_ER is an optional signal in the MII bus, and
thus could have its own group, but this is currently not supported by
any R-Car Gen2 pin controller driver.

Fixes: 19ef697d1e ("sh-pfc: r8a7790: add EtherAVB pin groups")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
 2018-03-21 18:16:51 +01:00
Sergei Shtylyov b3cbd8a567 pinctrl: sh-pfc: r8a77970: Add EtherAVB pin groups 
Add the EtherAVB pin groups to the R8A77970 PFC driver.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2018-03-14 14:39:52 +01:00
Sergei Shtylyov f59125248a pinctrl: sh-pfc: Add R8A77980 PFC support 
Add the PFC support for the R8A77980 SoC including pin groups for some
on-chip devices such as AVB, CAN-FD, GETHER, [H]SCIF, I2C, INTC-EX, MMC,
MSIOF, PWM, and VIN...

Based on the original (and large) patch by Vladimir Barinov.

Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2018-03-09 13:55:30 +01:00
Sergei Shtylyov c21a3e30e8 pinctrl: sh-pfc: Add PORT_GP_CFG_25() helper macro 
They follow the style of the existing PORT_GP_CFG_<n>() macros and
will be used by a follow-up patch for the R8A77980 SoC.

Based on the original (and large) patch by Vladimir Barinov.

Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2018-03-09 13:55:26 +01:00
Niklas Söderlund 625504aeff pinctrl: sh-pfc: r8a7795: remove duplicate of CLKOUT pin in pinmux_pins[] 
When adding GP-1-28 port pin support it was forgotten to remove the
CLKOUT pin from the list of pins that are not associated with a GPIO
port in pinmux_pins[]. This results in a warning when reading the
pinctrl files in sysfs as the CLKOUT pin is still added as a none GPIO
pin. Fix this by removing the duplicated entry which is no longer
needed.

~ # cat /sys/kernel/debug/pinctrl/e6060000.pin-controller/pinconf-pins
[   89.432081] ------------[ cut here ]------------
[   89.436904] Pin 496 is not in bias info list
[   89.441252] WARNING: CPU: 1 PID: 456 at drivers/pinctrl/sh-pfc/core.c:408 sh_pfc_pin_to_bias_reg+0xb0/0xb8
[   89.451002] CPU: 1 PID: 456 Comm: cat Not tainted 4.16.0-rc1-arm64-renesas-00048-gdfafc344a4f24dde #12
[   89.460394] Hardware name: Renesas Salvator-X 2nd version board based on r8a7795 ES2.0+ (DT)
[   89.468910] pstate: 80000085 (Nzcv daIf -PAN -UAO)
[   89.473747] pc : sh_pfc_pin_to_bias_reg+0xb0/0xb8
[   89.478495] lr : sh_pfc_pin_to_bias_reg+0xb0/0xb8
[   89.483241] sp : ffff00000aff3ab0
[   89.486587] x29: ffff00000aff3ab0 x28: ffff00000893c698
[   89.491955] x27: ffff000008ad7d98 x26: 0000000000000000
[   89.497323] x25: ffff8006fb3f5028 x24: ffff8006fb3f5018
[   89.502690] x23: 0000000000000001 x22: 00000000000001f0
[   89.508057] x21: ffff8006fb3f5018 x20: ffff000008bef000
[   89.513423] x19: 0000000000000000 x18: ffffffffffffffff
[   89.518790] x17: 0000000000006c4a x16: ffff000008d67c98
[   89.524157] x15: 0000000000000001 x14: ffff00000896ca98
[   89.529524] x13: 00000000cce5f611 x12: ffff8006f8d3b5a8
[   89.534891] x11: ffff00000981e000 x10: ffff000008befa08
[   89.540258] x9 : ffff8006f9b987a0 x8 : ffff000008befa08
[   89.545625] x7 : ffff000008137094 x6 : 0000000000000000
[   89.550991] x5 : 0000000000000000 x4 : 0000000000000001
[   89.556357] x3 : 0000000000000007 x2 : 0000000000000007
[   89.561723] x1 : 1ff24f80f1818600 x0 : 0000000000000000
[   89.567091] Call trace:
[   89.569561]  sh_pfc_pin_to_bias_reg+0xb0/0xb8
[   89.573960]  r8a7795_pinmux_get_bias+0x30/0xc0
[   89.578445]  sh_pfc_pinconf_get+0x1e0/0x2d8
[   89.582669]  pin_config_get_for_pin+0x20/0x30
[   89.587067]  pinconf_generic_dump_one+0x180/0x1c8
[   89.591815]  pinconf_generic_dump_pins+0x84/0xd8
[   89.596476]  pinconf_pins_show+0xc8/0x130
[   89.600528]  seq_read+0xe4/0x510
[   89.603789]  full_proxy_read+0x60/0x90
[   89.607576]  __vfs_read+0x30/0x140
[   89.611010]  vfs_read+0x90/0x170
[   89.614269]  SyS_read+0x60/0xd8
[   89.617443]  __sys_trace_return+0x0/0x4
[   89.621314] ---[ end trace 99c8d0d39c13e794 ]---

Fixes: 82d2de5a4f ("pinctrl: sh-pfc: r8a7795: Add GP-1-28 port pin support")
Reviewed-and-tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2018-03-08 13:02:01 +01:00
Takeshi Kihara c490b28f36 pinctrl: sh-pfc: r8a77965: Add USB3.0 host pins, groups and functions 
This patch adds USB30 (USB3.0 host) pin, group and function to
the R8A77965 SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2018-03-05 11:03:47 +01:00
Takeshi Kihara 0d75f8dae3 pinctrl: sh-pfc: r8a77965: Add USB2.0 host pins, groups and functions 
This patch adds USB{0,1} (USB2.0 host) pins, groups and functions to
the R8A77965 SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2018-03-05 11:02:32 +01:00
Takeshi Kihara a8ab4f2bd8 pinctrl: sh-pfc: r8a77965: Add support for INTC-EX IRQ pins 
Most pins on the R8A77965 SoC can be configured in GPIO mode for
interrupt and GPIO functionality, while a couple of them can also
be routed to the INTC-EX hardware block (formerly known as IRQC).

On R8A77965 the INTC-EX hardware handles pins IRQ0 -> IRQ5 and
this patch adds support for them to the PFC driver as "intc_ex_irqN".

Based on a similar patch for the R8A7795 PFC driver by Magnus Damm
<damm+renesas@opensource.se>.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2018-02-28 09:17:54 +01:00
Ulrich Hecht fbd452aeb4 pinctrl: sh-pfc: r8a77995: Add VIN4 pins, groups and function 
This patch adds VIN4 pins, groups and function for the
R8A77995 (D3) SoC.

Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2018-02-26 10:19:03 +01:00
Ulrich Hecht 6b4de40810 pinctrl: sh-pfc: r8a7795: Add VIN4, VIN5 pins, groups and functions 
This patch adds VIN4 and VIN5 pins, groups and functions for the
R8A7795 SoC.

Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2018-02-26 10:19:03 +01:00
Ulrich Hecht 8db6cbabac pinctrl: sh-pfc: r8a7796: Add VIN4, VIN5 pins, groups and functions 
This patch adds VIN4 and VIN5 pins, groups and functions for the
R8A7796 SoC.

Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2018-02-26 10:19:03 +01:00
Jacopo Mondi fa3e8b71b9 pinctrl: sh-pfc: r8a77965: Add EtherAVB groups/functions 
Add EtherAVB groups and functions definitions for R-Car M3-N.

Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2018-02-20 19:33:02 +01:00