Commit Graph

14 Commits

Author SHA1 Message Date
Chris Zankel 367b8112fe xtensa: move headers files to arch/xtensa/include
Move all header files for xtensa to arch/xtensa/include and platform and
variant header files to the appropriate arch/xtensa/platforms/ and
arch/xtensa/variants/ directories.

Moving the files gets also rid of all uses of symlinks in the Makefile.

This has been completed already for the majority of the architectures
and xtensa is one out of six missing.

Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Chris Zankel <chris@zankel.net>
2008-11-06 10:25:09 -08:00
Chris Zankel e108843062 [XTENSA] Fix register corruption for certain processor configurations
For processor configurations that have optional registers
(compiler-used but non-coprocessor), user space registers
might get corrupted when there are only 4 registers in
the current window-frame, ie. register a4 belongs to the
oldest frame in the register file.

Signed-off-by: Chris Zankel <chris@zankel.net>
2008-02-13 17:43:54 -08:00
Chris Zankel c658eac628 [XTENSA] Add support for configurable registers and coprocessors
The Xtensa architecture allows to define custom instructions and
registers. Registers that are bound to a coprocessor are only
accessible if the corresponding enable bit is set, which allows
to implement a 'lazy' context switch mechanism. Other registers
needs to be saved and restore at the time of the context switch
or during interrupt handling.

This patch adds support for these additional states:

- save and restore registers that are used by the compiler upon
  interrupt entry and exit.
- context switch additional registers unbound to any coprocessor
- 'lazy' context switch of registers bound to a coprocessor
- ptrace interface to provide access to additional registers
- update configuration files in include/asm-xtensa/variant-fsf

Signed-off-by: Chris Zankel <chris@zankel.net>
2008-02-13 17:41:43 -08:00
Chris Zankel 03dfa442e5 [XTENSA] Remove unused code
We will never (need to) support signal handling coming from a
double exception. There are too many things that could go wrong
and delivering signals is not the fastest method for IPC, anyway.

Signed-off-by: Chris Zankel <chris@zankel.net>
2008-02-13 17:24:17 -08:00
Chris Zankel ea0b6b0663 [XTENSA] Fix comments regarding the number of frames to save
Signed-off-by: Marc Gauthier <marc@tensilica.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
2008-02-13 17:22:18 -08:00
Chris Zankel 50c0716aa2 [XTENSA] Add missing a2 register restore in register spill routine
Register a2 is saved in depc but wasn't getting restored before
returning from _spill_registers when there weren't any registers
to spill. The mask to cut the top bit from the rotated WINDOWMASK
register was also one bit short.

Signed-off-by: CHris Zankel <chris@zankel.net>
2008-02-13 17:21:27 -08:00
Chris Zankel 6656920b0b [XTENSA] Add support for cache-aliasing
Add support for processors that have cache-aliasing issues, such as
the Stretch S5000 processor. Cache-aliasing means that the size of
the cache (for one way) is larger than the page size, thus, a page
can end up in several places in cache depending on the virtual to
physical translation. The method used here is to map a user page
temporarily through the auto-refill way 0 and of of the DTLB.
We probably will want to revisit this issue and use a better
approach with kmap/kunmap.

Signed-off-by: Chris Zankel <chris@zankel.net>
2007-08-27 13:54:16 -07:00
Chris Zankel 01858d1b0b [XTENSA] Add support for executable/non-executable feature in the mmu
Newer processor versions starting with Xtensa6/LX2 support an 'executable'
bit for memory pages. This bit replaces the 'valid' bit, so it must be
always set to one for older processor versions. To mark a page invalid, we now
set the cache-attributes to b11, which is backward compatible.

Signed-off-by: Chris Zankel <chris@zankel.net>
2007-08-27 13:54:01 -07:00
Chris Zankel 29c4dfd92e [XTENSA] Remove non-rt signal handling
The non-rt signal handling was never really used, so we don't break
anything. This patch also cleans up the signal stack-frame to make
it independent from the processor configuration. It also improves
the method used for controlling single-stepping. We now save and
restore the 'icountlevel' register that controls single stepping
and set or clear the saved state to enable or disable it.

Signed-off-by: Chris Zankel <chris@zankel.net>
2007-05-31 17:49:32 -07:00
Chris Zankel fc4fb2adf9 [PATCH] xtensa: fix system call interface
This is a long outstanding patch to finally fix the syscall interface.  The
constants used for the system calls are those we have provided in our libc
patches.  This patch also fixes the shmbuf and stat structure, and fcntl
definitions.

Signed-off-by: Chris Zankel <chris@zankel.net>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-12-10 09:55:39 -08:00
Chris Zankel 173d668138 [PATCH] xtensa: remove extra header files
The Xtensa port contained many header files that were never needed.  This
rather lengthy patch removes all those files.  Unfortunately, there were
many dependencies that needed to be updated, so this patch touches quite a
few source files.

Signed-off-by: Chris Zankel <chris@zankel.net>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-12-10 09:55:39 -08:00
Jesper Juhl b9e122c80c [PATCH] xtensa: remove verify_area macros
verify_area() is still alive on xtensa in 2.6.17-rc3-git13 It would be nice
to finally be rid of that function across the board.

Signed-off-by: Chris Zankel <chris@zankel.net>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-06-23 07:43:02 -07:00
Sam Ravnborg 0013a85454 kbuild: m68k,parisc,ppc,ppc64,s390,xtensa use generic asm-offsets.h support
Delete obsoleted parts form arch makefiles and rename to asm-offsets.h

Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
2005-09-09 20:57:26 +02:00
Chris Zankel 5a0015d626 [PATCH] xtensa: Architecture support for Tensilica Xtensa Part 3
The attached patches provides part 3 of an architecture implementation for the
Tensilica Xtensa CPU series.

Signed-off-by: Chris Zankel <chris@zankel.net>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-06-24 00:05:21 -07:00