Commit Graph

14 Commits

Author SHA1 Message Date
Alexander A. Klimov 5856d8bd30
ASoC: Replace HTTP links with HTTPS ones
Rationale:
Reduces attack surface on kernel devs opening the links for MITM
as HTTPS traffic is much harder to manipulate.

Deterministic algorithm:
For each file:
  If not .svg:
    For each line:
      If doesn't contain `\bxmlns\b`:
        For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`:
	  If neither `\bgnu\.org/license`, nor `\bmozilla\.org/MPL\b`:
            If both the HTTP and HTTPS versions
            return 200 OK and serve the same content:
              Replace HTTP with HTTPS.

Signed-off-by: Alexander A. Klimov <grandmaster@al2klimov.de>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20200719153822.59788-1-grandmaster@al2klimov.de
Signed-off-by: Mark Brown <broonie@kernel.org>
2020-07-22 14:31:55 +01:00
Thomas Gleixner 1802d0beec treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174
Based on 1 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license version 2 as
  published by the free software foundation this program is
  distributed in the hope that it will be useful but without any
  warranty without even the implied warranty of merchantability or
  fitness for a particular purpose see the gnu general public license
  for more details

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-only

has been chosen to replace the boilerplate/reference in 655 file(s).

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Allison Randal <allison@lohutok.net>
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Richard Fontana <rfontana@redhat.com>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190527070034.575739538@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-30 11:26:41 -07:00
Axel Lin 95f1044f56 ASoC: tas2552: Fix off-by-one for max_register setting
The latest valid register is TAS2552_VBAT_DATA.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Dan Murphy<dmurphy@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-07-23 16:46:31 +01:00
Peter Ujfalusi 4afdd89df0 ASoC: tas2552: Code, define alignment changes for uniformity
Align the numbers in the header file to the same column.
At the same time change the wrapping of CFG_2 register write in the probe
function to be uniform with the other calls.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-06-08 18:53:18 +01:00
Peter Ujfalusi 2a9dd1db70 ASoC: tas2552: Correct Boost Auto-Pass Through Control register usage
Correct the bit definition so the code will change the bits what it
supposed to change. Also rename the register define to
TAS2552_BOOST_APT_CTRL.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-06-08 18:53:18 +01:00
Peter Ujfalusi b2822f191a ASoC: tas2552: Correct Output Data register usage
Do not write to DOUT Tristate register at probe time, specially not write
data which is defined to be used in Output Data Register.
Fix the defines for the Output Data Register and correct the register write
at probe time.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-06-08 18:53:18 +01:00
Peter Ujfalusi 1014f7eff9 ASoC: tas2552: Correct the PLL configuration
Do not restrict the sampling rate to 44.1/48KHz. The pll_clk clock should
be (sampling rate * 512) in all cases.
Correct the J.D calculation (the D part was incorrectly calculated).
Restore PLL enable status after we are done with the configuration.
Implement hardware constraint handling towards the pll_clkin:
if D != 0 (in J.D) then 1.1MHz <= pll_clkin <= 9.2MHz needs to be checked.
If the PLL setup does not met with this constraint, fall back to BCLK as
reference clock, if BCLK fails, use the internal 1.8MHz clock.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-06-08 18:53:18 +01:00
Peter Ujfalusi a571cb17ac ASoC: tas2552: Configure the WCLK frequency based on the stream
Instead of hard wiring the WCLK frequency at probe time do it runtime.
The hard wired 88_96KHz was not even setting the correct bits since it was
defined as (1 << 6) which will  change the I2S_OUT_SEL bit and will leave
the amplifier configured for 8KHz.
At the same time clean up and fix the CFG3 register bits.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-06-05 18:53:36 +01:00
Peter Ujfalusi d20b098dd9 ASoC: tas2552: Add support for word length configuration
Configure the word length based on the params_width of the stream.
Also configure the clock per frame value which is used when tas2552 is bus
master.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-06-05 18:53:36 +01:00
Peter Ujfalusi 3f747a810e ASoC: tas2552: Add TDM support
TDM support is achieved using DSP transfer mode and setting a programmable
offset which specifies where data begins with respect to the frame sync.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-06-05 18:53:34 +01:00
Peter Ujfalusi 1b68c7dca2 ASoC: tas2552: Correct and clean up data format and BCLK/WCLK direction
Use names from the datasheet for the definitions.
Correct the data format definitions since they were not correct.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-06-05 18:53:34 +01:00
Peter Ujfalusi 7de544fd32 ASoC: tas2552: Correct CFG1 register bit definitions
Remove the _MASK postfix of the bit definitions, collect the CFG1 bit
definition in one place and correct the bit shifts at the same time.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-06-04 17:50:02 +01:00
Peter Ujfalusi 89683fdefd ASoC: tas2552: Correct PDM configuration register bit definitions
The PDM clock can be selected via bit0-1.
PDM_DATA_ES bit is at bit2.

The code were trying to select BCLK as PDM reference clock but instead
it was selecting PLL and set the DATA_ES bit to 1.
Selecting the PLL output as reference clock as default does make sense,
but the driver should not change the PDM data edge.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-06-04 17:50:02 +01:00
Dan Murphy 5df7f71d5c ASoC: tas2552: Support TI TAS2552 Amplifier
Support the TI TAS2552 Class D amplifier.

The TAS2552 is a high efficiency Class-D audio
power amplifier with advanced battery current
management and an integrated Class-G boost
The device constantly measures the
current and voltage across the load and provides a
digital stream of this information.

Signed-off-by: Dan Murphy <dmurphy@ti.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
2014-07-17 17:57:05 +01:00