Commit Graph

3 Commits

Author SHA1 Message Date
Thomas Gleixner 8e8e69d67e treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 285
Based on 1 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license as published by
  the free software foundation version 2 of the license this program
  is distributed in the hope that it will be useful but without any
  warranty without even the implied warranty of merchantability or
  fitness for a particular purpose see the gnu general public license
  for more details

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-only

has been chosen to replace the boilerplate/reference in 100 file(s).

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Alexios Zavras <alexios.zavras@intel.com>
Reviewed-by: Allison Randal <allison@lohutok.net>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190529141900.918357685@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-06-05 17:36:37 +02:00
Sriram Periyasamy 01f50d69be
ASoC: Intel: Skylake: Add ssp clock driver
For certain platforms, it is required to start the clocks (mclk/sclk/fs)
before the stream start. Example: for few chrome systems, codec needs the
mclk/sclk to be enabled early for a successful clock synchronization and
for few IVI platforms, clock need to be enabled at boot and should be ON
always.

Add the required structures and create set_dma_control ipc to enable or
disable the clock. To enable sclk without fs, mclk ipc structure is used,
else sclkfs ipc structure is used.

Clock prepare/unprepare are used to enable/disable the clock as the IPC
will be sent in non-atomic context. The clk set_dma_control IPC
structures are populated during the set_rate callback and IPC is sent
to enable the clock during prepare callback.

This patch creates virtual clock driver, which allows the machine driver
to use the clock interface to send IPCs to DSP to enable/disable the
clocks.

Signed-off-by: Sriram Periyasamy <sriramx.periyasamy@intel.com>
Signed-off-by: Jaikrishna Nemallapudi <jaikrishnax.nemallapudi@intel.com>
Signed-off-by: Subhransu S. Prusty <subhransu.s.prusty@intel.com>
Acked-by: Vinod Koul <vinod.koul@intel.com>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2018-01-26 12:51:21 +00:00
Sriram Periyasamy bc2bd45b1f
ASoC: Intel: Skylake: Parse nhlt and register clock device
When NHLT endpoint is present for a SSP then we create clock for that SSP.

MCLK is consistent across endpoints and configuration for an SSP, so query
only for first endpoint for an SSP.

For SCLK/SCLKFS, the best fit is queried from the NHLT configurations which
matches the clock rate requested. Best fit is decided based on below:

1. If rate matches with multiple configurations, then the first
   configuration is selected.

2. If for a selected fs and bits_per_sample, there are multiple endpoint
   configuration match, then the configuration with max number of
   channels is selected. So, the user has to set the rate which fits
   max number of channels

So we create a platform device and pass clock information parsed as
platform data.

Signed-off-by: Sriram Periyasamy <sriramx.periyasamy@intel.com>
Signed-off-by: Jaikrishna Nemallapudi <jaikrishnax.nemallapudi@intel.com>
Signed-off-by: Subhransu S. Prusty <subhransu.s.prusty@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2017-11-29 15:39:47 +00:00