Commit Graph

10 Commits

Author SHA1 Message Date
Thomas Gleixner 2874c5fd28 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152
Based on 1 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license as published by
  the free software foundation either version 2 of the license or at
  your option any later version

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-or-later

has been chosen to replace the boilerplate/reference in 3029 file(s).

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Allison Randal <allison@lohutok.net>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-30 11:26:32 -07:00
Linus Torvalds d8ea757b25 Xtensa improvements for 4.9:
- add new kernel memory layouts for MMUv3 cores: with 256MB and 512MB
   KSEG size, starting at physical address other than 0;
 - make kernel load address configurable;
 - clean up kernel memory layout macros;
 - drop sysmem early allocator and switch to memblock;
 - enable kmemleak and memory reservation from the device tree;
 - wire up new syscalls: userfaultfd, membarrier, mlock2, copy_file_range,
   preadv2 and pwritev2;
 - add new platform: Cadence Configurable System Platform (CSP) and new
   core variant for it: xt_lnx;
 - rearrange CCOUNT calibration code, make most of it generic;
 - improve machine reset code (XTFPGA now reboots reliably with MMUv3
   cores);
 - provide default memmap command line option for configurations without
   device tree support;
 - ISS fixes: simdisk is now capable of using highmem pages, panic
   correctly terminates simulator.
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Merge tag 'xtensa-20161005' of git://github.com/jcmvbkbc/linux-xtensa

Pull Xtensa updates from Max Filippov:
 "Updates for the xtensa architecture.  It is a combined set of patches
  for 4.8 that never got to the mainline and new patches for 4.9.

   - add new kernel memory layouts for MMUv3 cores: with 256MB and 512MB
     KSEG size, starting at physical address other than 0

   - make kernel load address configurable

   - clean up kernel memory layout macros

   - drop sysmem early allocator and switch to memblock

   - enable kmemleak and memory reservation from the device tree

   - wire up new syscalls: userfaultfd, membarrier, mlock2,
     copy_file_range, preadv2 and pwritev2

   - add new platform: Cadence Configurable System Platform (CSP) and
     new core variant for it: xt_lnx

   - rearrange CCOUNT calibration code, make most of it generic

   - improve machine reset code (XTFPGA now reboots reliably with MMUv3
     cores)

   - provide default memmap command line option for configurations
     without device tree support

   - ISS fixes: simdisk is now capable of using highmem pages, panic
     correctly terminates simulator"

* tag 'xtensa-20161005' of git://github.com/jcmvbkbc/linux-xtensa: (24 commits)
  xtensa: disable MMU initialization option on MMUv2 cores
  xtensa: add default memmap and mmio32native options to defconfigs
  xtensa: add default memmap option to common_defconfig
  xtensa: add default memmap option to iss_defconfig
  xtensa: ISS: allow simdisk to use high memory buffers
  xtensa: ISS: define simc_exit and use it instead of inline asm
  xtensa: xtfpga: group platform_* functions together
  xtensa: rearrange CCOUNT calibration
  xtensa: xtfpga: use clock provider, don't update DT
  xtensa: Tweak xuartps UART driver Rx watermark for Cadence CSP config.
  xtensa: initialize MMU before jumping to reset vector
  xtensa: fix icountlevel setting in cpu_reset
  xtensa: extract common CPU reset code into separate function
  xtensa: Added Cadence CSP kernel configuration for Xtensa
  xtensa: fix default kernel load address
  xtensa: wire up new syscalls
  xtensa: support reserved-memory DT node
  xtensa: drop sysmem and switch to memblock
  xtensa: minimize use of PLATFORM_DEFAULT_MEM_{ADDR,SIZE}
  xtensa: cleanup MMU setup and kernel layout macros
  ...
2016-10-05 17:44:48 -07:00
Max Filippov 4f2056873f xtensa: extract common CPU reset code into separate function
platform_restart implementatations do the same thing to reset CPU.
Don't duplicate that code, move it to a function and call it from
platform_restart.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2016-09-11 23:53:22 -07:00
Jiri Slaby 6137b7a629 tty: stop defining STD_COM_FLAGS in drivers
STD_COM_FLAGS is mostly a bad name for what the drivers thinks it is.
Stop using it and pass the flags directly.

cyclades defines it as 0, so we do not assign anything to freshly
tty_port_init'ed structure.

Signed-off-by: Jiri Slaby <jslaby@suse.cz>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2016-06-25 08:56:30 -07:00
Peter Hurley 35373abbce serial: Fix ASYNC_* => UPF_* flags misuse
The UPF_* flags are the correct values to use for struct uart_port
and struct old_serial_port/SERIAL_PORT_DFNS.

Signed-off-by: Peter Hurley <peter@hurleysoftware.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2016-01-28 14:17:42 -08:00
Max Filippov 5029615e25 xtensa: fixes for configs without loop option
Build-time fixes:
- make lbeg/lend/lcount save/restore conditional on kernel entry;
- don't clear lcount in platform_restart functions unconditionally.

Run-time fixes:
- use correct end of range register in __endla paired with __loopt, not
  the unused temporary register. This fixes .bss zero-initialization.
  Update comments in asmmacro.h;
- don't clobber a10 in the usercopy that leads to access to unmapped
  memory.

Cc: <stable@vger.kernel.org>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2015-11-02 18:02:47 +03:00
Max Filippov cfe8255f0a xtensa: xt2000: drop redundant sysmem initialization
sysmem structure initialization in xt2000 platform_init is identical to
the one done in init_arch just before the call to platform_init.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-04-10 00:19:03 -07:00
Max Filippov d83ff0bb82 xtensa: fix ibreakenable register update
Only set the register when there is at least one ibreak register,
otherwise the build fails:
	arch/xtensa/kernel/head.S:105: Error: invalid register 'ibreakenable'
	for 'wsr' instruction
	arch/xtensa/platforms/iss/setup.c:67: Error: invalid register
	'ibreakenable' for 'wsr' instruction

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
2013-05-09 01:07:09 -07:00
Max Filippov bc5378fcba xtensa: reorganize SR referencing
- reference SRs by names where possible, not by numbers;
- get rid of __stringify around SR names where possible;
- remove unneeded SR names from asm/regs.h;
- add SREG_ prefix to remaining SR names;

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
2012-10-15 21:48:08 -07:00
Chris Zankel 8fa5723aa7 xtensa: Add xt2000 support files.
The last check-in to support the xt2000 development platform was missing
some files.

Signed-off-by: Chris Zankel <chris@zankel.net>
2008-11-06 10:25:26 -08:00