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- introduce Allwinner D1 DTSI 

- add boards: Dongshan Nezha STU, MangoPi MQ (Pro), Sipeed Lichee RV,
   Nezha
 - add D1 power controller node
 - Add SATA regulator to Bananapi M3
 - fix regulator reference for nanopi-duo2
 - fix GPIO node names
 - align HDMI CEC node name for h3-beelink-x2
 - add DPHY interrupt to A64 and A33
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Merge tag 'sunxi-dt-for-6.3-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/dt

- introduce Allwinner D1 DTSI
- add boards: Dongshan Nezha STU, MangoPi MQ (Pro), Sipeed Lichee RV,
  Nezha
- add D1 power controller node
- Add SATA regulator to Bananapi M3
- fix regulator reference for nanopi-duo2
- fix GPIO node names
- align HDMI CEC node name for h3-beelink-x2
- add DPHY interrupt to A64 and A33

* tag 'sunxi-dt-for-6.3-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  riscv: dts: allwinner: d1: Add power controller node
  riscv: Add the Allwinner SoC family Kconfig option
  riscv: dts: allwinner: Add Dongshan Nezha STU devicetree
  riscv: dts: allwinner: Add MangoPi MQ Pro devicetree
  riscv: dts: allwinner: Add Sipeed Lichee RV devicetrees
  riscv: dts: allwinner: Add Allwinner D1 Nezha devicetree
  riscv: dts: allwinner: Add MangoPi MQ devicetree
  riscv: dts: allwinner: Add the D1/D1s SoC devicetree
  dt-bindings: riscv: Add Allwinner D1/D1s board compatibles
  dt-bindings: vendor-prefixes: Add Allwinner D1/D1s board vendors
  MAINTAINERS: Match the sun20i family of Allwinner SoCs
  ARM: dts: sun8i: a83t: bananapi-m3: describe SATA disk regulator
  ARM: dts: sun8i: nanopi-duo2: Fix regulator GPIO reference
  ARM: dts: sunxi: Fix GPIO LED node names
  ARM: dts: sun8i: h3-beelink-x2: align HDMI CEC node names with dtschema
  arm64: dts: allwinner: a64: Add DPHY interrupt
  ARM: dts: sun8i: a33: Add DPHY interrupt

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2023-01-30 22:42:37 +01:00
parent 248c07f92c dca36f7b3d
commit ffe4bd3db8
28 changed files with 2029 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

69
Documentation/devicetree/bindings/riscv/sunxi.yaml Normal file
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@ -0,0 +1,69 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/riscv/sunxi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner RISC-V SoC-based boards
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Jernej Skrabec <jernej.skrabec@gmail.com>
- Samuel Holland <samuel@sholland.org>
description:
Allwinner RISC-V SoC-based boards
properties:
$nodename:
const: '/'
compatible:
oneOf:
- description: Dongshan Nezha STU SoM
items:
- const: 100ask,dongshan-nezha-stu
- const: allwinner,sun20i-d1
- description: D1 Nezha board
items:
- const: allwinner,d1-nezha
- const: allwinner,sun20i-d1
- description: ClockworkPi R-01 SoM and v3.14 board
items:
- const: clockwork,r-01-clockworkpi-v3.14
- const: allwinner,sun20i-d1
- description: ClockworkPi R-01 SoM, v3.14 board, and DevTerm expansion
items:
- const: clockwork,r-01-devterm-v3.14
- const: clockwork,r-01-clockworkpi-v3.14
- const: allwinner,sun20i-d1
- description: Lichee RV SoM
items:
- const: sipeed,lichee-rv
- const: allwinner,sun20i-d1
- description: Carrier boards for the Lichee RV SoM
items:
- enum:
- sipeed,lichee-rv-86-panel-480p
- sipeed,lichee-rv-86-panel-720p
- sipeed,lichee-rv-dock
- const: sipeed,lichee-rv
- const: allwinner,sun20i-d1
- description: MangoPi MQ board
items:
- const: widora,mangopi-mq
- const: allwinner,sun20i-d1s
- description: MangoPi MQ Pro board
items:
- const: widora,mangopi-mq-pro
- const: allwinner,sun20i-d1
additionalProperties: true
...

4
Documentation/devicetree/bindings/vendor-prefixes.yaml
View File

@ -266,6 +266,8 @@ patternProperties:
description: Cirrus Logic, Inc.
"^cisco,.*":
description: Cisco Systems, Inc.
"^clockwork,.*":
description: Clockwork Tech LLC
"^cloos,.*":
description: Carl Cloos Schweisstechnik GmbH.
"^cloudengines,.*":
@ -1448,6 +1450,8 @@ patternProperties:
description: Shenzhen whwave Electronics, Inc.
"^wi2wi,.*":
description: Wi2Wi, Inc.
"^widora,.*":
description: Beijing Widora Technology Co., Ltd.
"^wiligear,.*":
description: Wiligear, Ltd.
"^willsemi,.*":

2
MAINTAINERS
View File

@ -1888,7 +1888,7 @@ F: drivers/pinctrl/sunxi/
F: drivers/soc/sunxi/
N: allwinner
N: sun[x456789]i
N: sun50i
N: sun[25]0i
ARM/Amlogic Meson SoC CLOCK FRAMEWORK
M: Neil Armstrong <neil.armstrong@linaro.org>

2
arch/arm/boot/dts/sun5i-gr8-chip-pro.dts
View File

@ -70,7 +70,7 @@
leds {
compatible = "gpio-leds";
status {
led-0 {
label = "chip-pro:white:status";
gpios = <&axp_gpio 2 GPIO_ACTIVE_HIGH>;
default-state = "on";

2
arch/arm/boot/dts/sun5i-r8-chip.dts
View File

@ -70,7 +70,7 @@
leds {
compatible = "gpio-leds";
status {
led-0 {
label = "chip:white:status";
gpios = <&axp_gpio 2 GPIO_ACTIVE_HIGH>;
default-state = "on";

2
arch/arm/boot/dts/sun6i-a31s-sina31s.dts
View File

@ -67,7 +67,7 @@
leds {
compatible = "gpio-leds";
status {
led-0 {
label = "sina31s:status:usr";
gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>; /* PH13 */
};

1
arch/arm/boot/dts/sun8i-a33.dtsi
View File

@ -278,6 +278,7 @@
dphy: d-phy@1ca1000 {
compatible = "allwinner,sun6i-a31-mipi-dphy";
reg = <0x01ca1000 0x1000>;
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_MIPI_DSI>,
<&ccu CLK_DSI_DPHY>;
clock-names = "bus", "mod";

15
arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
View File

@ -105,6 +105,21 @@
/* enables internal regulator and de-asserts reset */
reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */
};
/*
* Power supply for the SATA disk, behind a USB-SATA bridge.
* Since it is a USB device, there is no consumer in the DT, so we
* have to keep this always on.
*/
regulator-sata-disk-pwr {
compatible = "regulator-fixed";
regulator-name = "sata-disk-pwr";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
enable-active-high;
gpio = <&pio 3 25 GPIO_ACTIVE_HIGH>; /* PD25 */
};
};
&cpu0 {

2
arch/arm/boot/dts/sun8i-h3-beelink-x2.dts
View File

@ -57,7 +57,7 @@
ethernet1 = &sdiowifi;
};
cec-gpio {
cec {
compatible = "cec-gpio";
cec-gpios = <&pio 0 14 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; /* PA14 */
hdmi-phandle = <&hdmi>;

2
arch/arm/boot/dts/sun8i-h3-nanopi-duo2.dts
View File

@ -57,7 +57,7 @@
regulator-ramp-delay = <50>; /* 4ms */
enable-active-high;
enable-gpio = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */
enable-gpios = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */
gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
gpios-states = <0x1>;
states = <1100000 0>, <1300000 1>;

1
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
View File

@ -1199,6 +1199,7 @@
compatible = "allwinner,sun50i-a64-mipi-dphy",
"allwinner,sun6i-a31-mipi-dphy";
reg = <0x01ca1000 0x1000>;
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_MIPI_DSI>,
<&ccu CLK_DSI_DPHY>;
clock-names = "bus", "mod";

9
arch/riscv/Kconfig.socs
View File

@ -32,6 +32,15 @@ config SOC_STARFIVE
help
This enables support for StarFive SoC platform hardware.
config ARCH_SUNXI
bool "Allwinner sun20i SoCs"
depends on MMU && !XIP_KERNEL
select ERRATA_THEAD
select SUN4I_TIMER
help
This enables support for Allwinner sun20i platform hardware,
including boards based on the D1 and D1s SoCs.
config ARCH_VIRT
def_bool SOC_VIRT

1
arch/riscv/boot/dts/Makefile
View File

@ -1,4 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
subdir-y += allwinner
subdir-y += sifive
subdir-y += starfive
subdir-y += canaan

9
arch/riscv/boot/dts/allwinner/Makefile Normal file
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@ -0,0 +1,9 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-dongshan-nezha-stu.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-86-panel-480p.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-86-panel-720p.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-dock.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-mangopi-mq-pro.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-nezha.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1s-mangopi-mq.dtb

28
arch/riscv/boot/dts/allwinner/sun20i-common-regulators.dtsi Normal file
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@ -0,0 +1,28 @@
// SPDX-License-Identifier: (GPL-2.0+ or MIT)
// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
/ {
reg_vcc: vcc {
compatible = "regulator-fixed";
regulator-name = "vcc";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
reg_vcc_3v3: vcc-3v3 {
compatible = "regulator-fixed";
regulator-name = "vcc-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&reg_vcc>;
};
};
&pio {
vcc-pb-supply = <&reg_vcc_3v3>;
vcc-pc-supply = <&reg_vcc_3v3>;
vcc-pd-supply = <&reg_vcc_3v3>;
vcc-pe-supply = <&reg_vcc_3v3>;
vcc-pf-supply = <&reg_vcc_3v3>;
vcc-pg-supply = <&reg_vcc_3v3>;
};

117
arch/riscv/boot/dts/allwinner/sun20i-d1-dongshan-nezha-stu.dts Normal file
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@ -0,0 +1,117 @@
// SPDX-License-Identifier: (GPL-2.0+ or MIT)
// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
/dts-v1/;
#include "sun20i-d1.dtsi"
#include "sun20i-common-regulators.dtsi"
/ {
model = "Dongshan Nezha STU";
compatible = "100ask,dongshan-nezha-stu", "allwinner,sun20i-d1";
aliases {
ethernet0 = &emac;
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
leds {
compatible = "gpio-leds";
led-0 {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_STATUS;
gpios = <&pio 2 1 GPIO_ACTIVE_HIGH>; /* PC1 */
};
};
reg_usbvbus: usbvbus {
compatible = "regulator-fixed";
regulator-name = "usbvbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&pio 3 19 GPIO_ACTIVE_HIGH>; /* PD19 */
enable-active-high;
vin-supply = <&reg_vcc>;
};
/*
* This regulator is PWM-controlled, but the PWM controller is not
* yet supported, so fix the regulator to its default voltage.
*/
reg_vdd_cpu: vdd-cpu {
compatible = "regulator-fixed";
regulator-name = "vdd-cpu";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
vin-supply = <&reg_vcc>;
};
};
&cpu0 {
cpu-supply = <&reg_vdd_cpu>;
};
&dcxo {
clock-frequency = <24000000>;
};
&ehci0 {
status = "okay";
};
&emac {
pinctrl-0 = <&rgmii_pe_pins>;
pinctrl-names = "default";
phy-handle = <&ext_rgmii_phy>;
phy-mode = "rgmii-id";
phy-supply = <&reg_vcc_3v3>;
status = "okay";
};
&mdio {
ext_rgmii_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
&mmc0 {
broken-cd;
bus-width = <4>;
disable-wp;
vmmc-supply = <&reg_vcc_3v3>;
vqmmc-supply = <&reg_vcc_3v3>;
pinctrl-0 = <&mmc0_pins>;
pinctrl-names = "default";
status = "okay";
};
&ohci0 {
status = "okay";
};
&uart0 {
pinctrl-0 = <&uart0_pb8_pins>;
pinctrl-names = "default";
status = "okay";
};
&usb_otg {
dr_mode = "otg";
status = "okay";
};
&usbphy {
usb0_id_det-gpios = <&pio 3 21 GPIO_ACTIVE_HIGH>; /* PD21 */
usb0_vbus_det-gpios = <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */
usb0_vbus-supply = <&reg_usbvbus>;
status = "okay";
};

29
arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-480p.dts Normal file
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@ -0,0 +1,29 @@
// SPDX-License-Identifier: (GPL-2.0+ or MIT)
// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
#include "sun20i-d1-lichee-rv-86-panel.dtsi"
/ {
model = "Sipeed Lichee RV 86 Panel (480p)";
compatible = "sipeed,lichee-rv-86-panel-480p", "sipeed,lichee-rv",
"allwinner,sun20i-d1";
};
&i2c2 {
pinctrl-0 = <&i2c2_pb0_pins>;
pinctrl-names = "default";
status = "okay";
touchscreen@48 {
compatible = "focaltech,ft6236";
reg = <0x48>;
interrupt-parent = <&pio>;
interrupts = <6 14 IRQ_TYPE_LEVEL_LOW>; /* PG14 */
iovcc-supply = <&reg_vcc_3v3>;
reset-gpios = <&pio 6 15 GPIO_ACTIVE_LOW>; /* PG15 */
touchscreen-size-x = <480>;
touchscreen-size-y = <480>;
vcc-supply = <&reg_vcc_3v3>;
wakeup-source;
};
};

10
arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-720p.dts Normal file
View File

@ -0,0 +1,10 @@
// SPDX-License-Identifier: (GPL-2.0+ or MIT)
// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
#include "sun20i-d1-lichee-rv-86-panel.dtsi"
/ {
model = "Sipeed Lichee RV 86 Panel (720p)";
compatible = "sipeed,lichee-rv-86-panel-720p", "sipeed,lichee-rv",
"allwinner,sun20i-d1";
};

119
arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel.dtsi Normal file
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@ -0,0 +1,119 @@
// SPDX-License-Identifier: (GPL-2.0+ or MIT)
// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
#include "sun20i-d1-lichee-rv.dts"
/ {
aliases {
ethernet0 = &emac;
ethernet1 = &xr829;
};
dmic_codec: dmic-codec {
compatible = "dmic-codec";
num-channels = <2>;
#sound-dai-cells = <0>;
};
dmic-sound {
compatible = "simple-audio-card";
simple-audio-card,name = "DMIC";
#address-cells = <1>;
#size-cells = <0>;
simple-audio-card,dai-link@0 {
reg = <0>;
format = "pdm";
frame-master = <&link0_cpu>;
bitclock-master = <&link0_cpu>;
link0_cpu: cpu {
sound-dai = <&dmic>;
};
link0_codec: codec {
sound-dai = <&dmic_codec>;
};
};
};
/* PC1 is repurposed as BT_WAKE_AP */
/delete-node/ leds;
wifi_pwrseq: wifi-pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&ccu CLK_FANOUT1>;
clock-names = "ext_clock";
reset-gpios = <&pio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */
assigned-clocks = <&ccu CLK_FANOUT1>;
assigned-clock-rates = <32768>;
pinctrl-0 = <&clk_pg11_pin>;
pinctrl-names = "default";
};
};
&dmic {
pinctrl-0 = <&dmic_pb11_d0_pin>, <&dmic_pe17_clk_pin>;
pinctrl-names = "default";
status = "okay";
};
&ehci1 {
status = "okay";
};
&emac {
pinctrl-0 = <&rmii_pe_pins>;
pinctrl-names = "default";
phy-handle = <&ext_rmii_phy>;
phy-mode = "rmii";
phy-supply = <&reg_vcc_3v3>;
status = "okay";
};
&mdio {
ext_rmii_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
reset-gpios = <&pio 4 16 GPIO_ACTIVE_LOW>; /* PE16 */
};
};
&mmc1 {
bus-width = <4>;
mmc-pwrseq = <&wifi_pwrseq>;
non-removable;
vmmc-supply = <&reg_vcc_3v3>;
vqmmc-supply = <&reg_vcc_3v3>;
pinctrl-0 = <&mmc1_pins>;
pinctrl-names = "default";
status = "okay";
xr829: wifi@1 {
reg = <1>;
};
};
&ohci1 {
status = "okay";
};
&uart1 {
uart-has-rtscts;
pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>;
pinctrl-names = "default";
status = "okay";
/* XR829 bluetooth is connected here */
};
&usb_otg {
status = "disabled";
};
&usbphy {
/* PD20 and PD21 are repurposed for the LCD panel */
/delete-property/ usb0_id_det-gpios;
/delete-property/ usb0_vbus_det-gpios;
usb1_vbus-supply = <&reg_vcc>;
};

97
arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts Normal file
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@ -0,0 +1,97 @@
// SPDX-License-Identifier: (GPL-2.0+ or MIT)
// Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org>
// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
#include <dt-bindings/input/input.h>
#include "sun20i-d1-lichee-rv.dts"
/ {
model = "Sipeed Lichee RV Dock";
compatible = "sipeed,lichee-rv-dock", "sipeed,lichee-rv",
"allwinner,sun20i-d1";
aliases {
ethernet1 = &rtl8723ds;
};
dmic_codec: dmic-codec {
compatible = "dmic-codec";
num-channels = <2>;
#sound-dai-cells = <0>;
};
dmic-sound {
compatible = "simple-audio-card";
simple-audio-card,name = "DMIC";
#address-cells = <1>;
#size-cells = <0>;
simple-audio-card,dai-link@0 {
reg = <0>;
format = "pdm";
frame-master = <&link0_cpu>;
bitclock-master = <&link0_cpu>;
link0_cpu: cpu {
sound-dai = <&dmic>;
};
link0_codec: codec {
sound-dai = <&dmic_codec>;
};
};
};
wifi_pwrseq: wifi-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&pio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */
};
};
&dmic {
pinctrl-0 = <&dmic_pb11_d0_pin>, <&dmic_pe17_clk_pin>;
pinctrl-names = "default";
status = "okay";
};
&ehci1 {
status = "okay";
};
&mmc1 {
bus-width = <4>;
mmc-pwrseq = <&wifi_pwrseq>;
non-removable;
vmmc-supply = <&reg_vcc_3v3>;
vqmmc-supply = <&reg_vcc_3v3>;
pinctrl-0 = <&mmc1_pins>;
pinctrl-names = "default";
status = "okay";
rtl8723ds: wifi@1 {
reg = <1>;
};
};
&ohci1 {
status = "okay";
};
&uart1 {
uart-has-rtscts;
pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>;
pinctrl-names = "default";
status = "okay";
bluetooth {
compatible = "realtek,rtl8723ds-bt";
device-wake-gpios = <&pio 6 15 GPIO_ACTIVE_HIGH>; /* PG16 */
enable-gpios = <&pio 6 18 GPIO_ACTIVE_HIGH>; /* PG18 */
host-wake-gpios = <&pio 6 17 GPIO_ACTIVE_HIGH>; /* PG17 */
};
};
&usbphy {
usb1_vbus-supply = <&reg_vcc>;
};

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// SPDX-License-Identifier: (GPL-2.0+ or MIT)
// Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org>
// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
/dts-v1/;
#include "sun20i-d1.dtsi"
#include "sun20i-common-regulators.dtsi"
/ {
model = "Sipeed Lichee RV";
compatible = "sipeed,lichee-rv", "allwinner,sun20i-d1";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
leds {
compatible = "gpio-leds";
led-0 {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_STATUS;
gpios = <&pio 2 1 GPIO_ACTIVE_HIGH>; /* PC1 */
};
};
reg_vdd_cpu: vdd-cpu {
compatible = "regulator-fixed";
regulator-name = "vdd-cpu";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
vin-supply = <&reg_vcc>;
};
};
&cpu0 {
cpu-supply = <&reg_vdd_cpu>;
};
&dcxo {
clock-frequency = <24000000>;
};
&ehci0 {
status = "okay";
};
&mmc0 {
broken-cd;
bus-width = <4>;
disable-wp;
vmmc-supply = <&reg_vcc_3v3>;
vqmmc-supply = <&reg_vcc_3v3>;
pinctrl-0 = <&mmc0_pins>;
pinctrl-names = "default";
status = "okay";
};
&ohci0 {
status = "okay";
};
&uart0 {
pinctrl-0 = <&uart0_pb8_pins>;
pinctrl-names = "default";
status = "okay";
};
&usb_otg {
dr_mode = "otg";
status = "okay";
};
&usbphy {
usb0_id_det-gpios = <&pio 3 21 GPIO_ACTIVE_HIGH>; /* PD21 */
usb0_vbus_det-gpios = <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */
usb0_vbus-supply = <&reg_vcc>;
status = "okay";
};

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// SPDX-License-Identifier: (GPL-2.0+ or MIT)
// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
/dts-v1/;
#include "sun20i-d1.dtsi"
#include "sun20i-common-regulators.dtsi"
/ {
model = "MangoPi MQ Pro";
compatible = "widora,mangopi-mq-pro", "allwinner,sun20i-d1";
aliases {
ethernet0 = &rtl8723ds;
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
leds {
compatible = "gpio-leds";
led-0 {
color = <LED_COLOR_ID_BLUE>;
function = LED_FUNCTION_STATUS;
gpios = <&pio 3 18 GPIO_ACTIVE_HIGH>; /* PD18 */
};
};
reg_avdd2v8: avdd2v8 {
compatible = "regulator-fixed";
regulator-name = "avdd2v8";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
vin-supply = <&reg_vcc_3v3>;
};
reg_dvdd: dvdd {
compatible = "regulator-fixed";
regulator-name = "dvdd";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
vin-supply = <&reg_vcc_3v3>;
};
reg_vdd_cpu: vdd-cpu {
compatible = "regulator-fixed";
regulator-name = "vdd-cpu";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
vin-supply = <&reg_vcc>;
};
wifi_pwrseq: wifi-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&pio 6 17 GPIO_ACTIVE_LOW>; /* PG17 */
};
};
&cpu0 {
cpu-supply = <&reg_vdd_cpu>;
};
&dcxo {
clock-frequency = <24000000>;
};
&ehci1 {
status = "okay";
};
&mmc0 {
bus-width = <4>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
disable-wp;
vmmc-supply = <&reg_vcc_3v3>;
vqmmc-supply = <&reg_vcc_3v3>;
pinctrl-0 = <&mmc0_pins>;
pinctrl-names = "default";
status = "okay";
};
&mmc1 {
bus-width = <4>;
mmc-pwrseq = <&wifi_pwrseq>;
non-removable;
vmmc-supply = <&reg_vcc_3v3>;
vqmmc-supply = <&reg_vcc_3v3>;
pinctrl-0 = <&mmc1_pins>;
pinctrl-names = "default";
status = "okay";
rtl8723ds: wifi@1 {
reg = <1>;
interrupt-parent = <&pio>;
interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 */
interrupt-names = "host-wake";
};
};
&ohci1 {
status = "okay";
};
&pio {
vcc-pe-supply = <&reg_avdd2v8>;
};
&uart0 {
pinctrl-0 = <&uart0_pb8_pins>;
pinctrl-names = "default";
status = "okay";
};
&uart1 {
uart-has-rtscts;
pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>;
pinctrl-names = "default";
status = "okay";
bluetooth {
compatible = "realtek,rtl8723ds-bt";
device-wake-gpios = <&pio 6 18 GPIO_ACTIVE_HIGH>; /* PG18 */
enable-gpios = <&pio 6 15 GPIO_ACTIVE_HIGH>; /* PG15 */
host-wake-gpios = <&pio 6 14 GPIO_ACTIVE_HIGH>; /* PG14 */
};
};
&usb_otg {
dr_mode = "peripheral";
status = "okay";
};
&usbphy {
usb1_vbus-supply = <&reg_vcc>;
status = "okay";
};

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// SPDX-License-Identifier: (GPL-2.0+ or MIT)
// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/dts-v1/;
#include "sun20i-d1.dtsi"
#include "sun20i-common-regulators.dtsi"
/ {
model = "Allwinner D1 Nezha";
compatible = "allwinner,d1-nezha", "allwinner,sun20i-d1";
aliases {
ethernet0 = &emac;
ethernet1 = &xr829;
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
reg_usbvbus: usbvbus {
compatible = "regulator-fixed";
regulator-name = "usbvbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&pio 3 19 GPIO_ACTIVE_HIGH>; /* PD19 */
enable-active-high;
vin-supply = <&reg_vcc>;
};
/*
* This regulator is PWM-controlled, but the PWM controller is not
* yet supported, so fix the regulator to its default voltage.
*/
reg_vdd_cpu: vdd-cpu {
compatible = "regulator-fixed";
regulator-name = "vdd-cpu";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
vin-supply = <&reg_vcc>;
};
wifi_pwrseq: wifi-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&pio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */
};
};
&cpu0 {
cpu-supply = <&reg_vdd_cpu>;
};
&dcxo {
clock-frequency = <24000000>;
};
&ehci0 {
status = "okay";
};
&ehci1 {
status = "okay";
};
&emac {
pinctrl-0 = <&rgmii_pe_pins>;
pinctrl-names = "default";
phy-handle = <&ext_rgmii_phy>;
phy-mode = "rgmii-id";
phy-supply = <&reg_vcc_3v3>;
status = "okay";
};
&i2c2 {
pinctrl-0 = <&i2c2_pb0_pins>;
pinctrl-names = "default";
status = "okay";
pcf8574a: gpio@38 {
compatible = "nxp,pcf8574a";
reg = <0x38>;
interrupt-parent = <&pio>;
interrupts = <1 2 IRQ_TYPE_LEVEL_LOW>; /* PB2 */
interrupt-controller;
gpio-controller;
#gpio-cells = <2>;
#interrupt-cells = <2>;
};
};
&mdio {
ext_rgmii_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
&mmc0 {
bus-width = <4>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
disable-wp;
vmmc-supply = <&reg_vcc_3v3>;
vqmmc-supply = <&reg_vcc_3v3>;
pinctrl-0 = <&mmc0_pins>;
pinctrl-names = "default";
status = "okay";
};
&mmc1 {
bus-width = <4>;
mmc-pwrseq = <&wifi_pwrseq>;
non-removable;
vmmc-supply = <&reg_vcc_3v3>;
vqmmc-supply = <&reg_vcc_3v3>;
pinctrl-0 = <&mmc1_pins>;
pinctrl-names = "default";
status = "okay";
xr829: wifi@1 {
reg = <1>;
interrupt-parent = <&pio>;
interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 */
interrupt-names = "host-wake";
};
};
&ohci0 {
status = "okay";
};
&ohci1 {
status = "okay";
};
&uart0 {
pinctrl-0 = <&uart0_pb8_pins>;
pinctrl-names = "default";
status = "okay";
};
&uart1 {
uart-has-rtscts;
pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>;
pinctrl-names = "default";
status = "okay";
/* XR829 bluetooth is connected here */
};
&usb_otg {
dr_mode = "otg";
status = "okay";
};
&usbphy {
usb0_id_det-gpios = <&pio 3 21 GPIO_ACTIVE_HIGH>; /* PD21 */
usb0_vbus_det-gpios = <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */
usb0_vbus-supply = <&reg_usbvbus>;
usb1_vbus-supply = <&reg_vcc>;
status = "okay";
};

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// SPDX-License-Identifier: (GPL-2.0+ or MIT)
// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
#include "sun20i-d1s.dtsi"
#include "sunxi-d1-t113.dtsi"
/ {
soc {
lradc: keys@2009800 {
compatible = "allwinner,sun20i-d1-lradc",
"allwinner,sun50i-r329-lradc";
reg = <0x2009800 0x400>;
interrupts = <SOC_PERIPHERAL_IRQ(61) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_LRADC>;
resets = <&ccu RST_BUS_LRADC>;
status = "disabled";
};
i2s0: i2s@2032000 {
compatible = "allwinner,sun20i-d1-i2s",
"allwinner,sun50i-r329-i2s";
reg = <0x2032000 0x1000>;
interrupts = <SOC_PERIPHERAL_IRQ(26) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2S0>,
<&ccu CLK_I2S0>;
clock-names = "apb", "mod";
resets = <&ccu RST_BUS_I2S0>;
dmas = <&dma 3>, <&dma 3>;
dma-names = "rx", "tx";
status = "disabled";
#sound-dai-cells = <0>;
};
};
};
&pio {
/omit-if-no-ref/
dmic_pb11_d0_pin: dmic-pb11-d0-pin {
pins = "PB11";
function = "dmic";
};
/omit-if-no-ref/
dmic_pe17_clk_pin: dmic-pe17-clk-pin {
pins = "PE17";
function = "dmic";
};
/omit-if-no-ref/
i2c0_pb10_pins: i2c0-pb10-pins {
pins = "PB10", "PB11";
function = "i2c0";
};
/omit-if-no-ref/
i2c2_pb0_pins: i2c2-pb0-pins {
pins = "PB0", "PB1";
function = "i2c2";
};
/omit-if-no-ref/
uart0_pb8_pins: uart0-pb8-pins {
pins = "PB8", "PB9";
function = "uart0";
};
};

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// SPDX-License-Identifier: (GPL-2.0+ or MIT)
// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
/dts-v1/;
#include "sun20i-d1s.dtsi"
#include "sun20i-common-regulators.dtsi"
/ {
model = "MangoPi MQ";
compatible = "widora,mangopi-mq", "allwinner,sun20i-d1s";
aliases {
ethernet0 = &rtl8189ftv;
serial3 = &uart3;
};
chosen {
stdout-path = "serial3:115200n8";
};
leds {
compatible = "gpio-leds";
led-0 {
color = <LED_COLOR_ID_BLUE>;
function = LED_FUNCTION_STATUS;
gpios = <&pio 3 22 GPIO_ACTIVE_LOW>; /* PD22 */
};
};
reg_avdd2v8: avdd2v8 {
compatible = "regulator-fixed";
regulator-name = "avdd2v8";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
vin-supply = <&reg_vcc_3v3>;
};
reg_dvdd: dvdd {
compatible = "regulator-fixed";
regulator-name = "dvdd";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
vin-supply = <&reg_vcc_3v3>;
};
reg_vcc_core: vcc-core {
compatible = "regulator-fixed";
regulator-name = "vcc-core";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
vin-supply = <&reg_vcc>;
};
wifi_pwrseq: wifi-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&pio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */
};
};
&cpu0 {
cpu-supply = <&reg_vcc_core>;
};
&dcxo {
clock-frequency = <24000000>;
};
&ehci1 {
status = "okay";
};
&mmc0 {
bus-width = <4>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
disable-wp;
vmmc-supply = <&reg_vcc_3v3>;
vqmmc-supply = <&reg_vcc_3v3>;
pinctrl-0 = <&mmc0_pins>;
pinctrl-names = "default";
status = "okay";
};
&mmc1 {
bus-width = <4>;
mmc-pwrseq = <&wifi_pwrseq>;
non-removable;
vmmc-supply = <&reg_vcc_3v3>;
vqmmc-supply = <&reg_vcc_3v3>;
pinctrl-0 = <&mmc1_pins>;
pinctrl-names = "default";
status = "okay";
rtl8189ftv: wifi@1 {
reg = <1>;
interrupt-parent = <&pio>;
interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 */
interrupt-names = "host-wake";
};
};
&ohci1 {
status = "okay";
};
&pio {
vcc-pe-supply = <&reg_avdd2v8>;
};
&uart3 {
pinctrl-0 = <&uart3_pb_pins>;
pinctrl-names = "default";
status = "okay";
};
&usb_otg {
dr_mode = "peripheral";
status = "okay";
};
&usbphy {
usb1_vbus-supply = <&reg_vcc>;
status = "okay";
};

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// SPDX-License-Identifier: (GPL-2.0+ or MIT)
// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
#define SOC_PERIPHERAL_IRQ(nr) (nr + 16)
#include "sunxi-d1s-t113.dtsi"
/ {
cpus {
timebase-frequency = <24000000>;
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "thead,c906", "riscv";
device_type = "cpu";
reg = <0>;
clocks = <&ccu CLK_RISCV>;
d-cache-block-size = <64>;
d-cache-sets = <256>;
d-cache-size = <32768>;
i-cache-block-size = <64>;
i-cache-sets = <128>;
i-cache-size = <32768>;
mmu-type = "riscv,sv39";
operating-points-v2 = <&opp_table_cpu>;
riscv,isa = "rv64imafdc";
#cooling-cells = <2>;
cpu0_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
};
};
opp_table_cpu: opp-table-cpu {
compatible = "operating-points-v2";
opp-408000000 {
opp-hz = /bits/ 64 <408000000>;
opp-microvolt = <900000 900000 1100000>;
};
opp-1080000000 {
opp-hz = /bits/ 64 <1008000000>;
opp-microvolt = <900000 900000 1100000>;
};
};
soc {
interrupt-parent = <&plic>;
riscv_wdt: watchdog@6011000 {
compatible = "allwinner,sun20i-d1-wdt";
reg = <0x6011000 0x20>;
interrupts = <SOC_PERIPHERAL_IRQ(131) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&dcxo>, <&rtc CLK_OSC32K>;
clock-names = "hosc", "losc";
};
plic: interrupt-controller@10000000 {
compatible = "allwinner,sun20i-d1-plic",
"thead,c900-plic";
reg = <0x10000000 0x4000000>;
interrupts-extended = <&cpu0_intc 11>,
<&cpu0_intc 9>;
interrupt-controller;
riscv,ndev = <175>;
#address-cells = <0>;
#interrupt-cells = <2>;
};
};
};

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// SPDX-License-Identifier: (GPL-2.0+ or MIT)
// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
/ {
soc {
dsp_wdt: watchdog@1700400 {
compatible = "allwinner,sun20i-d1-wdt";
reg = <0x1700400 0x20>;
interrupts = <SOC_PERIPHERAL_IRQ(122) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&dcxo>, <&rtc CLK_OSC32K>;
clock-names = "hosc", "losc";
status = "reserved";
};
};
};

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// SPDX-License-Identifier: (GPL-2.0+ or MIT)
// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
#include <dt-bindings/clock/sun6i-rtc.h>
#include <dt-bindings/clock/sun8i-de2.h>
#include <dt-bindings/clock/sun8i-tcon-top.h>
#include <dt-bindings/clock/sun20i-d1-ccu.h>
#include <dt-bindings/clock/sun20i-d1-r-ccu.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/reset/sun8i-de2.h>
#include <dt-bindings/reset/sun20i-d1-ccu.h>
#include <dt-bindings/reset/sun20i-d1-r-ccu.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
dcxo: dcxo-clk {
compatible = "fixed-clock";
clock-output-names = "dcxo";
#clock-cells = <0>;
};
de: display-engine {
compatible = "allwinner,sun20i-d1-display-engine";
allwinner,pipelines = <&mixer0>, <&mixer1>;
status = "disabled";
};
soc {
compatible = "simple-bus";
ranges;
dma-noncoherent;
#address-cells = <1>;
#size-cells = <1>;
pio: pinctrl@2000000 {
compatible = "allwinner,sun20i-d1-pinctrl";
reg = <0x2000000 0x800>;
interrupts = <SOC_PERIPHERAL_IRQ(69) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(71) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(73) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(75) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(77) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(79) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_APB0>,
<&dcxo>,
<&rtc CLK_OSC32K>;
clock-names = "apb", "hosc", "losc";
gpio-controller;
interrupt-controller;
#gpio-cells = <3>;
#interrupt-cells = <3>;
/omit-if-no-ref/
clk_pg11_pin: clk-pg11-pin {
pins = "PG11";
function = "clk";
};
/omit-if-no-ref/
dsi_4lane_pins: dsi-4lane-pins {
pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5",
"PD6", "PD7", "PD8", "PD9";
drive-strength = <30>;
function = "dsi";
};
/omit-if-no-ref/
lcd_rgb666_pins: lcd-rgb666-pins {
pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5",
"PD6", "PD7", "PD8", "PD9", "PD10", "PD11",
"PD12", "PD13", "PD14", "PD15", "PD16", "PD17",
"PD18", "PD19", "PD20", "PD21";
function = "lcd0";
};
/omit-if-no-ref/
mmc0_pins: mmc0-pins {
pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
function = "mmc0";
};
/omit-if-no-ref/
mmc1_pins: mmc1-pins {
pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5";
function = "mmc1";
};
/omit-if-no-ref/
mmc2_pins: mmc2-pins {
pins = "PC2", "PC3", "PC4", "PC5", "PC6", "PC7";
function = "mmc2";
};
/omit-if-no-ref/
rgmii_pe_pins: rgmii-pe-pins {
pins = "PE0", "PE1", "PE2", "PE3", "PE4",
"PE5", "PE6", "PE7", "PE8", "PE9",
"PE11", "PE12", "PE13", "PE14", "PE15";
function = "emac";
};
/omit-if-no-ref/
rmii_pe_pins: rmii-pe-pins {
pins = "PE0", "PE1", "PE2", "PE3", "PE4",
"PE5", "PE6", "PE7", "PE8", "PE9";
function = "emac";
};
/omit-if-no-ref/
uart1_pg6_pins: uart1-pg6-pins {
pins = "PG6", "PG7";
function = "uart1";
};
/omit-if-no-ref/
uart1_pg8_rts_cts_pins: uart1-pg8-rts-cts-pins {
pins = "PG8", "PG9";
function = "uart1";
};
/omit-if-no-ref/
uart3_pb_pins: uart3-pb-pins {
pins = "PB6", "PB7";
function = "uart3";
};
};
ccu: clock-controller@2001000 {
compatible = "allwinner,sun20i-d1-ccu";
reg = <0x2001000 0x1000>;
clocks = <&dcxo>,
<&rtc CLK_OSC32K>,
<&rtc CLK_IOSC>;
clock-names = "hosc", "losc", "iosc";
#clock-cells = <1>;
#reset-cells = <1>;
};
dmic: dmic@2031000 {
compatible = "allwinner,sun20i-d1-dmic",
"allwinner,sun50i-h6-dmic";
reg = <0x2031000 0x400>;
interrupts = <SOC_PERIPHERAL_IRQ(24) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_DMIC>,
<&ccu CLK_DMIC>;
clock-names = "bus", "mod";
resets = <&ccu RST_BUS_DMIC>;
dmas = <&dma 8>;
dma-names = "rx";
status = "disabled";
#sound-dai-cells = <0>;
};
i2s1: i2s@2033000 {
compatible = "allwinner,sun20i-d1-i2s",
"allwinner,sun50i-r329-i2s";
reg = <0x2033000 0x1000>;
interrupts = <SOC_PERIPHERAL_IRQ(27) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2S1>,
<&ccu CLK_I2S1>;
clock-names = "apb", "mod";
resets = <&ccu RST_BUS_I2S1>;
dmas = <&dma 4>, <&dma 4>;
dma-names = "rx", "tx";
status = "disabled";
#sound-dai-cells = <0>;
};
i2s2: i2s@2034000 {
compatible = "allwinner,sun20i-d1-i2s",
"allwinner,sun50i-r329-i2s";
reg = <0x2034000 0x1000>;
interrupts = <SOC_PERIPHERAL_IRQ(28) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2S2>,
<&ccu CLK_I2S2>;
clock-names = "apb", "mod";
resets = <&ccu RST_BUS_I2S2>;
dmas = <&dma 5>, <&dma 5>;
dma-names = "rx", "tx";
status = "disabled";
#sound-dai-cells = <0>;
};
timer: timer@2050000 {
compatible = "allwinner,sun20i-d1-timer",
"allwinner,sun8i-a23-timer";
reg = <0x2050000 0xa0>;
interrupts = <SOC_PERIPHERAL_IRQ(59) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(60) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&dcxo>;
};
wdt: watchdog@20500a0 {
compatible = "allwinner,sun20i-d1-wdt-reset",
"allwinner,sun20i-d1-wdt";
reg = <0x20500a0 0x20>;
interrupts = <SOC_PERIPHERAL_IRQ(63) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&dcxo>, <&rtc CLK_OSC32K>;
clock-names = "hosc", "losc";
status = "reserved";
};
uart0: serial@2500000 {
compatible = "snps,dw-apb-uart";
reg = <0x2500000 0x400>;
reg-io-width = <4>;
reg-shift = <2>;
interrupts = <SOC_PERIPHERAL_IRQ(2) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_UART0>;
resets = <&ccu RST_BUS_UART0>;
dmas = <&dma 14>, <&dma 14>;
dma-names = "rx", "tx";
status = "disabled";
};
uart1: serial@2500400 {
compatible = "snps,dw-apb-uart";
reg = <0x2500400 0x400>;
reg-io-width = <4>;
reg-shift = <2>;
interrupts = <SOC_PERIPHERAL_IRQ(3) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_UART1>;
resets = <&ccu RST_BUS_UART1>;
dmas = <&dma 15>, <&dma 15>;
dma-names = "rx", "tx";
status = "disabled";
};
uart2: serial@2500800 {
compatible = "snps,dw-apb-uart";
reg = <0x2500800 0x400>;
reg-io-width = <4>;
reg-shift = <2>;
interrupts = <SOC_PERIPHERAL_IRQ(4) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_UART2>;
resets = <&ccu RST_BUS_UART2>;
dmas = <&dma 16>, <&dma 16>;
dma-names = "rx", "tx";
status = "disabled";
};
uart3: serial@2500c00 {
compatible = "snps,dw-apb-uart";
reg = <0x2500c00 0x400>;
reg-io-width = <4>;
reg-shift = <2>;
interrupts = <SOC_PERIPHERAL_IRQ(5) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_UART3>;
resets = <&ccu RST_BUS_UART3>;
dmas = <&dma 17>, <&dma 17>;
dma-names = "rx", "tx";
status = "disabled";
};
uart4: serial@2501000 {
compatible = "snps,dw-apb-uart";
reg = <0x2501000 0x400>;
reg-io-width = <4>;
reg-shift = <2>;
interrupts = <SOC_PERIPHERAL_IRQ(6) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_UART4>;
resets = <&ccu RST_BUS_UART4>;
dmas = <&dma 18>, <&dma 18>;
dma-names = "rx", "tx";
status = "disabled";
};
uart5: serial@2501400 {
compatible = "snps,dw-apb-uart";
reg = <0x2501400 0x400>;
reg-io-width = <4>;
reg-shift = <2>;
interrupts = <SOC_PERIPHERAL_IRQ(7) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_UART5>;
resets = <&ccu RST_BUS_UART5>;
dmas = <&dma 19>, <&dma 19>;
dma-names = "rx", "tx";
status = "disabled";
};
i2c0: i2c@2502000 {
compatible = "allwinner,sun20i-d1-i2c",
"allwinner,sun8i-v536-i2c",
"allwinner,sun6i-a31-i2c";
reg = <0x2502000 0x400>;
interrupts = <SOC_PERIPHERAL_IRQ(9) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2C0>;
resets = <&ccu RST_BUS_I2C0>;
dmas = <&dma 43>, <&dma 43>;
dma-names = "rx", "tx";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
i2c1: i2c@2502400 {
compatible = "allwinner,sun20i-d1-i2c",
"allwinner,sun8i-v536-i2c",
"allwinner,sun6i-a31-i2c";
reg = <0x2502400 0x400>;
interrupts = <SOC_PERIPHERAL_IRQ(10) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2C1>;
resets = <&ccu RST_BUS_I2C1>;
dmas = <&dma 44>, <&dma 44>;
dma-names = "rx", "tx";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
i2c2: i2c@2502800 {
compatible = "allwinner,sun20i-d1-i2c",
"allwinner,sun8i-v536-i2c",
"allwinner,sun6i-a31-i2c";
reg = <0x2502800 0x400>;
interrupts = <SOC_PERIPHERAL_IRQ(11) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2C2>;
resets = <&ccu RST_BUS_I2C2>;
dmas = <&dma 45>, <&dma 45>;
dma-names = "rx", "tx";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
i2c3: i2c@2502c00 {
compatible = "allwinner,sun20i-d1-i2c",
"allwinner,sun8i-v536-i2c",
"allwinner,sun6i-a31-i2c";
reg = <0x2502c00 0x400>;
interrupts = <SOC_PERIPHERAL_IRQ(12) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2C3>;
resets = <&ccu RST_BUS_I2C3>;
dmas = <&dma 46>, <&dma 46>;
dma-names = "rx", "tx";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
syscon: syscon@3000000 {
compatible = "allwinner,sun20i-d1-system-control";
reg = <0x3000000 0x1000>;
ranges;
#address-cells = <1>;
#size-cells = <1>;
};
dma: dma-controller@3002000 {
compatible = "allwinner,sun20i-d1-dma";
reg = <0x3002000 0x1000>;
interrupts = <SOC_PERIPHERAL_IRQ(50) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>;
clock-names = "bus", "mbus";
resets = <&ccu RST_BUS_DMA>;
dma-channels = <16>;
dma-requests = <48>;
#dma-cells = <1>;
};
sid: efuse@3006000 {
compatible = "allwinner,sun20i-d1-sid";
reg = <0x3006000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
};
mbus: dram-controller@3102000 {
compatible = "allwinner,sun20i-d1-mbus";
reg = <0x3102000 0x1000>,
<0x3103000 0x1000>;
reg-names = "mbus", "dram";
interrupts = <SOC_PERIPHERAL_IRQ(43) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_MBUS>,
<&ccu CLK_DRAM>,
<&ccu CLK_BUS_DRAM>;
clock-names = "mbus", "dram", "bus";
dma-ranges = <0 0x40000000 0x80000000>;
#address-cells = <1>;
#size-cells = <1>;
#interconnect-cells = <1>;
};
mmc0: mmc@4020000 {
compatible = "allwinner,sun20i-d1-mmc";
reg = <0x4020000 0x1000>;
interrupts = <SOC_PERIPHERAL_IRQ(40) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
clock-names = "ahb", "mmc";
resets = <&ccu RST_BUS_MMC0>;
reset-names = "ahb";
cap-sd-highspeed;
max-frequency = <150000000>;
no-mmc;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
mmc1: mmc@4021000 {
compatible = "allwinner,sun20i-d1-mmc";
reg = <0x4021000 0x1000>;
interrupts = <SOC_PERIPHERAL_IRQ(41) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
clock-names = "ahb", "mmc";
resets = <&ccu RST_BUS_MMC1>;
reset-names = "ahb";
cap-sd-highspeed;
max-frequency = <150000000>;
no-mmc;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
mmc2: mmc@4022000 {
compatible = "allwinner,sun20i-d1-emmc",
"allwinner,sun50i-a100-emmc";
reg = <0x4022000 0x1000>;
interrupts = <SOC_PERIPHERAL_IRQ(42) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
clock-names = "ahb", "mmc";
resets = <&ccu RST_BUS_MMC2>;
reset-names = "ahb";
cap-mmc-highspeed;
max-frequency = <150000000>;
mmc-ddr-1_8v;
mmc-ddr-3_3v;
no-sd;
no-sdio;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
usb_otg: usb@4100000 {
compatible = "allwinner,sun20i-d1-musb",
"allwinner,sun8i-a33-musb";
reg = <0x4100000 0x400>;
interrupts = <SOC_PERIPHERAL_IRQ(29) IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mc";
clocks = <&ccu CLK_BUS_OTG>;
resets = <&ccu RST_BUS_OTG>;
extcon = <&usbphy 0>;
phys = <&usbphy 0>;
phy-names = "usb";
status = "disabled";
};
usbphy: phy@4100400 {
compatible = "allwinner,sun20i-d1-usb-phy";
reg = <0x4100400 0x100>,
<0x4101800 0x100>,
<0x4200800 0x100>;
reg-names = "phy_ctrl",
"pmu0",
"pmu1";
clocks = <&dcxo>,
<&dcxo>;
clock-names = "usb0_phy",
"usb1_phy";
resets = <&ccu RST_USB_PHY0>,
<&ccu RST_USB_PHY1>;
reset-names = "usb0_reset",
"usb1_reset";
status = "disabled";
#phy-cells = <1>;
};
ehci0: usb@4101000 {
compatible = "allwinner,sun20i-d1-ehci",
"generic-ehci";
reg = <0x4101000 0x100>;
interrupts = <SOC_PERIPHERAL_IRQ(30) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_OHCI0>,
<&ccu CLK_BUS_EHCI0>,
<&ccu CLK_USB_OHCI0>;
resets = <&ccu RST_BUS_OHCI0>,
<&ccu RST_BUS_EHCI0>;
phys = <&usbphy 0>;
phy-names = "usb";
status = "disabled";
};
ohci0: usb@4101400 {
compatible = "allwinner,sun20i-d1-ohci",
"generic-ohci";
reg = <0x4101400 0x100>;
interrupts = <SOC_PERIPHERAL_IRQ(31) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_OHCI0>,
<&ccu CLK_USB_OHCI0>;
resets = <&ccu RST_BUS_OHCI0>;
phys = <&usbphy 0>;
phy-names = "usb";
status = "disabled";
};
ehci1: usb@4200000 {
compatible = "allwinner,sun20i-d1-ehci",
"generic-ehci";
reg = <0x4200000 0x100>;
interrupts = <SOC_PERIPHERAL_IRQ(33) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_OHCI1>,
<&ccu CLK_BUS_EHCI1>,
<&ccu CLK_USB_OHCI1>;
resets = <&ccu RST_BUS_OHCI1>,
<&ccu RST_BUS_EHCI1>;
phys = <&usbphy 1>;
phy-names = "usb";
status = "disabled";
};
ohci1: usb@4200400 {
compatible = "allwinner,sun20i-d1-ohci",
"generic-ohci";
reg = <0x4200400 0x100>;
interrupts = <SOC_PERIPHERAL_IRQ(34) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_OHCI1>,
<&ccu CLK_USB_OHCI1>;
resets = <&ccu RST_BUS_OHCI1>;
phys = <&usbphy 1>;
phy-names = "usb";
status = "disabled";
};
emac: ethernet@4500000 {
compatible = "allwinner,sun20i-d1-emac",
"allwinner,sun50i-a64-emac";
reg = <0x4500000 0x10000>;
interrupts = <SOC_PERIPHERAL_IRQ(46) IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
clocks = <&ccu CLK_BUS_EMAC>;
clock-names = "stmmaceth";
resets = <&ccu RST_BUS_EMAC>;
reset-names = "stmmaceth";
syscon = <&syscon>;
status = "disabled";
mdio: mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
};
};
display_clocks: clock-controller@5000000 {
compatible = "allwinner,sun20i-d1-de2-clk",
"allwinner,sun50i-h5-de2-clk";
reg = <0x5000000 0x10000>;
clocks = <&ccu CLK_BUS_DE>, <&ccu CLK_DE>;
clock-names = "bus", "mod";
resets = <&ccu RST_BUS_DE>;
#clock-cells = <1>;
#reset-cells = <1>;
};
mixer0: mixer@5100000 {
compatible = "allwinner,sun20i-d1-de2-mixer-0";
reg = <0x5100000 0x100000>;
clocks = <&display_clocks CLK_BUS_MIXER0>,
<&display_clocks CLK_MIXER0>;
clock-names = "bus", "mod";
resets = <&display_clocks RST_MIXER0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
mixer0_out: port@1 {
reg = <1>;
mixer0_out_tcon_top_mixer0: endpoint {
remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
};
};
};
};
mixer1: mixer@5200000 {
compatible = "allwinner,sun20i-d1-de2-mixer-1";
reg = <0x5200000 0x100000>;
clocks = <&display_clocks CLK_BUS_MIXER1>,
<&display_clocks CLK_MIXER1>;
clock-names = "bus", "mod";
resets = <&display_clocks RST_MIXER1>;
ports {
#address-cells = <1>;
#size-cells = <0>;
mixer1_out: port@1 {
reg = <1>;
mixer1_out_tcon_top_mixer1: endpoint {
remote-endpoint = <&tcon_top_mixer1_in_mixer1>;
};
};
};
};
dsi: dsi@5450000 {
compatible = "allwinner,sun20i-d1-mipi-dsi",
"allwinner,sun50i-a100-mipi-dsi";
reg = <0x5450000 0x1000>;
interrupts = <SOC_PERIPHERAL_IRQ(92) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_MIPI_DSI>,
<&tcon_top CLK_TCON_TOP_DSI>;
clock-names = "bus", "mod";
resets = <&ccu RST_BUS_MIPI_DSI>;
phys = <&dphy>;
phy-names = "dphy";
status = "disabled";
port {
dsi_in_tcon_lcd0: endpoint {
remote-endpoint = <&tcon_lcd0_out_dsi>;
};
};
};
dphy: phy@5451000 {
compatible = "allwinner,sun20i-d1-mipi-dphy",
"allwinner,sun50i-a100-mipi-dphy";
reg = <0x5451000 0x1000>;
interrupts = <SOC_PERIPHERAL_IRQ(92) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_MIPI_DSI>,
<&ccu CLK_MIPI_DSI>;
clock-names = "bus", "mod";
resets = <&ccu RST_BUS_MIPI_DSI>;
#phy-cells = <0>;
};
tcon_top: tcon-top@5460000 {
compatible = "allwinner,sun20i-d1-tcon-top";
reg = <0x5460000 0x1000>;
clocks = <&ccu CLK_BUS_DPSS_TOP>,
<&ccu CLK_TCON_TV>,
<&ccu CLK_TVE>,
<&ccu CLK_TCON_LCD0>;
clock-names = "bus", "tcon-tv0", "tve0", "dsi";
clock-output-names = "tcon-top-tv0", "tcon-top-dsi";
resets = <&ccu RST_BUS_DPSS_TOP>;
#clock-cells = <1>;
ports {
#address-cells = <1>;
#size-cells = <0>;
tcon_top_mixer0_in: port@0 {
reg = <0>;
tcon_top_mixer0_in_mixer0: endpoint {
remote-endpoint = <&mixer0_out_tcon_top_mixer0>;
};
};
tcon_top_mixer0_out: port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
tcon_top_mixer0_out_tcon_lcd0: endpoint@0 {
reg = <0>;
remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer0>;
};
tcon_top_mixer0_out_tcon_tv0: endpoint@2 {
reg = <2>;
remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>;
};
};
tcon_top_mixer1_in: port@2 {
reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
tcon_top_mixer1_in_mixer1: endpoint@1 {
reg = <1>;
remote-endpoint = <&mixer1_out_tcon_top_mixer1>;
};
};
tcon_top_mixer1_out: port@3 {
reg = <3>;
#address-cells = <1>;
#size-cells = <0>;
tcon_top_mixer1_out_tcon_lcd0: endpoint@0 {
reg = <0>;
remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer1>;
};
tcon_top_mixer1_out_tcon_tv0: endpoint@2 {
reg = <2>;
remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>;
};
};
tcon_top_hdmi_in: port@4 {
reg = <4>;
tcon_top_hdmi_in_tcon_tv0: endpoint {
remote-endpoint = <&tcon_tv0_out_tcon_top_hdmi>;
};
};
tcon_top_hdmi_out: port@5 {
reg = <5>;
};
};
};
tcon_lcd0: lcd-controller@5461000 {
compatible = "allwinner,sun20i-d1-tcon-lcd";
reg = <0x5461000 0x1000>;
interrupts = <SOC_PERIPHERAL_IRQ(90) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_TCON_LCD0>,
<&ccu CLK_TCON_LCD0>;
clock-names = "ahb", "tcon-ch0";
clock-output-names = "tcon-pixel-clock";
resets = <&ccu RST_BUS_TCON_LCD0>,
<&ccu RST_BUS_LVDS0>;
reset-names = "lcd", "lvds";
#clock-cells = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
tcon_lcd0_in: port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
tcon_lcd0_in_tcon_top_mixer0: endpoint@0 {
reg = <0>;
remote-endpoint = <&tcon_top_mixer0_out_tcon_lcd0>;
};
tcon_lcd0_in_tcon_top_mixer1: endpoint@1 {
reg = <1>;
remote-endpoint = <&tcon_top_mixer1_out_tcon_lcd0>;
};
};
tcon_lcd0_out: port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
tcon_lcd0_out_dsi: endpoint@1 {
reg = <1>;
remote-endpoint = <&dsi_in_tcon_lcd0>;
};
};
};
};
tcon_tv0: lcd-controller@5470000 {
compatible = "allwinner,sun20i-d1-tcon-tv";
reg = <0x5470000 0x1000>;
interrupts = <SOC_PERIPHERAL_IRQ(91) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_TCON_TV>,
<&tcon_top CLK_TCON_TOP_TV0>;
clock-names = "ahb", "tcon-ch1";
resets = <&ccu RST_BUS_TCON_TV>;
reset-names = "lcd";
ports {
#address-cells = <1>;
#size-cells = <0>;
tcon_tv0_in: port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
tcon_tv0_in_tcon_top_mixer0: endpoint@0 {
reg = <0>;
remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>;
};
tcon_tv0_in_tcon_top_mixer1: endpoint@1 {
reg = <1>;
remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>;
};
};
tcon_tv0_out: port@1 {
reg = <1>;
tcon_tv0_out_tcon_top_hdmi: endpoint {
remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>;
};
};
};
};
ppu: power-controller@7001000 {
compatible = "allwinner,sun20i-d1-ppu";
reg = <0x7001000 0x1000>;
clocks = <&r_ccu CLK_BUS_R_PPU>;
resets = <&r_ccu RST_BUS_R_PPU>;
#power-domain-cells = <1>;
};
r_ccu: clock-controller@7010000 {
compatible = "allwinner,sun20i-d1-r-ccu";
reg = <0x7010000 0x400>;
clocks = <&dcxo>,
<&rtc CLK_OSC32K>,
<&rtc CLK_IOSC>,
<&ccu CLK_PLL_PERIPH0_DIV3>;
clock-names = "hosc", "losc", "iosc", "pll-periph";
#clock-cells = <1>;
#reset-cells = <1>;
};
rtc: rtc@7090000 {
compatible = "allwinner,sun20i-d1-rtc",
"allwinner,sun50i-r329-rtc";
reg = <0x7090000 0x400>;
interrupts = <SOC_PERIPHERAL_IRQ(144) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&r_ccu CLK_BUS_R_RTC>,
<&dcxo>,
<&r_ccu CLK_R_AHB>;
clock-names = "bus", "hosc", "ahb";
#clock-cells = <1>;
};
};
};