Merge branches 'clk-samsung', 'clk-hisi3670' and 'clk-at91-div-0' into clk-next
- Hisilicon 3670 SoC support * clk-samsung: dt-bindings: clock: samsung: Add SPDX license identifiers clk: samsung: Use clk_hw API for calling clk framework from clk notifiers clk: samsung: exynos5420: Enable PERIS clocks for suspend clk: samsung: exynos5420: Define CLK_SECKEY gate clock only or Exynos5420 clk: samsung: exynos5433: Keep sclk_uart clocks enabled in suspend clk: samsung: Remove obsolete code for Exynos4412 ISP clocks clk: samsung: exynos5433: Add suspend state for TOP, CPIF & PERIC CMUs clk: samsung: Use NOIRQ stage for Exynos5433 clocks suspend/resume clk: samsung: exynos5420: Use generic helper for handling suspend/resume clk: samsung: exynos4: Use generic helper for handling suspend/resume clk: samsung: Add support for setting registers state before suspend clk: samsung: exynos5250: Use generic helper for handling suspend/resume clk: samsung: s5pv210: Use generic helper for handling suspend/resume clk: samsung: s3c64xx: Use generic helper for handling suspend/resume clk: samsung: s3c2443: Use generic helper for handling suspend/resume clk: samsung: s3c2412: Use generic helper for handling suspend/resume clk: samsung: s3c2410: Use generic helper for handling suspend/resume clk: samsung: Remove excessive include * clk-hisi3670: clk: hisilicon: Add clock driver for Hi3670 SoC dt-bindings: clk: hisilicon: Add bindings for Hi3670 clk * clk-at91-div-0: clk: at91: Fix division by zero in PLL recalc_rate()
This commit is contained in:
Stephen Boyd
commit
ffd3b1c880
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@ -0,0 +1,43 @@
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* Hisilicon Hi3670 Clock Controller
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The Hi3670 clock controller generates and supplies clock to various
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controllers within the Hi3670 SoC.
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Required Properties:
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- compatible: the compatible should be one of the following strings to
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indicate the clock controller functionality.
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- "hisilicon,hi3670-crgctrl"
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- "hisilicon,hi3670-pctrl"
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- "hisilicon,hi3670-pmuctrl"
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- "hisilicon,hi3670-sctrl"
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- "hisilicon,hi3670-iomcu"
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- "hisilicon,hi3670-media1-crg"
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- "hisilicon,hi3670-media2-crg"
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- reg: physical base address of the controller and length of memory mapped
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region.
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- #clock-cells: should be 1.
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Each clock is assigned an identifier and client nodes use this identifier
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to specify the clock which they consume.
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All these identifier could be found in <dt-bindings/clock/hi3670-clock.h>.
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Examples:
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crg_ctrl: clock-controller@fff35000 {
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compatible = "hisilicon,hi3670-crgctrl", "syscon";
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reg = <0x0 0xfff35000 0x0 0x1000>;
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#clock-cells = <1>;
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};
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uart0: serial@fdf02000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0 0xfdf02000 0x0 0x1000>;
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interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&crg_ctrl HI3670_CLK_GATE_UART0>,
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<&crg_ctrl HI3670_PCLK>;
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clock-names = "uartclk", "apb_pclk";
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};
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@ -133,6 +133,9 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
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{
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struct clk_pll *pll = to_clk_pll(hw);
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if (!pll->div || !pll->mul)
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return 0;
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return (parent_rate / pll->div) * (pll->mul + 1);
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}
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@ -21,6 +21,13 @@ config COMMON_CLK_HI3660
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help
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Build the clock driver for hi3660.
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config COMMON_CLK_HI3670
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bool "Hi3670 Clock Driver"
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depends on ARCH_HISI || COMPILE_TEST
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default ARCH_HISI
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help
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Build the clock driver for hi3670.
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config COMMON_CLK_HI3798CV200
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tristate "Hi3798CV200 Clock Driver"
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depends on ARCH_HISI || COMPILE_TEST
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@ -11,6 +11,7 @@ obj-$(CONFIG_ARCH_HIX5HD2) += clk-hix5hd2.o
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obj-$(CONFIG_COMMON_CLK_HI3516CV300) += crg-hi3516cv300.o
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obj-$(CONFIG_COMMON_CLK_HI3519) += clk-hi3519.o
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obj-$(CONFIG_COMMON_CLK_HI3660) += clk-hi3660.o
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obj-$(CONFIG_COMMON_CLK_HI3670) += clk-hi3670.o
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obj-$(CONFIG_COMMON_CLK_HI3798CV200) += crg-hi3798cv200.o
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obj-$(CONFIG_COMMON_CLK_HI6220) += clk-hi6220.o
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obj-$(CONFIG_RESET_HISI) += reset.o
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File diff suppressed because it is too large
Load Diff
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@ -152,7 +152,7 @@ static int exynos_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
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struct exynos_cpuclk *cpuclk, void __iomem *base)
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{
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const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg;
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unsigned long alt_prate = clk_get_rate(cpuclk->alt_parent);
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unsigned long alt_prate = clk_hw_get_rate(cpuclk->alt_parent);
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unsigned long alt_div = 0, alt_div_mask = DIV_MASK;
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unsigned long div0, div1 = 0, mux_reg;
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unsigned long flags;
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@ -280,7 +280,7 @@ static int exynos5433_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
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struct exynos_cpuclk *cpuclk, void __iomem *base)
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{
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const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg;
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unsigned long alt_prate = clk_get_rate(cpuclk->alt_parent);
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unsigned long alt_prate = clk_hw_get_rate(cpuclk->alt_parent);
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unsigned long alt_div = 0, alt_div_mask = DIV_MASK;
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unsigned long div0, div1 = 0, mux_reg;
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unsigned long flags;
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@ -432,7 +432,7 @@ int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
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else
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cpuclk->clk_nb.notifier_call = exynos_cpuclk_notifier_cb;
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cpuclk->alt_parent = __clk_lookup(alt_parent);
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cpuclk->alt_parent = __clk_get_hw(__clk_lookup(alt_parent));
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if (!cpuclk->alt_parent) {
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pr_err("%s: could not lookup alternate parent %s\n",
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__func__, alt_parent);
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@ -49,7 +49,7 @@ struct exynos_cpuclk_cfg_data {
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*/
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struct exynos_cpuclk {
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struct clk_hw hw;
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struct clk *alt_parent;
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struct clk_hw *alt_parent;
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void __iomem *ctrl_base;
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spinlock_t *lock;
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const struct exynos_cpuclk_cfg_data *cfg;
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@ -15,7 +15,6 @@
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#include <linux/clk-provider.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/syscore_ops.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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@ -12,7 +12,6 @@
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <linux/syscore_ops.h>
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#include <dt-bindings/clock/exynos3250.h>
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@ -16,7 +16,6 @@
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#include <linux/clk-provider.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/syscore_ops.h>
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#include "clk.h"
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#include "clk-cpu.h"
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@ -123,10 +122,6 @@
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#define CLKOUT_CMU_CPU 0x14a00
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#define PWR_CTRL1 0x15020
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#define E4X12_PWR_CTRL2 0x15024
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#define E4X12_DIV_ISP0 0x18300
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#define E4X12_DIV_ISP1 0x18304
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#define E4X12_GATE_ISP0 0x18800
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#define E4X12_GATE_ISP1 0x18804
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/* Below definitions are used for PWR_CTRL settings */
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#define PWR_CTRL1_CORE2_DOWN_RATIO(x) (((x) & 0x7) << 28)
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@ -157,14 +152,6 @@ enum exynos4_plls {
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static void __iomem *reg_base;
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static enum exynos4_soc exynos4_soc;
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/*
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* Support for CMU save/restore across system suspends
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*/
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#ifdef CONFIG_PM_SLEEP
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static struct samsung_clk_reg_dump *exynos4_save_common;
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static struct samsung_clk_reg_dump *exynos4_save_soc;
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static struct samsung_clk_reg_dump *exynos4_save_pll;
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/*
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* list of controller registers to be saved and restored during a
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* suspend/resume cycle.
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@ -192,7 +179,7 @@ static const unsigned long exynos4x12_clk_save[] __initconst = {
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E4X12_PWR_CTRL2,
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};
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static const unsigned long exynos4_clk_pll_regs[] __initconst = {
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static const unsigned long exynos4_clk_regs[] __initconst = {
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EPLL_LOCK,
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VPLL_LOCK,
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EPLL_CON0,
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@ -201,9 +188,6 @@ static const unsigned long exynos4_clk_pll_regs[] __initconst = {
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VPLL_CON0,
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VPLL_CON1,
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VPLL_CON2,
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};
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static const unsigned long exynos4_clk_regs[] __initconst = {
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SRC_LEFTBUS,
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DIV_LEFTBUS,
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GATE_IP_LEFTBUS,
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@ -276,6 +260,8 @@ static const unsigned long exynos4_clk_regs[] __initconst = {
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};
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static const struct samsung_clk_reg_dump src_mask_suspend[] = {
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{ .offset = VPLL_CON0, .value = 0x80600302, },
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{ .offset = EPLL_CON0, .value = 0x806F0302, },
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{ .offset = SRC_MASK_TOP, .value = 0x00000001, },
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{ .offset = SRC_MASK_CAM, .value = 0x11111111, },
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{ .offset = SRC_MASK_TV, .value = 0x00000111, },
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@ -291,123 +277,6 @@ static const struct samsung_clk_reg_dump src_mask_suspend_e4210[] = {
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{ .offset = E4210_SRC_MASK_LCD1, .value = 0x00001111, },
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};
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#define PLL_ENABLED (1 << 31)
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#define PLL_LOCKED (1 << 29)
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static void exynos4_clk_enable_pll(u32 reg)
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{
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u32 pll_con = readl(reg_base + reg);
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pll_con |= PLL_ENABLED;
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writel(pll_con, reg_base + reg);
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while (!(pll_con & PLL_LOCKED)) {
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cpu_relax();
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pll_con = readl(reg_base + reg);
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}
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}
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static void exynos4_clk_wait_for_pll(u32 reg)
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{
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u32 pll_con;
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pll_con = readl(reg_base + reg);
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if (!(pll_con & PLL_ENABLED))
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return;
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while (!(pll_con & PLL_LOCKED)) {
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cpu_relax();
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pll_con = readl(reg_base + reg);
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}
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}
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static int exynos4_clk_suspend(void)
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{
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samsung_clk_save(reg_base, exynos4_save_common,
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ARRAY_SIZE(exynos4_clk_regs));
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samsung_clk_save(reg_base, exynos4_save_pll,
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ARRAY_SIZE(exynos4_clk_pll_regs));
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exynos4_clk_enable_pll(EPLL_CON0);
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exynos4_clk_enable_pll(VPLL_CON0);
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if (exynos4_soc == EXYNOS4210) {
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samsung_clk_save(reg_base, exynos4_save_soc,
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ARRAY_SIZE(exynos4210_clk_save));
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samsung_clk_restore(reg_base, src_mask_suspend_e4210,
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ARRAY_SIZE(src_mask_suspend_e4210));
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} else {
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samsung_clk_save(reg_base, exynos4_save_soc,
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ARRAY_SIZE(exynos4x12_clk_save));
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}
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samsung_clk_restore(reg_base, src_mask_suspend,
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ARRAY_SIZE(src_mask_suspend));
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return 0;
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}
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static void exynos4_clk_resume(void)
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{
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samsung_clk_restore(reg_base, exynos4_save_pll,
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ARRAY_SIZE(exynos4_clk_pll_regs));
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exynos4_clk_wait_for_pll(EPLL_CON0);
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exynos4_clk_wait_for_pll(VPLL_CON0);
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samsung_clk_restore(reg_base, exynos4_save_common,
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ARRAY_SIZE(exynos4_clk_regs));
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if (exynos4_soc == EXYNOS4210)
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samsung_clk_restore(reg_base, exynos4_save_soc,
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ARRAY_SIZE(exynos4210_clk_save));
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else
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samsung_clk_restore(reg_base, exynos4_save_soc,
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ARRAY_SIZE(exynos4x12_clk_save));
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}
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static struct syscore_ops exynos4_clk_syscore_ops = {
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.suspend = exynos4_clk_suspend,
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.resume = exynos4_clk_resume,
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};
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static void __init exynos4_clk_sleep_init(void)
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{
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exynos4_save_common = samsung_clk_alloc_reg_dump(exynos4_clk_regs,
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ARRAY_SIZE(exynos4_clk_regs));
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if (!exynos4_save_common)
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goto err_warn;
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if (exynos4_soc == EXYNOS4210)
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exynos4_save_soc = samsung_clk_alloc_reg_dump(
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exynos4210_clk_save,
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ARRAY_SIZE(exynos4210_clk_save));
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else
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exynos4_save_soc = samsung_clk_alloc_reg_dump(
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exynos4x12_clk_save,
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ARRAY_SIZE(exynos4x12_clk_save));
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if (!exynos4_save_soc)
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goto err_common;
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exynos4_save_pll = samsung_clk_alloc_reg_dump(exynos4_clk_pll_regs,
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ARRAY_SIZE(exynos4_clk_pll_regs));
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if (!exynos4_save_pll)
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goto err_soc;
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register_syscore_ops(&exynos4_clk_syscore_ops);
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return;
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err_soc:
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kfree(exynos4_save_soc);
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err_common:
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kfree(exynos4_save_common);
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err_warn:
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pr_warn("%s: failed to allocate sleep save data, no sleep support!\n",
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__func__);
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}
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#else
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static void __init exynos4_clk_sleep_init(void) {}
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#endif
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/* list of all parent clock list */
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PNAME(mout_apll_p) = { "fin_pll", "fout_apll", };
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PNAME(mout_mpll_p) = { "fin_pll", "fout_mpll", };
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@ -841,18 +710,6 @@ static const struct samsung_div_clock exynos4x12_div_clks[] __initconst = {
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DIV(0, "div_c2c_aclk", "div_c2c", DIV_DMC1, 12, 3),
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};
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static struct samsung_div_clock exynos4x12_isp_div_clks[] = {
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DIV_F(CLK_DIV_ISP0, "div_isp0", "aclk200", E4X12_DIV_ISP0, 0, 3,
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CLK_GET_RATE_NOCACHE, 0),
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DIV_F(CLK_DIV_ISP1, "div_isp1", "aclk200", E4X12_DIV_ISP0, 4, 3,
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CLK_GET_RATE_NOCACHE, 0),
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DIV(0, "div_mpwm", "div_isp1", E4X12_DIV_ISP1, 0, 3),
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DIV_F(CLK_DIV_MCUISP0, "div_mcuisp0", "aclk400_mcuisp", E4X12_DIV_ISP1,
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4, 3, CLK_GET_RATE_NOCACHE, 0),
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DIV_F(CLK_DIV_MCUISP1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1,
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8, 3, CLK_GET_RATE_NOCACHE, 0),
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};
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/* list of gate clocks supported in all exynos4 soc's */
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static const struct samsung_gate_clock exynos4_gate_clks[] __initconst = {
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GATE(CLK_PPMULEFT, "ppmuleft", "aclk200", GATE_IP_LEFTBUS, 1, 0, 0),
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@ -1150,61 +1007,6 @@ static const struct samsung_gate_clock exynos4x12_gate_clks[] __initconst = {
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0),
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};
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static struct samsung_gate_clock exynos4x12_isp_gate_clks[] = {
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GATE(CLK_FIMC_ISP, "isp", "aclk200", E4X12_GATE_ISP0, 0,
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CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
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GATE(CLK_FIMC_DRC, "drc", "aclk200", E4X12_GATE_ISP0, 1,
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CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
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GATE(CLK_FIMC_FD, "fd", "aclk200", E4X12_GATE_ISP0, 2,
|
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CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
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GATE(CLK_FIMC_LITE0, "lite0", "aclk200", E4X12_GATE_ISP0, 3,
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CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
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GATE(CLK_FIMC_LITE1, "lite1", "aclk200", E4X12_GATE_ISP0, 4,
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CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
|
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GATE(CLK_MCUISP, "mcuisp", "aclk200", E4X12_GATE_ISP0, 5,
|
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CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
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GATE(CLK_GICISP, "gicisp", "aclk200", E4X12_GATE_ISP0, 7,
|
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CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
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GATE(CLK_SMMU_ISP, "smmu_isp", "aclk200", E4X12_GATE_ISP0, 8,
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CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
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GATE(CLK_SMMU_DRC, "smmu_drc", "aclk200", E4X12_GATE_ISP0, 9,
|
||||
CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
|
||||
GATE(CLK_SMMU_FD, "smmu_fd", "aclk200", E4X12_GATE_ISP0, 10,
|
||||
CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
|
||||
GATE(CLK_SMMU_LITE0, "smmu_lite0", "aclk200", E4X12_GATE_ISP0, 11,
|
||||
CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
|
||||
GATE(CLK_SMMU_LITE1, "smmu_lite1", "aclk200", E4X12_GATE_ISP0, 12,
|
||||
CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
|
||||
GATE(CLK_PPMUISPMX, "ppmuispmx", "aclk200", E4X12_GATE_ISP0, 20,
|
||||
CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
|
||||
GATE(CLK_PPMUISPX, "ppmuispx", "aclk200", E4X12_GATE_ISP0, 21,
|
||||
CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
|
||||
GATE(CLK_MCUCTL_ISP, "mcuctl_isp", "aclk200", E4X12_GATE_ISP0, 23,
|
||||
CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
|
||||
GATE(CLK_MPWM_ISP, "mpwm_isp", "aclk200", E4X12_GATE_ISP0, 24,
|
||||
CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
|
||||
GATE(CLK_I2C0_ISP, "i2c0_isp", "aclk200", E4X12_GATE_ISP0, 25,
|
||||
CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
|
||||
GATE(CLK_I2C1_ISP, "i2c1_isp", "aclk200", E4X12_GATE_ISP0, 26,
|
||||
CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
|
||||
GATE(CLK_MTCADC_ISP, "mtcadc_isp", "aclk200", E4X12_GATE_ISP0, 27,
|
||||
CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
|
||||
GATE(CLK_PWM_ISP, "pwm_isp", "aclk200", E4X12_GATE_ISP0, 28,
|
||||
CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
|
||||
GATE(CLK_WDT_ISP, "wdt_isp", "aclk200", E4X12_GATE_ISP0, 30,
|
||||
CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
|
||||
GATE(CLK_UART_ISP, "uart_isp", "aclk200", E4X12_GATE_ISP0, 31,
|
||||
CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
|
||||
GATE(CLK_ASYNCAXIM, "asyncaxim", "aclk200", E4X12_GATE_ISP1, 0,
|
||||
CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
|
||||
GATE(CLK_SMMU_ISPCX, "smmu_ispcx", "aclk200", E4X12_GATE_ISP1, 4,
|
||||
CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
|
||||
GATE(CLK_SPI0_ISP, "spi0_isp", "aclk200", E4X12_GATE_ISP1, 12,
|
||||
CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
|
||||
GATE(CLK_SPI1_ISP, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13,
|
||||
CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
|
||||
};
|
||||
|
||||
/*
|
||||
* The parent of the fin_pll clock is selected by the XOM[0] bit. This bit
|
||||
* resides in chipid register space, outside of the clock controller memory
|
||||
|
|
@ -1504,8 +1306,6 @@ static void __init exynos4_clk_init(struct device_node *np,
|
|||
e4210_armclk_d, ARRAY_SIZE(e4210_armclk_d),
|
||||
CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);
|
||||
} else {
|
||||
struct resource res;
|
||||
|
||||
samsung_clk_register_mux(ctx, exynos4x12_mux_clks,
|
||||
ARRAY_SIZE(exynos4x12_mux_clks));
|
||||
samsung_clk_register_div(ctx, exynos4x12_div_clks,
|
||||
|
|
@ -1516,14 +1316,6 @@ static void __init exynos4_clk_init(struct device_node *np,
|
|||
exynos4x12_fixed_factor_clks,
|
||||
ARRAY_SIZE(exynos4x12_fixed_factor_clks));
|
||||
|
||||
of_address_to_resource(np, 0, &res);
|
||||
if (resource_size(&res) > 0x18000) {
|
||||
samsung_clk_register_div(ctx, exynos4x12_isp_div_clks,
|
||||
ARRAY_SIZE(exynos4x12_isp_div_clks));
|
||||
samsung_clk_register_gate(ctx, exynos4x12_isp_gate_clks,
|
||||
ARRAY_SIZE(exynos4x12_isp_gate_clks));
|
||||
}
|
||||
|
||||
exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
|
||||
mout_core_p4x12[0], mout_core_p4x12[1], 0x14200,
|
||||
e4412_armclk_d, ARRAY_SIZE(e4412_armclk_d),
|
||||
|
|
@ -1532,7 +1324,17 @@ static void __init exynos4_clk_init(struct device_node *np,
|
|||
|
||||
if (soc == EXYNOS4X12)
|
||||
exynos4x12_core_down_clock();
|
||||
exynos4_clk_sleep_init();
|
||||
|
||||
samsung_clk_extended_sleep_init(reg_base,
|
||||
exynos4_clk_regs, ARRAY_SIZE(exynos4_clk_regs),
|
||||
src_mask_suspend, ARRAY_SIZE(src_mask_suspend));
|
||||
if (exynos4_soc == EXYNOS4210)
|
||||
samsung_clk_extended_sleep_init(reg_base,
|
||||
exynos4210_clk_save, ARRAY_SIZE(exynos4210_clk_save),
|
||||
src_mask_suspend_e4210, ARRAY_SIZE(src_mask_suspend_e4210));
|
||||
else
|
||||
samsung_clk_sleep_init(reg_base, exynos4x12_clk_save,
|
||||
ARRAY_SIZE(exynos4x12_clk_save));
|
||||
|
||||
samsung_clk_of_add_provider(np, ctx);
|
||||
|
||||
|
|
|
|||
|
|
@ -14,7 +14,6 @@
|
|||
#include <linux/clk-provider.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/syscore_ops.h>
|
||||
|
||||
#include "clk.h"
|
||||
#include "clk-cpu.h"
|
||||
|
|
@ -111,9 +110,6 @@ enum exynos5250_plls {
|
|||
|
||||
static void __iomem *reg_base;
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static struct samsung_clk_reg_dump *exynos5250_save;
|
||||
|
||||
/*
|
||||
* list of controller registers to be saved and restored during a
|
||||
* suspend/resume cycle.
|
||||
|
|
@ -172,41 +168,6 @@ static const unsigned long exynos5250_clk_regs[] __initconst = {
|
|||
GATE_IP_ISP1,
|
||||
};
|
||||
|
||||
static int exynos5250_clk_suspend(void)
|
||||
{
|
||||
samsung_clk_save(reg_base, exynos5250_save,
|
||||
ARRAY_SIZE(exynos5250_clk_regs));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void exynos5250_clk_resume(void)
|
||||
{
|
||||
samsung_clk_restore(reg_base, exynos5250_save,
|
||||
ARRAY_SIZE(exynos5250_clk_regs));
|
||||
}
|
||||
|
||||
static struct syscore_ops exynos5250_clk_syscore_ops = {
|
||||
.suspend = exynos5250_clk_suspend,
|
||||
.resume = exynos5250_clk_resume,
|
||||
};
|
||||
|
||||
static void __init exynos5250_clk_sleep_init(void)
|
||||
{
|
||||
exynos5250_save = samsung_clk_alloc_reg_dump(exynos5250_clk_regs,
|
||||
ARRAY_SIZE(exynos5250_clk_regs));
|
||||
if (!exynos5250_save) {
|
||||
pr_warn("%s: failed to allocate sleep save data, no sleep support!\n",
|
||||
__func__);
|
||||
return;
|
||||
}
|
||||
|
||||
register_syscore_ops(&exynos5250_clk_syscore_ops);
|
||||
}
|
||||
#else
|
||||
static void __init exynos5250_clk_sleep_init(void) {}
|
||||
#endif
|
||||
|
||||
/* list of all parent clock list */
|
||||
PNAME(mout_apll_p) = { "fin_pll", "fout_apll", };
|
||||
PNAME(mout_cpu_p) = { "mout_apll", "mout_mpll", };
|
||||
|
|
@ -882,7 +843,8 @@ static void __init exynos5250_clk_init(struct device_node *np)
|
|||
PWR_CTRL2_CORE2_UP_RATIO | PWR_CTRL2_CORE1_UP_RATIO);
|
||||
__raw_writel(tmp, reg_base + PWR_CTRL2);
|
||||
|
||||
exynos5250_clk_sleep_init();
|
||||
samsung_clk_sleep_init(reg_base, exynos5250_clk_regs,
|
||||
ARRAY_SIZE(exynos5250_clk_regs));
|
||||
exynos5_subcmus_init(ctx, 1, &exynos5250_disp_subcmu);
|
||||
|
||||
samsung_clk_of_add_provider(np, ctx);
|
||||
|
|
|
|||
|
|
@ -15,7 +15,6 @@
|
|||
#include <linux/clk-provider.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/syscore_ops.h>
|
||||
|
||||
#include "clk.h"
|
||||
#include "clk-cpu.h"
|
||||
|
|
@ -156,10 +155,6 @@ enum exynos5x_plls {
|
|||
static void __iomem *reg_base;
|
||||
static enum exynos5x_soc exynos5x_soc;
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static struct samsung_clk_reg_dump *exynos5x_save;
|
||||
static struct samsung_clk_reg_dump *exynos5800_save;
|
||||
|
||||
/*
|
||||
* list of controller registers to be saved and restored during a
|
||||
* suspend/resume cycle.
|
||||
|
|
@ -281,68 +276,9 @@ static const struct samsung_clk_reg_dump exynos5420_set_clksrc[] = {
|
|||
{ .offset = GATE_BUS_TOP, .value = 0xffffffff, },
|
||||
{ .offset = GATE_BUS_DISP1, .value = 0xffffffff, },
|
||||
{ .offset = GATE_IP_PERIC, .value = 0xffffffff, },
|
||||
{ .offset = GATE_IP_PERIS, .value = 0xffffffff, },
|
||||
};
|
||||
|
||||
static int exynos5420_clk_suspend(void)
|
||||
{
|
||||
samsung_clk_save(reg_base, exynos5x_save,
|
||||
ARRAY_SIZE(exynos5x_clk_regs));
|
||||
|
||||
if (exynos5x_soc == EXYNOS5800)
|
||||
samsung_clk_save(reg_base, exynos5800_save,
|
||||
ARRAY_SIZE(exynos5800_clk_regs));
|
||||
|
||||
samsung_clk_restore(reg_base, exynos5420_set_clksrc,
|
||||
ARRAY_SIZE(exynos5420_set_clksrc));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void exynos5420_clk_resume(void)
|
||||
{
|
||||
samsung_clk_restore(reg_base, exynos5x_save,
|
||||
ARRAY_SIZE(exynos5x_clk_regs));
|
||||
|
||||
if (exynos5x_soc == EXYNOS5800)
|
||||
samsung_clk_restore(reg_base, exynos5800_save,
|
||||
ARRAY_SIZE(exynos5800_clk_regs));
|
||||
}
|
||||
|
||||
static struct syscore_ops exynos5420_clk_syscore_ops = {
|
||||
.suspend = exynos5420_clk_suspend,
|
||||
.resume = exynos5420_clk_resume,
|
||||
};
|
||||
|
||||
static void __init exynos5420_clk_sleep_init(void)
|
||||
{
|
||||
exynos5x_save = samsung_clk_alloc_reg_dump(exynos5x_clk_regs,
|
||||
ARRAY_SIZE(exynos5x_clk_regs));
|
||||
if (!exynos5x_save) {
|
||||
pr_warn("%s: failed to allocate sleep save data, no sleep support!\n",
|
||||
__func__);
|
||||
return;
|
||||
}
|
||||
|
||||
if (exynos5x_soc == EXYNOS5800) {
|
||||
exynos5800_save =
|
||||
samsung_clk_alloc_reg_dump(exynos5800_clk_regs,
|
||||
ARRAY_SIZE(exynos5800_clk_regs));
|
||||
if (!exynos5800_save)
|
||||
goto err_soc;
|
||||
}
|
||||
|
||||
register_syscore_ops(&exynos5420_clk_syscore_ops);
|
||||
return;
|
||||
err_soc:
|
||||
kfree(exynos5x_save);
|
||||
pr_warn("%s: failed to allocate sleep save data, no sleep support!\n",
|
||||
__func__);
|
||||
return;
|
||||
}
|
||||
#else
|
||||
static void __init exynos5420_clk_sleep_init(void) {}
|
||||
#endif
|
||||
|
||||
/* list of all parent clocks */
|
||||
PNAME(mout_mspll_cpu_p) = {"mout_sclk_cpll", "mout_sclk_dpll",
|
||||
"mout_sclk_mpll", "mout_sclk_spll"};
|
||||
|
|
@ -633,6 +569,7 @@ static const struct samsung_div_clock exynos5420_div_clks[] __initconst = {
|
|||
};
|
||||
|
||||
static const struct samsung_gate_clock exynos5420_gate_clks[] __initconst = {
|
||||
GATE(CLK_SECKEY, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0),
|
||||
GATE(CLK_MAU_EPLL, "mau_epll", "mout_mau_epll_clk",
|
||||
SRC_MASK_TOP7, 20, CLK_SET_RATE_PARENT, 0),
|
||||
};
|
||||
|
|
@ -1162,8 +1099,6 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {
|
|||
GATE(CLK_TMU, "tmu", "aclk66_psgen", GATE_IP_PERIS, 21, 0, 0),
|
||||
GATE(CLK_TMU_GPU, "tmu_gpu", "aclk66_psgen", GATE_IP_PERIS, 22, 0, 0),
|
||||
|
||||
GATE(CLK_SECKEY, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0),
|
||||
|
||||
/* GEN Block */
|
||||
GATE(CLK_ROTATOR, "rotator", "mout_user_aclk266", GATE_IP_GEN, 1, 0, 0),
|
||||
GATE(CLK_JPEG, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0),
|
||||
|
|
@ -1540,7 +1475,12 @@ static void __init exynos5x_clk_init(struct device_node *np,
|
|||
mout_kfc_p[0], mout_kfc_p[1], 0x28200,
|
||||
exynos5420_kfcclk_d, ARRAY_SIZE(exynos5420_kfcclk_d), 0);
|
||||
|
||||
exynos5420_clk_sleep_init();
|
||||
samsung_clk_extended_sleep_init(reg_base,
|
||||
exynos5x_clk_regs, ARRAY_SIZE(exynos5x_clk_regs),
|
||||
exynos5420_set_clksrc, ARRAY_SIZE(exynos5420_set_clksrc));
|
||||
if (soc == EXYNOS5800)
|
||||
samsung_clk_sleep_init(reg_base, exynos5800_clk_regs,
|
||||
ARRAY_SIZE(exynos5800_clk_regs));
|
||||
exynos5_subcmus_init(ctx, ARRAY_SIZE(exynos5x_subcmus),
|
||||
exynos5x_subcmus);
|
||||
|
||||
|
|
|
|||
|
|
@ -177,6 +177,17 @@ static const unsigned long top_clk_regs[] __initconst = {
|
|||
ENABLE_CMU_TOP_DIV_STAT,
|
||||
};
|
||||
|
||||
static const struct samsung_clk_reg_dump top_suspend_regs[] = {
|
||||
/* force all aclk clocks enabled */
|
||||
{ ENABLE_ACLK_TOP, 0x67ecffed },
|
||||
/* force all sclk_uart clocks enabled */
|
||||
{ ENABLE_SCLK_TOP_PERIC, 0x38 },
|
||||
/* ISP PLL has to be enabled for suspend: reset value + ENABLE bit */
|
||||
{ ISP_PLL_CON0, 0x85cc0502 },
|
||||
/* ISP PLL has to be enabled for suspend: reset value + ENABLE bit */
|
||||
{ AUD_PLL_CON0, 0x84830202 },
|
||||
};
|
||||
|
||||
/* list of all parent clock list */
|
||||
PNAME(mout_aud_pll_p) = { "oscclk", "fout_aud_pll", };
|
||||
PNAME(mout_isp_pll_p) = { "oscclk", "fout_isp_pll", };
|
||||
|
|
@ -792,6 +803,8 @@ static const struct samsung_cmu_info top_cmu_info __initconst = {
|
|||
.nr_clk_ids = TOP_NR_CLK,
|
||||
.clk_regs = top_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(top_clk_regs),
|
||||
.suspend_regs = top_suspend_regs,
|
||||
.nr_suspend_regs = ARRAY_SIZE(top_suspend_regs),
|
||||
};
|
||||
|
||||
static void __init exynos5433_cmu_top_init(struct device_node *np)
|
||||
|
|
@ -822,6 +835,13 @@ static const unsigned long cpif_clk_regs[] __initconst = {
|
|||
ENABLE_SCLK_CPIF,
|
||||
};
|
||||
|
||||
static const struct samsung_clk_reg_dump cpif_suspend_regs[] = {
|
||||
/* force all sclk clocks enabled */
|
||||
{ ENABLE_SCLK_CPIF, 0x3ff },
|
||||
/* MPHY PLL has to be enabled for suspend: reset value + ENABLE bit */
|
||||
{ MPHY_PLL_CON0, 0x81c70601 },
|
||||
};
|
||||
|
||||
/* list of all parent clock list */
|
||||
PNAME(mout_mphy_pll_p) = { "oscclk", "fout_mphy_pll", };
|
||||
|
||||
|
|
@ -862,6 +882,8 @@ static const struct samsung_cmu_info cpif_cmu_info __initconst = {
|
|||
.nr_clk_ids = CPIF_NR_CLK,
|
||||
.clk_regs = cpif_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(cpif_clk_regs),
|
||||
.suspend_regs = cpif_suspend_regs,
|
||||
.nr_suspend_regs = ARRAY_SIZE(cpif_suspend_regs),
|
||||
};
|
||||
|
||||
static void __init exynos5433_cmu_cpif_init(struct device_node *np)
|
||||
|
|
@ -1547,6 +1569,13 @@ static const unsigned long peric_clk_regs[] __initconst = {
|
|||
ENABLE_IP_PERIC2,
|
||||
};
|
||||
|
||||
static const struct samsung_clk_reg_dump peric_suspend_regs[] = {
|
||||
/* pclk: sci, pmu, sysreg, gpio_{finger, ese, touch, nfc}, uart2-0 */
|
||||
{ ENABLE_PCLK_PERIC0, 0xe00ff000 },
|
||||
/* sclk: uart2-0 */
|
||||
{ ENABLE_SCLK_PERIC, 0x7 },
|
||||
};
|
||||
|
||||
static const struct samsung_div_clock peric_div_clks[] __initconst = {
|
||||
/* DIV_PERIC */
|
||||
DIV(CLK_DIV_SCLK_SCI, "div_sclk_sci", "oscclk", DIV_PERIC, 4, 4),
|
||||
|
|
@ -1705,6 +1734,8 @@ static const struct samsung_cmu_info peric_cmu_info __initconst = {
|
|||
.nr_clk_ids = PERIC_NR_CLK,
|
||||
.clk_regs = peric_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(peric_clk_regs),
|
||||
.suspend_regs = peric_suspend_regs,
|
||||
.nr_suspend_regs = ARRAY_SIZE(peric_suspend_regs),
|
||||
};
|
||||
|
||||
static void __init exynos5433_cmu_peric_init(struct device_node *np)
|
||||
|
|
@ -5630,7 +5661,7 @@ static const struct of_device_id exynos5433_cmu_of_match[] = {
|
|||
static const struct dev_pm_ops exynos5433_cmu_pm_ops = {
|
||||
SET_RUNTIME_PM_OPS(exynos5433_cmu_suspend, exynos5433_cmu_resume,
|
||||
NULL)
|
||||
SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
|
||||
SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
|
||||
pm_runtime_force_resume)
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -11,7 +11,6 @@
|
|||
#include <linux/clk-provider.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/syscore_ops.h>
|
||||
|
||||
#include <dt-bindings/clock/s3c2410.h>
|
||||
|
||||
|
|
@ -40,9 +39,6 @@ enum s3c2410_plls {
|
|||
|
||||
static void __iomem *reg_base;
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static struct samsung_clk_reg_dump *s3c2410_save;
|
||||
|
||||
/*
|
||||
* list of controller registers to be saved and restored during a
|
||||
* suspend/resume cycle.
|
||||
|
|
@ -57,42 +53,6 @@ static unsigned long s3c2410_clk_regs[] __initdata = {
|
|||
CAMDIVN,
|
||||
};
|
||||
|
||||
static int s3c2410_clk_suspend(void)
|
||||
{
|
||||
samsung_clk_save(reg_base, s3c2410_save,
|
||||
ARRAY_SIZE(s3c2410_clk_regs));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void s3c2410_clk_resume(void)
|
||||
{
|
||||
samsung_clk_restore(reg_base, s3c2410_save,
|
||||
ARRAY_SIZE(s3c2410_clk_regs));
|
||||
}
|
||||
|
||||
static struct syscore_ops s3c2410_clk_syscore_ops = {
|
||||
.suspend = s3c2410_clk_suspend,
|
||||
.resume = s3c2410_clk_resume,
|
||||
};
|
||||
|
||||
static void __init s3c2410_clk_sleep_init(void)
|
||||
{
|
||||
s3c2410_save = samsung_clk_alloc_reg_dump(s3c2410_clk_regs,
|
||||
ARRAY_SIZE(s3c2410_clk_regs));
|
||||
if (!s3c2410_save) {
|
||||
pr_warn("%s: failed to allocate sleep save data, no sleep support!\n",
|
||||
__func__);
|
||||
return;
|
||||
}
|
||||
|
||||
register_syscore_ops(&s3c2410_clk_syscore_ops);
|
||||
return;
|
||||
}
|
||||
#else
|
||||
static void __init s3c2410_clk_sleep_init(void) {}
|
||||
#endif
|
||||
|
||||
PNAME(fclk_p) = { "mpll", "div_slow" };
|
||||
|
||||
static struct samsung_mux_clock s3c2410_common_muxes[] __initdata = {
|
||||
|
|
@ -461,7 +421,8 @@ void __init s3c2410_common_clk_init(struct device_node *np, unsigned long xti_f,
|
|||
ARRAY_SIZE(s3c244x_common_aliases));
|
||||
}
|
||||
|
||||
s3c2410_clk_sleep_init();
|
||||
samsung_clk_sleep_init(reg_base, s3c2410_clk_regs,
|
||||
ARRAY_SIZE(s3c2410_clk_regs));
|
||||
|
||||
samsung_clk_of_add_provider(np, ctx);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -11,7 +11,6 @@
|
|||
#include <linux/clk-provider.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/syscore_ops.h>
|
||||
#include <linux/reboot.h>
|
||||
|
||||
#include <dt-bindings/clock/s3c2412.h>
|
||||
|
|
@ -29,9 +28,6 @@
|
|||
|
||||
static void __iomem *reg_base;
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static struct samsung_clk_reg_dump *s3c2412_save;
|
||||
|
||||
/*
|
||||
* list of controller registers to be saved and restored during a
|
||||
* suspend/resume cycle.
|
||||
|
|
@ -45,42 +41,6 @@ static unsigned long s3c2412_clk_regs[] __initdata = {
|
|||
CLKSRC,
|
||||
};
|
||||
|
||||
static int s3c2412_clk_suspend(void)
|
||||
{
|
||||
samsung_clk_save(reg_base, s3c2412_save,
|
||||
ARRAY_SIZE(s3c2412_clk_regs));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void s3c2412_clk_resume(void)
|
||||
{
|
||||
samsung_clk_restore(reg_base, s3c2412_save,
|
||||
ARRAY_SIZE(s3c2412_clk_regs));
|
||||
}
|
||||
|
||||
static struct syscore_ops s3c2412_clk_syscore_ops = {
|
||||
.suspend = s3c2412_clk_suspend,
|
||||
.resume = s3c2412_clk_resume,
|
||||
};
|
||||
|
||||
static void __init s3c2412_clk_sleep_init(void)
|
||||
{
|
||||
s3c2412_save = samsung_clk_alloc_reg_dump(s3c2412_clk_regs,
|
||||
ARRAY_SIZE(s3c2412_clk_regs));
|
||||
if (!s3c2412_save) {
|
||||
pr_warn("%s: failed to allocate sleep save data, no sleep support!\n",
|
||||
__func__);
|
||||
return;
|
||||
}
|
||||
|
||||
register_syscore_ops(&s3c2412_clk_syscore_ops);
|
||||
return;
|
||||
}
|
||||
#else
|
||||
static void __init s3c2412_clk_sleep_init(void) {}
|
||||
#endif
|
||||
|
||||
static struct clk_div_table divxti_d[] = {
|
||||
{ .val = 0, .div = 1 },
|
||||
{ .val = 1, .div = 2 },
|
||||
|
|
@ -278,7 +238,8 @@ void __init s3c2412_common_clk_init(struct device_node *np, unsigned long xti_f,
|
|||
samsung_clk_register_alias(ctx, s3c2412_aliases,
|
||||
ARRAY_SIZE(s3c2412_aliases));
|
||||
|
||||
s3c2412_clk_sleep_init();
|
||||
samsung_clk_sleep_init(reg_base, s3c2412_clk_regs,
|
||||
ARRAY_SIZE(s3c2412_clk_regs));
|
||||
|
||||
samsung_clk_of_add_provider(np, ctx);
|
||||
|
||||
|
|
|
|||
|
|
@ -11,7 +11,6 @@
|
|||
#include <linux/clk-provider.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/syscore_ops.h>
|
||||
#include <linux/reboot.h>
|
||||
|
||||
#include <dt-bindings/clock/s3c2443.h>
|
||||
|
|
@ -43,9 +42,6 @@ enum supported_socs {
|
|||
|
||||
static void __iomem *reg_base;
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static struct samsung_clk_reg_dump *s3c2443_save;
|
||||
|
||||
/*
|
||||
* list of controller registers to be saved and restored during a
|
||||
* suspend/resume cycle.
|
||||
|
|
@ -65,42 +61,6 @@ static unsigned long s3c2443_clk_regs[] __initdata = {
|
|||
SCLKCON,
|
||||
};
|
||||
|
||||
static int s3c2443_clk_suspend(void)
|
||||
{
|
||||
samsung_clk_save(reg_base, s3c2443_save,
|
||||
ARRAY_SIZE(s3c2443_clk_regs));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void s3c2443_clk_resume(void)
|
||||
{
|
||||
samsung_clk_restore(reg_base, s3c2443_save,
|
||||
ARRAY_SIZE(s3c2443_clk_regs));
|
||||
}
|
||||
|
||||
static struct syscore_ops s3c2443_clk_syscore_ops = {
|
||||
.suspend = s3c2443_clk_suspend,
|
||||
.resume = s3c2443_clk_resume,
|
||||
};
|
||||
|
||||
static void __init s3c2443_clk_sleep_init(void)
|
||||
{
|
||||
s3c2443_save = samsung_clk_alloc_reg_dump(s3c2443_clk_regs,
|
||||
ARRAY_SIZE(s3c2443_clk_regs));
|
||||
if (!s3c2443_save) {
|
||||
pr_warn("%s: failed to allocate sleep save data, no sleep support!\n",
|
||||
__func__);
|
||||
return;
|
||||
}
|
||||
|
||||
register_syscore_ops(&s3c2443_clk_syscore_ops);
|
||||
return;
|
||||
}
|
||||
#else
|
||||
static void __init s3c2443_clk_sleep_init(void) {}
|
||||
#endif
|
||||
|
||||
PNAME(epllref_p) = { "mpllref", "mpllref", "xti", "ext" };
|
||||
PNAME(esysclk_p) = { "epllref", "epll" };
|
||||
PNAME(mpllref_p) = { "xti", "mdivclk" };
|
||||
|
|
@ -450,7 +410,8 @@ void __init s3c2443_common_clk_init(struct device_node *np, unsigned long xti_f,
|
|||
break;
|
||||
}
|
||||
|
||||
s3c2443_clk_sleep_init();
|
||||
samsung_clk_sleep_init(reg_base, s3c2443_clk_regs,
|
||||
ARRAY_SIZE(s3c2443_clk_regs));
|
||||
|
||||
samsung_clk_of_add_provider(np, ctx);
|
||||
|
||||
|
|
|
|||
|
|
@ -12,7 +12,6 @@
|
|||
#include <linux/clk-provider.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/syscore_ops.h>
|
||||
|
||||
#include <dt-bindings/clock/samsung,s3c64xx-clock.h>
|
||||
|
||||
|
|
@ -59,10 +58,6 @@
|
|||
static void __iomem *reg_base;
|
||||
static bool is_s3c6400;
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static struct samsung_clk_reg_dump *s3c64xx_save_common;
|
||||
static struct samsung_clk_reg_dump *s3c64xx_save_soc;
|
||||
|
||||
/*
|
||||
* List of controller registers to be saved and restored during
|
||||
* a suspend/resume cycle.
|
||||
|
|
@ -89,60 +84,6 @@ static unsigned long s3c6410_clk_regs[] __initdata = {
|
|||
MEM0_GATE,
|
||||
};
|
||||
|
||||
static int s3c64xx_clk_suspend(void)
|
||||
{
|
||||
samsung_clk_save(reg_base, s3c64xx_save_common,
|
||||
ARRAY_SIZE(s3c64xx_clk_regs));
|
||||
|
||||
if (!is_s3c6400)
|
||||
samsung_clk_save(reg_base, s3c64xx_save_soc,
|
||||
ARRAY_SIZE(s3c6410_clk_regs));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void s3c64xx_clk_resume(void)
|
||||
{
|
||||
samsung_clk_restore(reg_base, s3c64xx_save_common,
|
||||
ARRAY_SIZE(s3c64xx_clk_regs));
|
||||
|
||||
if (!is_s3c6400)
|
||||
samsung_clk_restore(reg_base, s3c64xx_save_soc,
|
||||
ARRAY_SIZE(s3c6410_clk_regs));
|
||||
}
|
||||
|
||||
static struct syscore_ops s3c64xx_clk_syscore_ops = {
|
||||
.suspend = s3c64xx_clk_suspend,
|
||||
.resume = s3c64xx_clk_resume,
|
||||
};
|
||||
|
||||
static void __init s3c64xx_clk_sleep_init(void)
|
||||
{
|
||||
s3c64xx_save_common = samsung_clk_alloc_reg_dump(s3c64xx_clk_regs,
|
||||
ARRAY_SIZE(s3c64xx_clk_regs));
|
||||
if (!s3c64xx_save_common)
|
||||
goto err_warn;
|
||||
|
||||
if (!is_s3c6400) {
|
||||
s3c64xx_save_soc = samsung_clk_alloc_reg_dump(s3c6410_clk_regs,
|
||||
ARRAY_SIZE(s3c6410_clk_regs));
|
||||
if (!s3c64xx_save_soc)
|
||||
goto err_soc;
|
||||
}
|
||||
|
||||
register_syscore_ops(&s3c64xx_clk_syscore_ops);
|
||||
return;
|
||||
|
||||
err_soc:
|
||||
kfree(s3c64xx_save_common);
|
||||
err_warn:
|
||||
pr_warn("%s: failed to allocate sleep save data, no sleep support!\n",
|
||||
__func__);
|
||||
}
|
||||
#else
|
||||
static void __init s3c64xx_clk_sleep_init(void) {}
|
||||
#endif
|
||||
|
||||
/* List of parent clocks common for all S3C64xx SoCs. */
|
||||
PNAME(spi_mmc_p) = { "mout_epll", "dout_mpll", "fin_pll", "clk27m" };
|
||||
PNAME(uart_p) = { "mout_epll", "dout_mpll" };
|
||||
|
|
@ -508,7 +449,12 @@ void __init s3c64xx_clk_init(struct device_node *np, unsigned long xtal_f,
|
|||
|
||||
samsung_clk_register_alias(ctx, s3c64xx_clock_aliases,
|
||||
ARRAY_SIZE(s3c64xx_clock_aliases));
|
||||
s3c64xx_clk_sleep_init();
|
||||
|
||||
samsung_clk_sleep_init(reg_base, s3c64xx_clk_regs,
|
||||
ARRAY_SIZE(s3c64xx_clk_regs));
|
||||
if (!is_s3c6400)
|
||||
samsung_clk_sleep_init(reg_base, s3c6410_clk_regs,
|
||||
ARRAY_SIZE(s3c6410_clk_regs));
|
||||
|
||||
samsung_clk_of_add_provider(np, ctx);
|
||||
|
||||
|
|
|
|||
|
|
@ -14,7 +14,6 @@
|
|||
#include <linux/clk-provider.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/syscore_ops.h>
|
||||
|
||||
#include "clk.h"
|
||||
#include "clk-pll.h"
|
||||
|
|
@ -83,9 +82,6 @@ enum {
|
|||
|
||||
static void __iomem *reg_base;
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static struct samsung_clk_reg_dump *s5pv210_clk_dump;
|
||||
|
||||
/* List of registers that need to be preserved across suspend/resume. */
|
||||
static unsigned long s5pv210_clk_regs[] __initdata = {
|
||||
CLK_SRC0,
|
||||
|
|
@ -132,40 +128,6 @@ static unsigned long s5pv210_clk_regs[] __initdata = {
|
|||
CLK_OUT,
|
||||
};
|
||||
|
||||
static int s5pv210_clk_suspend(void)
|
||||
{
|
||||
samsung_clk_save(reg_base, s5pv210_clk_dump,
|
||||
ARRAY_SIZE(s5pv210_clk_regs));
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void s5pv210_clk_resume(void)
|
||||
{
|
||||
samsung_clk_restore(reg_base, s5pv210_clk_dump,
|
||||
ARRAY_SIZE(s5pv210_clk_regs));
|
||||
}
|
||||
|
||||
static struct syscore_ops s5pv210_clk_syscore_ops = {
|
||||
.suspend = s5pv210_clk_suspend,
|
||||
.resume = s5pv210_clk_resume,
|
||||
};
|
||||
|
||||
static void s5pv210_clk_sleep_init(void)
|
||||
{
|
||||
s5pv210_clk_dump =
|
||||
samsung_clk_alloc_reg_dump(s5pv210_clk_regs,
|
||||
ARRAY_SIZE(s5pv210_clk_regs));
|
||||
if (!s5pv210_clk_dump) {
|
||||
pr_warn("%s: Failed to allocate sleep save data\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
register_syscore_ops(&s5pv210_clk_syscore_ops);
|
||||
}
|
||||
#else
|
||||
static inline void s5pv210_clk_sleep_init(void) { }
|
||||
#endif
|
||||
|
||||
/* Mux parent lists. */
|
||||
static const char *const fin_pll_p[] __initconst = {
|
||||
"xxti",
|
||||
|
|
@ -822,7 +784,8 @@ static void __init __s5pv210_clk_init(struct device_node *np,
|
|||
samsung_clk_register_alias(ctx, s5pv210_aliases,
|
||||
ARRAY_SIZE(s5pv210_aliases));
|
||||
|
||||
s5pv210_clk_sleep_init();
|
||||
samsung_clk_sleep_init(reg_base, s5pv210_clk_regs,
|
||||
ARRAY_SIZE(s5pv210_clk_regs));
|
||||
|
||||
samsung_clk_of_add_provider(np, ctx);
|
||||
|
||||
|
|
|
|||
|
|
@ -290,9 +290,12 @@ static int samsung_clk_suspend(void)
|
|||
{
|
||||
struct samsung_clock_reg_cache *reg_cache;
|
||||
|
||||
list_for_each_entry(reg_cache, &clock_reg_cache_list, node)
|
||||
list_for_each_entry(reg_cache, &clock_reg_cache_list, node) {
|
||||
samsung_clk_save(reg_cache->reg_base, reg_cache->rdump,
|
||||
reg_cache->rd_num);
|
||||
samsung_clk_restore(reg_cache->reg_base, reg_cache->rsuspend,
|
||||
reg_cache->rsuspend_num);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -310,9 +313,11 @@ static struct syscore_ops samsung_clk_syscore_ops = {
|
|||
.resume = samsung_clk_resume,
|
||||
};
|
||||
|
||||
void samsung_clk_sleep_init(void __iomem *reg_base,
|
||||
void samsung_clk_extended_sleep_init(void __iomem *reg_base,
|
||||
const unsigned long *rdump,
|
||||
unsigned long nr_rdump)
|
||||
unsigned long nr_rdump,
|
||||
const struct samsung_clk_reg_dump *rsuspend,
|
||||
unsigned long nr_rsuspend)
|
||||
{
|
||||
struct samsung_clock_reg_cache *reg_cache;
|
||||
|
||||
|
|
@ -330,13 +335,10 @@ void samsung_clk_sleep_init(void __iomem *reg_base,
|
|||
|
||||
reg_cache->reg_base = reg_base;
|
||||
reg_cache->rd_num = nr_rdump;
|
||||
reg_cache->rsuspend = rsuspend;
|
||||
reg_cache->rsuspend_num = nr_rsuspend;
|
||||
list_add_tail(®_cache->node, &clock_reg_cache_list);
|
||||
}
|
||||
|
||||
#else
|
||||
void samsung_clk_sleep_init(void __iomem *reg_base,
|
||||
const unsigned long *rdump,
|
||||
unsigned long nr_rdump) {}
|
||||
#endif
|
||||
|
||||
/*
|
||||
|
|
@ -380,8 +382,9 @@ struct samsung_clk_provider * __init samsung_cmu_register_one(
|
|||
samsung_clk_register_fixed_factor(ctx, cmu->fixed_factor_clks,
|
||||
cmu->nr_fixed_factor_clks);
|
||||
if (cmu->clk_regs)
|
||||
samsung_clk_sleep_init(reg_base, cmu->clk_regs,
|
||||
cmu->nr_clk_regs);
|
||||
samsung_clk_extended_sleep_init(reg_base,
|
||||
cmu->clk_regs, cmu->nr_clk_regs,
|
||||
cmu->suspend_regs, cmu->nr_suspend_regs);
|
||||
|
||||
samsung_clk_of_add_provider(np, ctx);
|
||||
|
||||
|
|
|
|||
|
|
@ -279,6 +279,8 @@ struct samsung_clock_reg_cache {
|
|||
void __iomem *reg_base;
|
||||
struct samsung_clk_reg_dump *rdump;
|
||||
unsigned int rd_num;
|
||||
const struct samsung_clk_reg_dump *rsuspend;
|
||||
unsigned int rsuspend_num;
|
||||
};
|
||||
|
||||
struct samsung_cmu_info {
|
||||
|
|
@ -358,9 +360,21 @@ extern struct samsung_clk_provider __init *samsung_cmu_register_one(
|
|||
|
||||
extern unsigned long _get_rate(const char *clk_name);
|
||||
|
||||
extern void samsung_clk_sleep_init(void __iomem *reg_base,
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
extern void samsung_clk_extended_sleep_init(void __iomem *reg_base,
|
||||
const unsigned long *rdump,
|
||||
unsigned long nr_rdump);
|
||||
unsigned long nr_rdump,
|
||||
const struct samsung_clk_reg_dump *rsuspend,
|
||||
unsigned long nr_rsuspend);
|
||||
#else
|
||||
static inline void samsung_clk_extended_sleep_init(void __iomem *reg_base,
|
||||
const unsigned long *rdump,
|
||||
unsigned long nr_rdump,
|
||||
const struct samsung_clk_reg_dump *rsuspend,
|
||||
unsigned long nr_rsuspend) {}
|
||||
#endif
|
||||
#define samsung_clk_sleep_init(reg_base, rdump, nr_rdump) \
|
||||
samsung_clk_extended_sleep_init(reg_base, rdump, nr_rdump, NULL, 0)
|
||||
|
||||
extern void samsung_clk_save(void __iomem *base,
|
||||
struct samsung_clk_reg_dump *rd,
|
||||
|
|
|
|||
|
|
@ -1,11 +1,8 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
|
||||
* Author: Tomasz Figa <t.figa@samsung.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* Device Tree binding constants for Samsung Exynos3250 clock controllers.
|
||||
*/
|
||||
|
||||
|
|
|
|||
|
|
@ -1,13 +1,10 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
|
||||
* Author: Andrzej Hajda <a.hajda@samsung.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* Device Tree binding constants for Exynos4 clock controller.
|
||||
*/
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLOCK_EXYNOS_4_H
|
||||
#define _DT_BINDINGS_CLOCK_EXYNOS_4_H
|
||||
|
|
@ -190,32 +187,6 @@
|
|||
#define CLK_MIPI_HSI 349 /* Exynos4210 only */
|
||||
#define CLK_PIXELASYNCM0 351
|
||||
#define CLK_PIXELASYNCM1 352
|
||||
#define CLK_FIMC_LITE0 353 /* Exynos4x12 only */
|
||||
#define CLK_FIMC_LITE1 354 /* Exynos4x12 only */
|
||||
#define CLK_PPMUISPX 355 /* Exynos4x12 only */
|
||||
#define CLK_PPMUISPMX 356 /* Exynos4x12 only */
|
||||
#define CLK_FIMC_ISP 357 /* Exynos4x12 only */
|
||||
#define CLK_FIMC_DRC 358 /* Exynos4x12 only */
|
||||
#define CLK_FIMC_FD 359 /* Exynos4x12 only */
|
||||
#define CLK_MCUISP 360 /* Exynos4x12 only */
|
||||
#define CLK_GICISP 361 /* Exynos4x12 only */
|
||||
#define CLK_SMMU_ISP 362 /* Exynos4x12 only */
|
||||
#define CLK_SMMU_DRC 363 /* Exynos4x12 only */
|
||||
#define CLK_SMMU_FD 364 /* Exynos4x12 only */
|
||||
#define CLK_SMMU_LITE0 365 /* Exynos4x12 only */
|
||||
#define CLK_SMMU_LITE1 366 /* Exynos4x12 only */
|
||||
#define CLK_MCUCTL_ISP 367 /* Exynos4x12 only */
|
||||
#define CLK_MPWM_ISP 368 /* Exynos4x12 only */
|
||||
#define CLK_I2C0_ISP 369 /* Exynos4x12 only */
|
||||
#define CLK_I2C1_ISP 370 /* Exynos4x12 only */
|
||||
#define CLK_MTCADC_ISP 371 /* Exynos4x12 only */
|
||||
#define CLK_PWM_ISP 372 /* Exynos4x12 only */
|
||||
#define CLK_WDT_ISP 373 /* Exynos4x12 only */
|
||||
#define CLK_UART_ISP 374 /* Exynos4x12 only */
|
||||
#define CLK_ASYNCAXIM 375 /* Exynos4x12 only */
|
||||
#define CLK_SMMU_ISPCX 376 /* Exynos4x12 only */
|
||||
#define CLK_SPI0_ISP 377 /* Exynos4x12 only */
|
||||
#define CLK_SPI1_ISP 378 /* Exynos4x12 only */
|
||||
#define CLK_PWM_ISP_SCLK 379 /* Exynos4x12 only */
|
||||
#define CLK_SPI0_ISP_SCLK 380 /* Exynos4x12 only */
|
||||
#define CLK_SPI1_ISP_SCLK 381 /* Exynos4x12 only */
|
||||
|
|
@ -257,10 +228,6 @@
|
|||
#define CLK_PPMUACP 415
|
||||
|
||||
/* div clocks */
|
||||
#define CLK_DIV_ISP0 450 /* Exynos4x12 only */
|
||||
#define CLK_DIV_ISP1 451 /* Exynos4x12 only */
|
||||
#define CLK_DIV_MCUISP0 452 /* Exynos4x12 only */
|
||||
#define CLK_DIV_MCUISP1 453 /* Exynos4x12 only */
|
||||
#define CLK_DIV_ACLK200 454 /* Exynos4x12 only */
|
||||
#define CLK_DIV_ACLK400_MCUISP 455 /* Exynos4x12 only */
|
||||
#define CLK_DIV_ACP 456
|
||||
|
|
|
|||
|
|
@ -1,13 +1,10 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
|
||||
* Author: Andrzej Hajda <a.hajda@samsung.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* Device Tree binding constants for Exynos5250 clock controller.
|
||||
*/
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5250_H
|
||||
#define _DT_BINDINGS_CLOCK_EXYNOS_5250_H
|
||||
|
|
|
|||
|
|
@ -1,13 +1,10 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
|
||||
* Author: Rahul Sharma <rahul.sharma@samsung.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* Provides Constants for Exynos5260 clocks.
|
||||
*/
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_EXYNOS5260_H
|
||||
#define _DT_BINDINGS_CLK_EXYNOS5260_H
|
||||
|
|
|
|||
|
|
@ -1,13 +1,10 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
|
||||
* Copyright (c) 2016 Krzysztof Kozlowski
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* Device Tree binding constants for Exynos5421 clock controller.
|
||||
*/
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5410_H
|
||||
#define _DT_BINDINGS_CLOCK_EXYNOS_5410_H
|
||||
|
|
|
|||
|
|
@ -1,13 +1,10 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
|
||||
* Author: Andrzej Hajda <a.hajda@samsung.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* Device Tree binding constants for Exynos5420 clock controller.
|
||||
*/
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5420_H
|
||||
#define _DT_BINDINGS_CLOCK_EXYNOS_5420_H
|
||||
|
|
|
|||
|
|
@ -1,10 +1,7 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
|
||||
* Author: Chanwoo Choi <cw00.choi@samsung.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLOCK_EXYNOS5433_H
|
||||
|
|
|
|||
|
|
@ -1,11 +1,8 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
|
||||
* Author: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLOCK_EXYNOS7_H
|
||||
#define _DT_BINDINGS_CLOCK_EXYNOS7_H
|
||||
|
|
|
|||
|
|
@ -0,0 +1,348 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Device Tree binding constants for HiSilicon Hi3670 SoC
|
||||
*
|
||||
* Copyright (c) 2001-2021, Huawei Tech. Co., Ltd.
|
||||
* Copyright (c) 2018 Linaro Ltd.
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_HI3670_H
|
||||
#define __DT_BINDINGS_CLOCK_HI3670_H
|
||||
|
||||
/* clk in stub clock */
|
||||
#define HI3670_CLK_STUB_CLUSTER0 0
|
||||
#define HI3670_CLK_STUB_CLUSTER1 1
|
||||
#define HI3670_CLK_STUB_GPU 2
|
||||
#define HI3670_CLK_STUB_DDR 3
|
||||
#define HI3670_CLK_STUB_DDR_VOTE 4
|
||||
#define HI3670_CLK_STUB_DDR_LIMIT 5
|
||||
#define HI3670_CLK_STUB_NUM 6
|
||||
|
||||
/* clk in crg clock */
|
||||
#define HI3670_CLKIN_SYS 0
|
||||
#define HI3670_CLKIN_REF 1
|
||||
#define HI3670_CLK_FLL_SRC 2
|
||||
#define HI3670_CLK_PPLL0 3
|
||||
#define HI3670_CLK_PPLL1 4
|
||||
#define HI3670_CLK_PPLL2 5
|
||||
#define HI3670_CLK_PPLL3 6
|
||||
#define HI3670_CLK_PPLL4 7
|
||||
#define HI3670_CLK_PPLL6 8
|
||||
#define HI3670_CLK_PPLL7 9
|
||||
#define HI3670_CLK_PPLL_PCIE 10
|
||||
#define HI3670_CLK_PCIEPLL_REV 11
|
||||
#define HI3670_CLK_SCPLL 12
|
||||
#define HI3670_PCLK 13
|
||||
#define HI3670_CLK_UART0_DBG 14
|
||||
#define HI3670_CLK_UART6 15
|
||||
#define HI3670_OSC32K 16
|
||||
#define HI3670_OSC19M 17
|
||||
#define HI3670_CLK_480M 18
|
||||
#define HI3670_CLK_INVALID 19
|
||||
#define HI3670_CLK_DIV_SYSBUS 20
|
||||
#define HI3670_CLK_FACTOR_MMC 21
|
||||
#define HI3670_CLK_SD_SYS 22
|
||||
#define HI3670_CLK_SDIO_SYS 23
|
||||
#define HI3670_CLK_DIV_A53HPM 24
|
||||
#define HI3670_CLK_DIV_320M 25
|
||||
#define HI3670_PCLK_GATE_UART0 26
|
||||
#define HI3670_CLK_FACTOR_UART0 27
|
||||
#define HI3670_CLK_FACTOR_USB3PHY_PLL 28
|
||||
#define HI3670_CLK_GATE_ABB_USB 29
|
||||
#define HI3670_CLK_GATE_UFSPHY_REF 30
|
||||
#define HI3670_ICS_VOLT_HIGH 31
|
||||
#define HI3670_ICS_VOLT_MIDDLE 32
|
||||
#define HI3670_VENC_VOLT_HOLD 33
|
||||
#define HI3670_VDEC_VOLT_HOLD 34
|
||||
#define HI3670_EDC_VOLT_HOLD 35
|
||||
#define HI3670_CLK_ISP_SNCLK_FAC 36
|
||||
#define HI3670_CLK_FACTOR_RXDPHY 37
|
||||
#define HI3670_AUTODIV_SYSBUS 38
|
||||
#define HI3670_AUTODIV_EMMC0BUS 39
|
||||
#define HI3670_PCLK_ANDGT_MMC1_PCIE 40
|
||||
#define HI3670_CLK_GATE_VCODECBUS_GT 41
|
||||
#define HI3670_CLK_ANDGT_SD 42
|
||||
#define HI3670_CLK_SD_SYS_GT 43
|
||||
#define HI3670_CLK_ANDGT_SDIO 44
|
||||
#define HI3670_CLK_SDIO_SYS_GT 45
|
||||
#define HI3670_CLK_A53HPM_ANDGT 46
|
||||
#define HI3670_CLK_320M_PLL_GT 47
|
||||
#define HI3670_CLK_ANDGT_UARTH 48
|
||||
#define HI3670_CLK_ANDGT_UARTL 49
|
||||
#define HI3670_CLK_ANDGT_UART0 50
|
||||
#define HI3670_CLK_ANDGT_SPI 51
|
||||
#define HI3670_CLK_ANDGT_PCIEAXI 52
|
||||
#define HI3670_CLK_DIV_AO_ASP_GT 53
|
||||
#define HI3670_CLK_GATE_CSI_TRANS 54
|
||||
#define HI3670_CLK_GATE_DSI_TRANS 55
|
||||
#define HI3670_CLK_ANDGT_PTP 56
|
||||
#define HI3670_CLK_ANDGT_OUT0 57
|
||||
#define HI3670_CLK_ANDGT_OUT1 58
|
||||
#define HI3670_CLKGT_DP_AUDIO_PLL_AO 59
|
||||
#define HI3670_CLK_ANDGT_VDEC 60
|
||||
#define HI3670_CLK_ANDGT_VENC 61
|
||||
#define HI3670_CLK_ISP_SNCLK_ANGT 62
|
||||
#define HI3670_CLK_ANDGT_RXDPHY 63
|
||||
#define HI3670_CLK_ANDGT_ICS 64
|
||||
#define HI3670_AUTODIV_DMABUS 65
|
||||
#define HI3670_CLK_MUX_SYSBUS 66
|
||||
#define HI3670_CLK_MUX_VCODECBUS 67
|
||||
#define HI3670_CLK_MUX_SD_SYS 68
|
||||
#define HI3670_CLK_MUX_SD_PLL 69
|
||||
#define HI3670_CLK_MUX_SDIO_SYS 70
|
||||
#define HI3670_CLK_MUX_SDIO_PLL 71
|
||||
#define HI3670_CLK_MUX_A53HPM 72
|
||||
#define HI3670_CLK_MUX_320M 73
|
||||
#define HI3670_CLK_MUX_UARTH 74
|
||||
#define HI3670_CLK_MUX_UARTL 75
|
||||
#define HI3670_CLK_MUX_UART0 76
|
||||
#define HI3670_CLK_MUX_I2C 77
|
||||
#define HI3670_CLK_MUX_SPI 78
|
||||
#define HI3670_CLK_MUX_PCIEAXI 79
|
||||
#define HI3670_CLK_MUX_AO_ASP 80
|
||||
#define HI3670_CLK_MUX_VDEC 81
|
||||
#define HI3670_CLK_MUX_VENC 82
|
||||
#define HI3670_CLK_ISP_SNCLK_MUX0 83
|
||||
#define HI3670_CLK_ISP_SNCLK_MUX1 84
|
||||
#define HI3670_CLK_ISP_SNCLK_MUX2 85
|
||||
#define HI3670_CLK_MUX_RXDPHY_CFG 86
|
||||
#define HI3670_CLK_MUX_ICS 87
|
||||
#define HI3670_CLK_DIV_CFGBUS 88
|
||||
#define HI3670_CLK_DIV_MMC0BUS 89
|
||||
#define HI3670_CLK_DIV_MMC1BUS 90
|
||||
#define HI3670_PCLK_DIV_MMC1_PCIE 91
|
||||
#define HI3670_CLK_DIV_VCODECBUS 92
|
||||
#define HI3670_CLK_DIV_SD 93
|
||||
#define HI3670_CLK_DIV_SDIO 94
|
||||
#define HI3670_CLK_DIV_UARTH 95
|
||||
#define HI3670_CLK_DIV_UARTL 96
|
||||
#define HI3670_CLK_DIV_UART0 97
|
||||
#define HI3670_CLK_DIV_I2C 98
|
||||
#define HI3670_CLK_DIV_SPI 99
|
||||
#define HI3670_CLK_DIV_PCIEAXI 100
|
||||
#define HI3670_CLK_DIV_AO_ASP 101
|
||||
#define HI3670_CLK_DIV_CSI_TRANS 102
|
||||
#define HI3670_CLK_DIV_DSI_TRANS 103
|
||||
#define HI3670_CLK_DIV_PTP 104
|
||||
#define HI3670_CLK_DIV_CLKOUT0_PLL 105
|
||||
#define HI3670_CLK_DIV_CLKOUT1_PLL 106
|
||||
#define HI3670_CLKDIV_DP_AUDIO_PLL_AO 107
|
||||
#define HI3670_CLK_DIV_VDEC 108
|
||||
#define HI3670_CLK_DIV_VENC 109
|
||||
#define HI3670_CLK_ISP_SNCLK_DIV0 110
|
||||
#define HI3670_CLK_ISP_SNCLK_DIV1 111
|
||||
#define HI3670_CLK_ISP_SNCLK_DIV2 112
|
||||
#define HI3670_CLK_DIV_ICS 113
|
||||
#define HI3670_PPLL1_EN_ACPU 114
|
||||
#define HI3670_PPLL2_EN_ACPU 115
|
||||
#define HI3670_PPLL3_EN_ACPU 116
|
||||
#define HI3670_PPLL1_GT_CPU 117
|
||||
#define HI3670_PPLL2_GT_CPU 118
|
||||
#define HI3670_PPLL3_GT_CPU 119
|
||||
#define HI3670_CLK_GATE_PPLL2_MEDIA 120
|
||||
#define HI3670_CLK_GATE_PPLL3_MEDIA 121
|
||||
#define HI3670_CLK_GATE_PPLL4_MEDIA 122
|
||||
#define HI3670_CLK_GATE_PPLL6_MEDIA 123
|
||||
#define HI3670_CLK_GATE_PPLL7_MEDIA 124
|
||||
#define HI3670_PCLK_GPIO0 125
|
||||
#define HI3670_PCLK_GPIO1 126
|
||||
#define HI3670_PCLK_GPIO2 127
|
||||
#define HI3670_PCLK_GPIO3 128
|
||||
#define HI3670_PCLK_GPIO4 129
|
||||
#define HI3670_PCLK_GPIO5 130
|
||||
#define HI3670_PCLK_GPIO6 131
|
||||
#define HI3670_PCLK_GPIO7 132
|
||||
#define HI3670_PCLK_GPIO8 133
|
||||
#define HI3670_PCLK_GPIO9 134
|
||||
#define HI3670_PCLK_GPIO10 135
|
||||
#define HI3670_PCLK_GPIO11 136
|
||||
#define HI3670_PCLK_GPIO12 137
|
||||
#define HI3670_PCLK_GPIO13 138
|
||||
#define HI3670_PCLK_GPIO14 139
|
||||
#define HI3670_PCLK_GPIO15 140
|
||||
#define HI3670_PCLK_GPIO16 141
|
||||
#define HI3670_PCLK_GPIO17 142
|
||||
#define HI3670_PCLK_GPIO20 143
|
||||
#define HI3670_PCLK_GPIO21 144
|
||||
#define HI3670_PCLK_GATE_DSI0 145
|
||||
#define HI3670_PCLK_GATE_DSI1 146
|
||||
#define HI3670_HCLK_GATE_USB3OTG 147
|
||||
#define HI3670_ACLK_GATE_USB3DVFS 148
|
||||
#define HI3670_HCLK_GATE_SDIO 149
|
||||
#define HI3670_PCLK_GATE_PCIE_SYS 150
|
||||
#define HI3670_PCLK_GATE_PCIE_PHY 151
|
||||
#define HI3670_PCLK_GATE_MMC1_PCIE 152
|
||||
#define HI3670_PCLK_GATE_MMC0_IOC 153
|
||||
#define HI3670_PCLK_GATE_MMC1_IOC 154
|
||||
#define HI3670_CLK_GATE_DMAC 155
|
||||
#define HI3670_CLK_GATE_VCODECBUS2DDR 156
|
||||
#define HI3670_CLK_CCI400_BYPASS 157
|
||||
#define HI3670_CLK_GATE_CCI400 158
|
||||
#define HI3670_CLK_GATE_SD 159
|
||||
#define HI3670_HCLK_GATE_SD 160
|
||||
#define HI3670_CLK_GATE_SDIO 161
|
||||
#define HI3670_CLK_GATE_A57HPM 162
|
||||
#define HI3670_CLK_GATE_A53HPM 163
|
||||
#define HI3670_CLK_GATE_PA_A53 164
|
||||
#define HI3670_CLK_GATE_PA_A57 165
|
||||
#define HI3670_CLK_GATE_PA_G3D 166
|
||||
#define HI3670_CLK_GATE_GPUHPM 167
|
||||
#define HI3670_CLK_GATE_PERIHPM 168
|
||||
#define HI3670_CLK_GATE_AOHPM 169
|
||||
#define HI3670_CLK_GATE_UART1 170
|
||||
#define HI3670_CLK_GATE_UART4 171
|
||||
#define HI3670_PCLK_GATE_UART1 172
|
||||
#define HI3670_PCLK_GATE_UART4 173
|
||||
#define HI3670_CLK_GATE_UART2 174
|
||||
#define HI3670_CLK_GATE_UART5 175
|
||||
#define HI3670_PCLK_GATE_UART2 176
|
||||
#define HI3670_PCLK_GATE_UART5 177
|
||||
#define HI3670_CLK_GATE_UART0 178
|
||||
#define HI3670_CLK_GATE_I2C3 179
|
||||
#define HI3670_CLK_GATE_I2C4 180
|
||||
#define HI3670_CLK_GATE_I2C7 181
|
||||
#define HI3670_PCLK_GATE_I2C3 182
|
||||
#define HI3670_PCLK_GATE_I2C4 183
|
||||
#define HI3670_PCLK_GATE_I2C7 184
|
||||
#define HI3670_CLK_GATE_SPI1 185
|
||||
#define HI3670_CLK_GATE_SPI4 186
|
||||
#define HI3670_PCLK_GATE_SPI1 187
|
||||
#define HI3670_PCLK_GATE_SPI4 188
|
||||
#define HI3670_CLK_GATE_USB3OTG_REF 189
|
||||
#define HI3670_CLK_GATE_USB2PHY_REF 190
|
||||
#define HI3670_CLK_GATE_PCIEAUX 191
|
||||
#define HI3670_ACLK_GATE_PCIE 192
|
||||
#define HI3670_CLK_GATE_MMC1_PCIEAXI 193
|
||||
#define HI3670_CLK_GATE_PCIEPHY_REF 194
|
||||
#define HI3670_CLK_GATE_PCIE_DEBOUNCE 195
|
||||
#define HI3670_CLK_GATE_PCIEIO 196
|
||||
#define HI3670_CLK_GATE_PCIE_HP 197
|
||||
#define HI3670_CLK_GATE_AO_ASP 198
|
||||
#define HI3670_PCLK_GATE_PCTRL 199
|
||||
#define HI3670_CLK_CSI_TRANS_GT 200
|
||||
#define HI3670_CLK_DSI_TRANS_GT 201
|
||||
#define HI3670_CLK_GATE_PWM 202
|
||||
#define HI3670_ABB_AUDIO_EN0 203
|
||||
#define HI3670_ABB_AUDIO_EN1 204
|
||||
#define HI3670_ABB_AUDIO_GT_EN0 205
|
||||
#define HI3670_ABB_AUDIO_GT_EN1 206
|
||||
#define HI3670_CLK_GATE_DP_AUDIO_PLL_AO 207
|
||||
#define HI3670_PERI_VOLT_HOLD 208
|
||||
#define HI3670_PERI_VOLT_MIDDLE 209
|
||||
#define HI3670_CLK_GATE_ISP_SNCLK0 210
|
||||
#define HI3670_CLK_GATE_ISP_SNCLK1 211
|
||||
#define HI3670_CLK_GATE_ISP_SNCLK2 212
|
||||
#define HI3670_CLK_GATE_RXDPHY0_CFG 213
|
||||
#define HI3670_CLK_GATE_RXDPHY1_CFG 214
|
||||
#define HI3670_CLK_GATE_RXDPHY2_CFG 215
|
||||
#define HI3670_CLK_GATE_TXDPHY0_CFG 216
|
||||
#define HI3670_CLK_GATE_TXDPHY0_REF 217
|
||||
#define HI3670_CLK_GATE_TXDPHY1_CFG 218
|
||||
#define HI3670_CLK_GATE_TXDPHY1_REF 219
|
||||
#define HI3670_CLK_GATE_MEDIA_TCXO 220
|
||||
|
||||
/* clk in sctrl */
|
||||
#define HI3670_CLK_ANDGT_IOPERI 0
|
||||
#define HI3670_CLKANDGT_ASP_SUBSYS_PERI 1
|
||||
#define HI3670_CLK_ANGT_ASP_SUBSYS 2
|
||||
#define HI3670_CLK_MUX_UFS_SUBSYS 3
|
||||
#define HI3670_CLK_MUX_CLKOUT0 4
|
||||
#define HI3670_CLK_MUX_CLKOUT1 5
|
||||
#define HI3670_CLK_MUX_ASP_SUBSYS_PERI 6
|
||||
#define HI3670_CLK_MUX_ASP_PLL 7
|
||||
#define HI3670_CLK_DIV_AOBUS 8
|
||||
#define HI3670_CLK_DIV_UFS_SUBSYS 9
|
||||
#define HI3670_CLK_DIV_IOPERI 10
|
||||
#define HI3670_CLK_DIV_CLKOUT0_TCXO 11
|
||||
#define HI3670_CLK_DIV_CLKOUT1_TCXO 12
|
||||
#define HI3670_CLK_ASP_SUBSYS_PERI_DIV 13
|
||||
#define HI3670_CLK_DIV_ASP_SUBSYS 14
|
||||
#define HI3670_PPLL0_EN_ACPU 15
|
||||
#define HI3670_PPLL0_GT_CPU 16
|
||||
#define HI3670_CLK_GATE_PPLL0_MEDIA 17
|
||||
#define HI3670_PCLK_GPIO18 18
|
||||
#define HI3670_PCLK_GPIO19 19
|
||||
#define HI3670_CLK_GATE_SPI 20
|
||||
#define HI3670_PCLK_GATE_SPI 21
|
||||
#define HI3670_CLK_GATE_UFS_SUBSYS 22
|
||||
#define HI3670_CLK_GATE_UFSIO_REF 23
|
||||
#define HI3670_PCLK_AO_GPIO0 24
|
||||
#define HI3670_PCLK_AO_GPIO1 25
|
||||
#define HI3670_PCLK_AO_GPIO2 26
|
||||
#define HI3670_PCLK_AO_GPIO3 27
|
||||
#define HI3670_PCLK_AO_GPIO4 28
|
||||
#define HI3670_PCLK_AO_GPIO5 29
|
||||
#define HI3670_PCLK_AO_GPIO6 30
|
||||
#define HI3670_CLK_GATE_OUT0 31
|
||||
#define HI3670_CLK_GATE_OUT1 32
|
||||
#define HI3670_PCLK_GATE_SYSCNT 33
|
||||
#define HI3670_CLK_GATE_SYSCNT 34
|
||||
#define HI3670_CLK_GATE_ASP_SUBSYS_PERI 35
|
||||
#define HI3670_CLK_GATE_ASP_SUBSYS 36
|
||||
#define HI3670_CLK_GATE_ASP_TCXO 37
|
||||
#define HI3670_CLK_GATE_DP_AUDIO_PLL 38
|
||||
|
||||
/* clk in pmuctrl */
|
||||
#define HI3670_GATE_ABB_192 0
|
||||
|
||||
/* clk in pctrl */
|
||||
#define HI3670_GATE_UFS_TCXO_EN 0
|
||||
#define HI3670_GATE_USB_TCXO_EN 1
|
||||
|
||||
/* clk in iomcu */
|
||||
#define HI3670_CLK_GATE_I2C0 0
|
||||
#define HI3670_CLK_GATE_I2C1 1
|
||||
#define HI3670_CLK_GATE_I2C2 2
|
||||
#define HI3670_CLK_GATE_SPI0 3
|
||||
#define HI3670_CLK_GATE_SPI2 4
|
||||
#define HI3670_CLK_GATE_UART3 5
|
||||
#define HI3670_CLK_I2C0_GATE_IOMCU 6
|
||||
#define HI3670_CLK_I2C1_GATE_IOMCU 7
|
||||
#define HI3670_CLK_I2C2_GATE_IOMCU 8
|
||||
#define HI3670_CLK_SPI0_GATE_IOMCU 9
|
||||
#define HI3670_CLK_SPI2_GATE_IOMCU 10
|
||||
#define HI3670_CLK_UART3_GATE_IOMCU 11
|
||||
#define HI3670_CLK_GATE_PERI0_IOMCU 12
|
||||
|
||||
/* clk in media1 */
|
||||
#define HI3670_CLK_GATE_VIVOBUS_ANDGT 0
|
||||
#define HI3670_CLK_ANDGT_EDC0 1
|
||||
#define HI3670_CLK_ANDGT_LDI0 2
|
||||
#define HI3670_CLK_ANDGT_LDI1 3
|
||||
#define HI3670_CLK_MMBUF_PLL_ANDGT 4
|
||||
#define HI3670_PCLK_MMBUF_ANDGT 5
|
||||
#define HI3670_CLK_MUX_VIVOBUS 6
|
||||
#define HI3670_CLK_MUX_EDC0 7
|
||||
#define HI3670_CLK_MUX_LDI0 8
|
||||
#define HI3670_CLK_MUX_LDI1 9
|
||||
#define HI3670_CLK_SW_MMBUF 10
|
||||
#define HI3670_CLK_DIV_VIVOBUS 11
|
||||
#define HI3670_CLK_DIV_EDC0 12
|
||||
#define HI3670_CLK_DIV_LDI0 13
|
||||
#define HI3670_CLK_DIV_LDI1 14
|
||||
#define HI3670_ACLK_DIV_MMBUF 15
|
||||
#define HI3670_PCLK_DIV_MMBUF 16
|
||||
#define HI3670_ACLK_GATE_NOC_DSS 17
|
||||
#define HI3670_PCLK_GATE_NOC_DSS_CFG 18
|
||||
#define HI3670_PCLK_GATE_MMBUF_CFG 19
|
||||
#define HI3670_PCLK_GATE_DISP_NOC_SUBSYS 20
|
||||
#define HI3670_ACLK_GATE_DISP_NOC_SUBSYS 21
|
||||
#define HI3670_PCLK_GATE_DSS 22
|
||||
#define HI3670_ACLK_GATE_DSS 23
|
||||
#define HI3670_CLK_GATE_VIVOBUSFREQ 24
|
||||
#define HI3670_CLK_GATE_EDC0 25
|
||||
#define HI3670_CLK_GATE_LDI0 26
|
||||
#define HI3670_CLK_GATE_LDI1FREQ 27
|
||||
#define HI3670_CLK_GATE_BRG 28
|
||||
#define HI3670_ACLK_GATE_ASC 29
|
||||
#define HI3670_CLK_GATE_DSS_AXI_MM 30
|
||||
#define HI3670_CLK_GATE_MMBUF 31
|
||||
#define HI3670_PCLK_GATE_MMBUF 32
|
||||
#define HI3670_CLK_GATE_ATDIV_VIVO 33
|
||||
|
||||
/* clk in media2 */
|
||||
#define HI3670_CLK_GATE_VDECFREQ 0
|
||||
#define HI3670_CLK_GATE_VENCFREQ 1
|
||||
#define HI3670_CLK_GATE_ICSFREQ 2
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_HI3670_H */
|
||||
|
|
@ -1,10 +1,7 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* Device Tree binding constants clock controllers of Samsung S3C2410 and later.
|
||||
*/
|
||||
|
||||
|
|
|
|||
|
|
@ -1,10 +1,7 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* Device Tree binding constants clock controllers of Samsung S3C2412.
|
||||
*/
|
||||
|
||||
|
|
|
|||
|
|
@ -1,10 +1,7 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* Device Tree binding constants clock controllers of Samsung S3C2443 and later.
|
||||
*/
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue