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drivers/soc/litex: s/LITEX_REG_SIZE/LITEX_SUBREG_ALIGN/g 

The constant LITEX_REG_SIZE is renamed to the more descriptive
LITEX_SUBREG_ALIGN (LiteX CSR subregisters are located at 32-bit
aligned MMIO addresses).

NOTE: this is a non-functional change.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
Signed-off-by: Stafford Horne <shorne@gmail.com>
This commit is contained in:
Gabriel Somlo 2021-01-12 12:31:42 -05:00 committed by Stafford Horne
parent b5d3061ea2
commit ffa4ebc489
1 changed files with 5 additions and 3 deletions
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8
include/linux/litex.h
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@ -20,10 +20,12 @@
* Supporting other configurations will require extending the logic in this
* header and in the LiteX SoC controller driver.
*/
#define LITEX_REG_SIZE 0x4
#define LITEX_SUBREG_SIZE 0x1
#define LITEX_SUBREG_SIZE_BIT (LITEX_SUBREG_SIZE * 8)
/* LiteX subregisters of any width are always aligned on a 4-byte boundary */
#define LITEX_SUBREG_ALIGN 0x4
static inline void _write_litex_subregister(u32 val, void __iomem *addr)
{
writel((u32 __force)cpu_to_le32(val), addr);
@ -36,11 +38,11 @@ static inline u32 _read_litex_subregister(void __iomem *addr)
#define WRITE_LITEX_SUBREGISTER(val, base_offset, subreg_id) \
_write_litex_subregister(val, (base_offset) + \
LITEX_REG_SIZE * (subreg_id))
LITEX_SUBREG_ALIGN * (subreg_id))
#define READ_LITEX_SUBREGISTER(base_offset, subreg_id) \
_read_litex_subregister((base_offset) + \
LITEX_REG_SIZE * (subreg_id))
LITEX_SUBREG_ALIGN * (subreg_id))
/*
* LiteX SoC Generator, depending on the configuration, can split a single