media: amphion: decoder implement display delay enable

amphion vpu support a low latency mode,
when V4L2_CID_MPEG_VIDEO_DEC_DISPLAY_DELAY_ENABLE is enabled,
decoder can display frame immediately after it's decoded.
Only h264 is support yet.

Fixes: 6de8d628df ("media: amphion: add v4l2 m2m vpu decoder stateful driver")
Signed-off-by: Ming Qian <ming.qian@nxp.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
This commit is contained in:
Ming Qian 2023-03-02 06:34:10 +01:00 committed by Mauro Carvalho Chehab
parent 46ff24efe0
commit ffa331d9bf
3 changed files with 37 additions and 2 deletions

View File

@ -168,7 +168,31 @@ static const struct vpu_format vdec_formats[] = {
{0, 0, 0, 0},
};
static int vdec_op_s_ctrl(struct v4l2_ctrl *ctrl)
{
struct vpu_inst *inst = ctrl_to_inst(ctrl);
struct vdec_t *vdec = inst->priv;
int ret = 0;
vpu_inst_lock(inst);
switch (ctrl->id) {
case V4L2_CID_MPEG_VIDEO_DEC_DISPLAY_DELAY_ENABLE:
vdec->params.display_delay_enable = ctrl->val;
break;
case V4L2_CID_MPEG_VIDEO_DEC_DISPLAY_DELAY:
vdec->params.display_delay = ctrl->val;
break;
default:
ret = -EINVAL;
break;
}
vpu_inst_unlock(inst);
return ret;
}
static const struct v4l2_ctrl_ops vdec_ctrl_ops = {
.s_ctrl = vdec_op_s_ctrl,
.g_volatile_ctrl = vpu_helper_g_volatile_ctrl,
};
@ -181,6 +205,14 @@ static int vdec_ctrl_init(struct vpu_inst *inst)
if (ret)
return ret;
v4l2_ctrl_new_std(&inst->ctrl_handler, &vdec_ctrl_ops,
V4L2_CID_MPEG_VIDEO_DEC_DISPLAY_DELAY,
0, 0, 1, 0);
v4l2_ctrl_new_std(&inst->ctrl_handler, &vdec_ctrl_ops,
V4L2_CID_MPEG_VIDEO_DEC_DISPLAY_DELAY_ENABLE,
0, 1, 1, 0);
ctrl = v4l2_ctrl_new_std(&inst->ctrl_handler, &vdec_ctrl_ops,
V4L2_CID_MIN_BUFFERS_FOR_CAPTURE, 1, 32, 1, 2);
if (ctrl)

View File

@ -55,7 +55,8 @@ struct vpu_encode_params {
struct vpu_decode_params {
u32 codec_format;
u32 output_format;
u32 b_dis_reorder;
u32 display_delay_enable;
u32 display_delay;
u32 b_non_frame;
u32 frame_count;
u32 end_flag;

View File

@ -641,7 +641,9 @@ static int vpu_malone_set_params(struct vpu_shared_addr *shared,
hc->jpg[instance].jpg_mjpeg_interlaced = 0;
}
hc->codec_param[instance].disp_imm = params->b_dis_reorder ? 1 : 0;
hc->codec_param[instance].disp_imm = params->display_delay_enable ? 1 : 0;
if (malone_format != MALONE_FMT_AVC)
hc->codec_param[instance].disp_imm = 0;
hc->codec_param[instance].dbglog_enable = 0;
iface->dbglog_desc.level = 0;