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clk: mediatek: mt8365: Join top_misc_mux_gates and top_misc_muxes arrays 

In preparation for migrating this driver to the simple probe mechanism,
join the audio gates to the top_misc_mux_gates array of mtk_composite
clocks in one top_misc_muxes array.

While at it, since the `apll_i2s0_parents` array is for all i2s clocks,
rename that to `apll_i2s_parents`.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20230306140543.1813621-14-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
AngeloGioacchino Del Regno 2023-03-06 15:05:02 +01:00 committed by Stephen Boyd
parent 905b7430d3
commit ff96210073
1 changed files with 14 additions and 32 deletions
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46
drivers/clk/mediatek/clk-mt8365.c
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@ -384,25 +384,23 @@ static const char * const mbist_diag_parents[] = {
"univpll2_d8"
};
static const char * const apll_i2s0_parents[] = {
static const char * const apll_i2s_parents[] = {
"aud_1_sel",
"aud_2_sel"
};
static struct mtk_composite top_misc_mux_gates[] = {
static struct mtk_composite top_misc_muxes[] = {
/* CLK_CFG_11 */
MUX_GATE(CLK_TOP_MBIST_DIAG_SEL, "mbist_diag_sel", mbist_diag_parents,
0x0ec, 0, 2, 7),
};
static struct mt8365_clk_audio_mux top_misc_muxes[] = {
{ CLK_TOP_APLL_I2S0_SEL, "apll_i2s0_sel", 11},
{ CLK_TOP_APLL_I2S1_SEL, "apll_i2s1_sel", 12},
{ CLK_TOP_APLL_I2S2_SEL, "apll_i2s2_sel", 13},
{ CLK_TOP_APLL_I2S3_SEL, "apll_i2s3_sel", 14},
{ CLK_TOP_APLL_TDMOUT_SEL, "apll_tdmout_sel", 15},
{ CLK_TOP_APLL_TDMIN_SEL, "apll_tdmin_sel", 16},
{ CLK_TOP_APLL_SPDIF_SEL, "apll_spdif_sel", 17},
/* Audio MUX */
MUX(CLK_TOP_APLL_I2S0_SEL, "apll_i2s0_sel", apll_i2s_parents, 0x0320, 11, 1),
MUX(CLK_TOP_APLL_I2S1_SEL, "apll_i2s1_sel", apll_i2s_parents, 0x0320, 12, 1),
MUX(CLK_TOP_APLL_I2S2_SEL, "apll_i2s2_sel", apll_i2s_parents, 0x0320, 13, 1),
MUX(CLK_TOP_APLL_I2S3_SEL, "apll_i2s3_sel", apll_i2s_parents, 0x0320, 14, 1),
MUX(CLK_TOP_APLL_TDMOUT_SEL, "apll_tdmout_sel", apll_i2s_parents, 0x0320, 15, 1),
MUX(CLK_TOP_APLL_TDMIN_SEL, "apll_tdmin_sel", apll_i2s_parents, 0x0320, 16, 1),
MUX(CLK_TOP_APLL_SPDIF_SEL, "apll_spdif_sel", apll_i2s_parents, 0x0320, 17, 1),
};
#define CLK_CFG_UPDATE 0x004
@ -787,28 +785,12 @@ static int clk_mt8365_top_probe(struct platform_device *pdev)
if (ret)
goto unregister_factors;
ret = mtk_clk_register_composites(&pdev->dev, top_misc_mux_gates,
ARRAY_SIZE(top_misc_mux_gates), base,
ret = mtk_clk_register_composites(&pdev->dev, top_misc_muxes,
ARRAY_SIZE(top_misc_muxes), base,
&mt8365_clk_lock, clk_data);
if (ret)
goto unregister_muxes;
for (i = 0; i != ARRAY_SIZE(top_misc_muxes); ++i) {
struct mt8365_clk_audio_mux *mux = &top_misc_muxes[i];
struct clk_hw *hw;
hw = devm_clk_hw_register_mux(dev, mux->name, apll_i2s0_parents,
ARRAY_SIZE(apll_i2s0_parents),
CLK_SET_RATE_PARENT, base + 0x320,
mux->shift, 1, 0, NULL);
if (IS_ERR(hw)) {
ret = PTR_ERR(hw);
goto unregister_composites;
}
clk_data->hws[mux->id] = hw;
}
ret = mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
base, &mt8365_clk_lock, clk_data);
if (ret)
@ -830,8 +812,8 @@ unregister_dividers:
mtk_clk_unregister_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
clk_data);
unregister_composites:
mtk_clk_unregister_composites(top_misc_mux_gates,
ARRAY_SIZE(top_misc_mux_gates), clk_data);
mtk_clk_unregister_composites(top_misc_muxes,
ARRAY_SIZE(top_misc_muxes), clk_data);
unregister_muxes:
mtk_clk_unregister_muxes(top_muxes, ARRAY_SIZE(top_muxes), clk_data);
unregister_factors: