iwlwifi: move some msix and rx functions to a common place
We would like to allow other utlities to init msix and rx. Put their declarations in a place accessible to other utilities. Signed-off-by: Golan Ben Ami <golan.ben.ami@intel.com> Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
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@ -45,6 +45,7 @@
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#include "iwl-debug.h"
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#include "iwl-debug.h"
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#include "iwl-io.h"
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#include "iwl-io.h"
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#include "iwl-op-mode.h"
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#include "iwl-op-mode.h"
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#include "iwl-drv.h"
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/* We need 2 entries for the TX command and header, and another one might
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/* We need 2 entries for the TX command and header, and another one might
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* be needed for potential data in the SKB's head. The remaining ones can
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* be needed for potential data in the SKB's head. The remaining ones can
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@ -639,6 +640,20 @@ IWL_TRANS_GET_PCIE_TRANS(struct iwl_trans *trans)
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return (void *)trans->trans_specific;
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return (void *)trans->trans_specific;
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}
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}
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static inline void iwl_pcie_clear_irq(struct iwl_trans *trans,
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struct msix_entry *entry)
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{
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/*
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* Before sending the interrupt the HW disables it to prevent
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* a nested interrupt. This is done by writing 1 to the corresponding
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* bit in the mask register. After handling the interrupt, it should be
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* re-enabled by clearing this bit. This register is defined as
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* write 1 clear (W1C) register, meaning that it's being clear
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* by writing 1 to the bit.
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*/
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iwl_write32(trans, CSR_MSIX_AUTOMASK_ST_AD, BIT(entry->entry));
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}
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static inline struct iwl_trans *
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static inline struct iwl_trans *
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iwl_trans_pcie_get_trans(struct iwl_trans_pcie *trans_pcie)
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iwl_trans_pcie_get_trans(struct iwl_trans_pcie *trans_pcie)
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{
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{
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@ -666,6 +681,11 @@ irqreturn_t iwl_pcie_irq_msix_handler(int irq, void *dev_id);
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irqreturn_t iwl_pcie_irq_rx_msix_handler(int irq, void *dev_id);
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irqreturn_t iwl_pcie_irq_rx_msix_handler(int irq, void *dev_id);
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int iwl_pcie_rx_stop(struct iwl_trans *trans);
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int iwl_pcie_rx_stop(struct iwl_trans *trans);
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void iwl_pcie_rx_free(struct iwl_trans *trans);
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void iwl_pcie_rx_free(struct iwl_trans *trans);
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void iwl_pcie_free_rbs_pool(struct iwl_trans *trans);
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void iwl_pcie_rx_init_rxb_lists(struct iwl_rxq *rxq);
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int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget);
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void iwl_pcie_rxq_alloc_rbs(struct iwl_trans *trans, gfp_t priority,
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struct iwl_rxq *rxq);
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/*****************************************************
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/*****************************************************
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* ICT - interrupt handling
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* ICT - interrupt handling
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@ -892,6 +912,29 @@ static inline void *iwl_pcie_get_tfd(struct iwl_trans *trans,
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return txq->tfds + trans_pcie->tfd_size * idx;
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return txq->tfds + trans_pcie->tfd_size * idx;
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}
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}
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static inline const char *queue_name(struct device *dev,
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struct iwl_trans_pcie *trans_p, int i)
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{
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if (trans_p->shared_vec_mask) {
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int vec = trans_p->shared_vec_mask &
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IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0;
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if (i == 0)
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return DRV_NAME ": shared IRQ";
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return devm_kasprintf(dev, GFP_KERNEL,
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DRV_NAME ": queue %d", i + vec);
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}
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if (i == 0)
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return DRV_NAME ": default queue";
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if (i == trans_p->alloc_vecs - 1)
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return DRV_NAME ": exception";
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return devm_kasprintf(dev, GFP_KERNEL,
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DRV_NAME ": queue %d", i);
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}
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static inline void iwl_enable_rfkill_int(struct iwl_trans *trans)
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static inline void iwl_enable_rfkill_int(struct iwl_trans *trans)
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{
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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@ -417,8 +417,8 @@ static struct page *iwl_pcie_rx_alloc_page(struct iwl_trans *trans,
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* iwl_pcie_rxq_restock. The latter function will update the HW to use the newly
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* iwl_pcie_rxq_restock. The latter function will update the HW to use the newly
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* allocated buffers.
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* allocated buffers.
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*/
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*/
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static void iwl_pcie_rxq_alloc_rbs(struct iwl_trans *trans, gfp_t priority,
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void iwl_pcie_rxq_alloc_rbs(struct iwl_trans *trans, gfp_t priority,
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struct iwl_rxq *rxq)
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struct iwl_rxq *rxq)
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{
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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struct iwl_rx_mem_buffer *rxb;
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struct iwl_rx_mem_buffer *rxb;
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@ -474,7 +474,7 @@ static void iwl_pcie_rxq_alloc_rbs(struct iwl_trans *trans, gfp_t priority,
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}
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}
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}
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}
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static void iwl_pcie_free_rbs_pool(struct iwl_trans *trans)
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void iwl_pcie_free_rbs_pool(struct iwl_trans *trans)
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{
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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int i;
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int i;
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@ -986,7 +986,7 @@ static void iwl_pcie_rx_mq_hw_init(struct iwl_trans *trans)
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iwl_pcie_enable_rx_wake(trans, true);
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iwl_pcie_enable_rx_wake(trans, true);
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}
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}
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static void iwl_pcie_rx_init_rxb_lists(struct iwl_rxq *rxq)
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void iwl_pcie_rx_init_rxb_lists(struct iwl_rxq *rxq)
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{
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{
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lockdep_assert_held(&rxq->lock);
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lockdep_assert_held(&rxq->lock);
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@ -996,7 +996,7 @@ static void iwl_pcie_rx_init_rxb_lists(struct iwl_rxq *rxq)
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rxq->used_count = 0;
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rxq->used_count = 0;
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}
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}
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static int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget)
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int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget)
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{
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{
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WARN_ON(1);
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WARN_ON(1);
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return 0;
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return 0;
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@ -1479,20 +1479,6 @@ static struct iwl_trans_pcie *iwl_pcie_get_trans_pcie(struct msix_entry *entry)
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return container_of(entries, struct iwl_trans_pcie, msix_entries[0]);
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return container_of(entries, struct iwl_trans_pcie, msix_entries[0]);
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}
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}
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static inline void iwl_pcie_clear_irq(struct iwl_trans *trans,
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struct msix_entry *entry)
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{
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/*
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* Before sending the interrupt the HW disables it to prevent
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* a nested interrupt. This is done by writing 1 to the corresponding
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* bit in the mask register. After handling the interrupt, it should be
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* re-enabled by clearing this bit. This register is defined as
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* write 1 clear (W1C) register, meaning that it's being clear
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* by writing 1 to the bit.
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*/
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iwl_write32(trans, CSR_MSIX_AUTOMASK_ST_AD, BIT(entry->entry));
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}
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/*
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/*
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* iwl_pcie_rx_msix_handle - Main entry function for receiving responses from fw
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* iwl_pcie_rx_msix_handle - Main entry function for receiving responses from fw
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* This interrupt handler should be used with RSS queue only.
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* This interrupt handler should be used with RSS queue only.
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@ -1709,29 +1709,6 @@ static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans)
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}
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}
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}
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}
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static const char *queue_name(struct device *dev,
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struct iwl_trans_pcie *trans_p, int i)
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{
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if (trans_p->shared_vec_mask) {
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int vec = trans_p->shared_vec_mask &
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IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0;
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if (i == 0)
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return DRV_NAME ": shared IRQ";
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return devm_kasprintf(dev, GFP_KERNEL,
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DRV_NAME ": queue %d", i + vec);
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}
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if (i == 0)
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return DRV_NAME ": default queue";
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if (i == trans_p->alloc_vecs - 1)
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return DRV_NAME ": exception";
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return devm_kasprintf(dev, GFP_KERNEL,
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DRV_NAME ": queue %d", i);
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}
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static int iwl_pcie_init_msix_handler(struct pci_dev *pdev,
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static int iwl_pcie_init_msix_handler(struct pci_dev *pdev,
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struct iwl_trans_pcie *trans_pcie)
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struct iwl_trans_pcie *trans_pcie)
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{
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{
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