ARM: dts: sun8i: Add PLL6 and MBUS clock nodes
Now that the clock driver supports PLL6 and MBUS on sun8i correctly, add the corresponding clock nodes to the dtsi. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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@ -110,11 +110,19 @@
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/* dummy clock until actually implemented */
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pll6: pll6_clk {
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pll5: pll5_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <600000000>;
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clock-output-names = "pll6";
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clock-frequency = <0>;
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clock-output-names = "pll5";
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};
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pll6: clk@01c20028 {
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#clock-cells = <1>;
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compatible = "allwinner,sun6i-a31-pll6-clk";
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reg = <0x01c20028 0x4>;
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clocks = <&osc24M>;
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clock-output-names = "pll6", "pll6x2";
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};
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cpu: cpu_clk@01c20050 {
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@ -144,7 +152,7 @@
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#clock-cells = <0>;
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compatible = "allwinner,sun6i-a31-ahb1-clk";
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reg = <0x01c20054 0x4>;
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clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
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clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
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clock-output-names = "ahb1";
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};
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@ -185,7 +193,7 @@
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-apb1-clk";
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reg = <0x01c20058 0x4>;
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clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
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clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
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clock-output-names = "apb2";
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};
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@ -204,7 +212,7 @@
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-mod0-clk";
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reg = <0x01c20088 0x4>;
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clocks = <&osc24M>, <&pll6>;
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clocks = <&osc24M>, <&pll6 0>;
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clock-output-names = "mmc0";
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};
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@ -212,7 +220,7 @@
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-mod0-clk";
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reg = <0x01c2008c 0x4>;
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clocks = <&osc24M>, <&pll6>;
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clocks = <&osc24M>, <&pll6 0>;
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clock-output-names = "mmc1";
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};
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@ -220,9 +228,17 @@
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-mod0-clk";
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reg = <0x01c20090 0x4>;
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clocks = <&osc24M>, <&pll6>;
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clocks = <&osc24M>, <&pll6 0>;
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clock-output-names = "mmc2";
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};
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mbus_clk: clk@01c2015c {
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#clock-cells = <0>;
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compatible = "allwinner,sun8i-a23-mbus-clk";
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reg = <0x01c2015c 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5>;
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clock-output-names = "mbus";
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};
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};
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soc@01c00000 {
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