KVM: arm64: Enable GICv3 common sysreg trapping via command-line
Now that we're able to safely handle common sysreg access, let's give the user the opportunity to enable it by passing a specific command-line option (vgic_v3.common_trap). Tested-by: Alexander Graf <agraf@suse.de> Acked-by: David Daney <david.daney@cavium.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Christoffer Dall <cdall@linaro.org> Signed-off-by: Christoffer Dall <cdall@linaro.org>
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@ -1837,6 +1837,10 @@
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[KVM,ARM] Trap guest accesses to GICv3 group-1
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system registers
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kvm-arm.vgic_v3_common_trap=
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[KVM,ARM] Trap guest accesses to GICv3 common
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system registers
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kvm-intel.ept= [KVM,Intel] Disable extended page tables
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(virtualized MMU) support on capable Intel chips.
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Default is 1 (enabled)
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@ -417,6 +417,7 @@
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#define ICH_HCR_EN (1 << 0)
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#define ICH_HCR_UIE (1 << 1)
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#define ICH_HCR_TC (1 << 10)
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#define ICH_HCR_TALL0 (1 << 11)
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#define ICH_HCR_TALL1 (1 << 12)
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#define ICH_HCR_EOIcount_SHIFT 27
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@ -23,6 +23,7 @@
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static bool group0_trap;
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static bool group1_trap;
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static bool common_trap;
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void vgic_v3_set_underflow(struct kvm_vcpu *vcpu)
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{
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@ -265,6 +266,8 @@ void vgic_v3_enable(struct kvm_vcpu *vcpu)
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vgic_v3->vgic_hcr |= ICH_HCR_TALL0;
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if (group1_trap)
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vgic_v3->vgic_hcr |= ICH_HCR_TALL1;
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if (common_trap)
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vgic_v3->vgic_hcr |= ICH_HCR_TC;
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}
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int vgic_v3_lpi_sync_pending_status(struct kvm *kvm, struct vgic_irq *irq)
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@ -450,6 +453,12 @@ static int __init early_group1_trap_cfg(char *buf)
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}
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early_param("kvm-arm.vgic_v3_group1_trap", early_group1_trap_cfg);
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static int __init early_common_trap_cfg(char *buf)
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{
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return strtobool(buf, &common_trap);
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}
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early_param("kvm-arm.vgic_v3_common_trap", early_common_trap_cfg);
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/**
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* vgic_v3_probe - probe for a GICv3 compatible interrupt controller in DT
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* @node: pointer to the DT node
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@ -508,7 +517,7 @@ int vgic_v3_probe(const struct gic_kvm_info *info)
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}
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#endif
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if (group0_trap || group1_trap) {
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if (group0_trap || group1_trap || common_trap) {
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kvm_info("GICv3 sysreg trapping enabled (reduced performance)\n");
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static_branch_enable(&vgic_v3_cpuif_trap);
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}
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