This batch of clk driver updates for the merge window contains almost no new
SoC support. Instead there's a treewide patch series from Maxime that makes
clk_ops::determine_rate mandatory for muxes. Beyond that core framework change
we have the usual pile of clk driver updates such as migrating i2c drivers to
use .probe() again or YAMLfication of clk DT bindings so we can validate DTBs.
Overall the SoCs that got the most updates this time around in terms of
diffstat are the Amlogic and Mediatek drivers because they added new SoC
support or fixed up various drivers to have proper data.
In general things look kinda quiet. I suspect the core framework change may
still shake out some problems after the merge window, mostly because not
everyone tests linux-next where that series has been for some number of weeks.
I saw that there's at least one pending fix for Tegra that needs to be wrapped
up into a proper patch. I'll try to catch those bits before the window closes
so that -rc1 is bootable. More details below.
Core:
- Make clk_ops::determine_rate mandatory for muxes
New Drivers:
- Add amlogic a1 SoC family PLL and peripheral clock controller support
Updates:
- Handle allocation failures from kasprintf() and friends
- Migrate platform clk drivers to .remove_new()
- Migrate i2c clk drivers to .probe() instead of .probe_new()
- Remove CLK_SET_PARENT from all Mediatek MSDC core clocks
- Add infra_ao reset support for Mediatek MT8188 SoCs
- Align driver_data to i2c_device_id tables in some i2c clk drivers
- Use device_get_match_data() in vc5 clk driver
- New Kconfig symbol name (SOC_MICROCHIP_POLARFIRE) for Microchip FPGA clock
drivers
- Use of_property_read_bool() to read "microchip,pic32mzda-sosc" boolean DT
property in clk-pic32mzda
- Convert AT91 clock dt-bindings to YAML
- Remove CLK_SET_RATE_PARENT flag from LDB clocks on i.MX6SX
- Keep i.MX UART clocks enabled during kernel boot if earlycon is set
- Drop imx_unregister_clocks() as there are no users anymore
- Switch to _safe iterator on imx_clk_scu_unregister() to avoid use after free
- Add determine_rate op to the imx8m composite clock
- Use device managed API for iomap and kzalloc for i.MXRT1050, i.MX8MN,
i.MX8MP and i.MX93 clock controller drivers
- Add missing interrupt DT property for the i.MX8M clock controller
- Re-add support for Exynos4212 clock controller because we are
re-introducing the SoC in the mainline
- Add CONFIG_OF dependency to Samsung clk Kconfig symbols to solve some
objtool warnings
- Preselect PLL MIPI as TCON0 parent for Allwinner A64 SoC
- Convert the Renesas clock drivers to readl_poll_timeout_atomic()
- Add PWM clock on Renesas R-Car V3U
- Fix PLL5 on Renesas RZ/G2L and RZ/V2L
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"This batch of clk driver updates contains almost no new SoC support.
Instead there's a treewide patch series from Maxime that makes
clk_ops::determine_rate mandatory for muxes.
Beyond that core framework change we have the usual pile of clk driver
updates such as migrating i2c drivers to use .probe() again or
YAMLfication of clk DT bindings so we can validate DTBs.
Overall the SoCs that got the most updates this time around in terms
of diffstat are the Amlogic and Mediatek drivers because they added
new SoC support or fixed up various drivers to have proper data.
In general things look kinda quiet. I suspect the core framework
change may still shake out some problems after the merge window,
mostly because not everyone tests linux-next where that series has
been for some number of weeks. I saw that there's at least one pending
fix for Tegra that needs to be wrapped up into a proper patch. I'll
try to catch those bits before the window closes so that -rc1 is
bootable. More details below.
Core:
- Make clk_ops::determine_rate mandatory for muxes
New Drivers:
- Add amlogic a1 SoC family PLL and peripheral clock controller support
Updates:
- Handle allocation failures from kasprintf() and friends
- Migrate platform clk drivers to .remove_new()
- Migrate i2c clk drivers to .probe() instead of .probe_new()
- Remove CLK_SET_PARENT from all Mediatek MSDC core clocks
- Add infra_ao reset support for Mediatek MT8188 SoCs
- Align driver_data to i2c_device_id tables in some i2c clk drivers
- Use device_get_match_data() in vc5 clk driver
- New Kconfig symbol name (SOC_MICROCHIP_POLARFIRE) for Microchip
FPGA clock drivers
- Use of_property_read_bool() to read "microchip,pic32mzda-sosc"
boolean DT property in clk-pic32mzda
- Convert AT91 clock dt-bindings to YAML
- Remove CLK_SET_RATE_PARENT flag from LDB clocks on i.MX6SX
- Keep i.MX UART clocks enabled during kernel boot if earlycon is set
- Drop imx_unregister_clocks() as there are no users anymore
- Switch to _safe iterator on imx_clk_scu_unregister() to avoid use
after free
- Add determine_rate op to the imx8m composite clock
- Use device managed API for iomap and kzalloc for i.MXRT1050,
i.MX8MN, i.MX8MP and i.MX93 clock controller drivers
- Add missing interrupt DT property for the i.MX8M clock controller
- Re-add support for Exynos4212 clock controller because we are
re-introducing the SoC in the mainline
- Add CONFIG_OF dependency to Samsung clk Kconfig symbols to solve
some objtool warnings
- Preselect PLL MIPI as TCON0 parent for Allwinner A64 SoC
- Convert the Renesas clock drivers to readl_poll_timeout_atomic()
- Add PWM clock on Renesas R-Car V3U
- Fix PLL5 on Renesas RZ/G2L and RZ/V2L"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (149 commits)
clk: fix typo in clk_hw_register_fixed_rate_parent_data() macro
clk: Fix memory leak in devm_clk_notifier_register()
clk: mvebu: Iterate over possible CPUs instead of DT CPU nodes
clk: mvebu: Use of_get_cpu_hwid() to read CPU ID
MAINTAINERS: Add Marvell mvebu clock drivers
clk: clocking-wizard: check return value of devm_kasprintf()
clk: ti: clkctrl: check return value of kasprintf()
clk: keystone: sci-clk: check return value of kasprintf()
clk: si5341: free unused memory on probe failure
clk: si5341: check return value of {devm_}kasprintf()
clk: si5341: return error if one synth clock registration fails
clk: cdce925: check return value of kasprintf()
clk: vc5: check memory returned by kasprintf()
clk: mediatek: clk-mt8173-apmixedsys: Fix iomap not released issue
clk: mediatek: clk-mt8173-apmixedsys: Fix return value for of_iomap() error
clk: mediatek: clk-mtk: Grab iomem pointer for divider clocks
clk: keystone: syscon-clk: Add support for audio refclk
dt-bindings: clock: Add binding documentation for TI Audio REFCLK
dt-bindings: clock: ehrpwm: Remove unneeded syscon compatible
clk: keystone: syscon-clk: Allow the clock node to not be of type syscon
...
This commit is contained in:
Linus Torvalds
commit
ff7ddcf0db
|
|
@ -0,0 +1,73 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/amlogic,a1-peripherals-clkc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Amlogic A1 Peripherals Clock Control Unit
|
||||
|
||||
maintainers:
|
||||
- Neil Armstrong <neil.armstrong@linaro.org>
|
||||
- Jerome Brunet <jbrunet@baylibre.com>
|
||||
- Jian Hu <jian.hu@jian.hu.com>
|
||||
- Dmitry Rokosov <ddrokosov@sberdevices.ru>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: amlogic,a1-peripherals-clkc
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: input fixed pll div2
|
||||
- description: input fixed pll div3
|
||||
- description: input fixed pll div5
|
||||
- description: input fixed pll div7
|
||||
- description: input hifi pll
|
||||
- description: input oscillator (usually at 24MHz)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: fclk_div2
|
||||
- const: fclk_div3
|
||||
- const: fclk_div5
|
||||
- const: fclk_div7
|
||||
- const: hifi_pll
|
||||
- const: xtal
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- '#clock-cells'
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/amlogic,a1-pll-clkc.h>
|
||||
apb {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
clock-controller@800 {
|
||||
compatible = "amlogic,a1-peripherals-clkc";
|
||||
reg = <0 0x800 0 0x104>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&clkc_pll CLKID_FCLK_DIV2>,
|
||||
<&clkc_pll CLKID_FCLK_DIV3>,
|
||||
<&clkc_pll CLKID_FCLK_DIV5>,
|
||||
<&clkc_pll CLKID_FCLK_DIV7>,
|
||||
<&clkc_pll CLKID_HIFI_PLL>,
|
||||
<&xtal>;
|
||||
clock-names = "fclk_div2", "fclk_div3",
|
||||
"fclk_div5", "fclk_div7",
|
||||
"hifi_pll", "xtal";
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,59 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/amlogic,a1-pll-clkc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Amlogic A1 PLL Clock Control Unit
|
||||
|
||||
maintainers:
|
||||
- Neil Armstrong <neil.armstrong@linaro.org>
|
||||
- Jerome Brunet <jbrunet@baylibre.com>
|
||||
- Jian Hu <jian.hu@jian.hu.com>
|
||||
- Dmitry Rokosov <ddrokosov@sberdevices.ru>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: amlogic,a1-pll-clkc
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: input fixpll_in
|
||||
- description: input hifipll_in
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: fixpll_in
|
||||
- const: hifipll_in
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- '#clock-cells'
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/amlogic,a1-peripherals-clkc.h>
|
||||
apb {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
clock-controller@7c80 {
|
||||
compatible = "amlogic,a1-pll-clkc";
|
||||
reg = <0 0x7c80 0 0x18c>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&clkc_periphs CLKID_FIXPLL_IN>,
|
||||
<&clkc_periphs CLKID_HIFIPLL_IN>;
|
||||
clock-names = "fixpll_in", "hifipll_in";
|
||||
};
|
||||
};
|
||||
|
|
@ -1,58 +0,0 @@
|
|||
Device Tree Clock bindings for arch-at91
|
||||
|
||||
This binding uses the common clock binding[1].
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
Slow Clock controller:
|
||||
|
||||
Required properties:
|
||||
- compatible : shall be one of the following:
|
||||
"atmel,at91sam9x5-sckc",
|
||||
"atmel,sama5d3-sckc",
|
||||
"atmel,sama5d4-sckc" or
|
||||
"microchip,sam9x60-sckc":
|
||||
at91 SCKC (Slow Clock Controller)
|
||||
- #clock-cells : shall be 1 for "microchip,sam9x60-sckc" otherwise shall be 0.
|
||||
- clocks : shall be the input parent clock phandle for the clock.
|
||||
|
||||
Optional properties:
|
||||
- atmel,osc-bypass : boolean property. Set this when a clock signal is directly
|
||||
provided on XIN.
|
||||
|
||||
For example:
|
||||
sckc@fffffe50 {
|
||||
compatible = "atmel,at91sam9x5-sckc";
|
||||
reg = <0xfffffe50 0x4>;
|
||||
clocks = <&slow_xtal>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
Power Management Controller (PMC):
|
||||
|
||||
Required properties:
|
||||
- compatible : shall be "atmel,<chip>-pmc", "syscon" or
|
||||
"microchip,sam9x60-pmc"
|
||||
<chip> can be: at91rm9200, at91sam9260, at91sam9261,
|
||||
at91sam9263, at91sam9g45, at91sam9n12, at91sam9rl, at91sam9g15,
|
||||
at91sam9g25, at91sam9g35, at91sam9x25, at91sam9x35, at91sam9x5,
|
||||
sama5d2, sama5d3 or sama5d4.
|
||||
- #clock-cells : from common clock binding; shall be set to 2. The first entry
|
||||
is the type of the clock (core, system, peripheral or generated) and the
|
||||
second entry its index as provided by the datasheet
|
||||
- clocks : Must contain an entry for each entry in clock-names.
|
||||
- clock-names: Must include the following entries: "slow_clk", "main_xtal"
|
||||
|
||||
Optional properties:
|
||||
- atmel,osc-bypass : boolean property. Set this when a clock signal is directly
|
||||
provided on XIN.
|
||||
|
||||
For example:
|
||||
pmc: pmc@f0018000 {
|
||||
compatible = "atmel,sama5d4-pmc", "syscon";
|
||||
reg = <0xf0018000 0x120>;
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
#clock-cells = <2>;
|
||||
clocks = <&clk32k>, <&main_xtal>;
|
||||
clock-names = "slow_clk", "main_xtal";
|
||||
};
|
||||
|
|
@ -0,0 +1,154 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/atmel,at91rm9200-pmc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Atmel Power Management Controller (PMC)
|
||||
|
||||
maintainers:
|
||||
- Claudiu Beznea <claudiu.beznea@microchip.com>
|
||||
|
||||
description:
|
||||
The power management controller optimizes power consumption by controlling all
|
||||
system and user peripheral clocks. The PMC enables/disables the clock inputs
|
||||
to many of the peripherals and to the processor.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: atmel,at91sam9g20-pmc
|
||||
- const: atmel,at91sam9260-pmc
|
||||
- const: syscon
|
||||
- items:
|
||||
- enum:
|
||||
- atmel,at91sam9g15-pmc
|
||||
- atmel,at91sam9g25-pmc
|
||||
- atmel,at91sam9g35-pmc
|
||||
- atmel,at91sam9x25-pmc
|
||||
- atmel,at91sam9x35-pmc
|
||||
- const: atmel,at91sam9x5-pmc
|
||||
- const: syscon
|
||||
- items:
|
||||
- enum:
|
||||
- atmel,at91rm9200-pmc
|
||||
- atmel,at91sam9260-pmc
|
||||
- atmel,at91sam9g45-pmc
|
||||
- atmel,at91sam9n12-pmc
|
||||
- atmel,at91sam9rl-pmc
|
||||
- atmel,at91sam9x5-pmc
|
||||
- atmel,sama5d2-pmc
|
||||
- atmel,sama5d3-pmc
|
||||
- atmel,sama5d4-pmc
|
||||
- microchip,sam9x60-pmc
|
||||
- microchip,sama7g5-pmc
|
||||
- const: syscon
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
"#clock-cells":
|
||||
description: |
|
||||
- 1st cell is the clock type, one of PMC_TYPE_CORE, PMC_TYPE_SYSTEM,
|
||||
PMC_TYPE_PERIPHERAL, PMC_TYPE_GCK, PMC_TYPE_PROGRAMMABLE (as defined
|
||||
in <dt-bindings/clock/at91.h>)
|
||||
- 2nd cell is the clock identifier as defined in <dt-bindings/clock/at91.h
|
||||
(for core clocks) or as defined in datasheet (for system, peripheral,
|
||||
gck and programmable clocks).
|
||||
const: 2
|
||||
|
||||
clocks:
|
||||
minItems: 2
|
||||
maxItems: 3
|
||||
|
||||
clock-names:
|
||||
minItems: 2
|
||||
maxItems: 3
|
||||
|
||||
atmel,osc-bypass:
|
||||
description: set when a clock signal is directly provided on XIN
|
||||
type: boolean
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- "#clock-cells"
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- microchip,sam9x60-pmc
|
||||
- microchip,sama7g5-pmc
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 3
|
||||
maxItems: 3
|
||||
clock-names:
|
||||
items:
|
||||
- const: td_slck
|
||||
- const: md_slck
|
||||
- const: main_xtal
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- atmel,at91rm9200-pmc
|
||||
- atmel,at91sam9260-pmc
|
||||
- atmel,at91sam9g20-pmc
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
clock-names:
|
||||
items:
|
||||
- const: slow_xtal
|
||||
- const: main_xtal
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- atmel,sama5d2-pmc
|
||||
- atmel,sama5d3-pmc
|
||||
- atmel,sama5d4-pmc
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
clock-names:
|
||||
items:
|
||||
- const: slow_clk
|
||||
- const: main_xtal
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
pmc: clock-controller@f0018000 {
|
||||
compatible = "atmel,sama5d4-pmc", "syscon";
|
||||
reg = <0xf0018000 0x120>;
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
#clock-cells = <2>;
|
||||
clocks = <&clk32k>, <&main_xtal>;
|
||||
clock-names = "slow_clk", "main_xtal";
|
||||
};
|
||||
|
||||
...
|
||||
|
|
@ -0,0 +1,70 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/atmel,at91sam9x5-sckc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Atmel Slow Clock Controller (SCKC)
|
||||
|
||||
maintainers:
|
||||
- Claudiu Beznea <claudiu.beznea@microchip.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- enum:
|
||||
- atmel,at91sam9x5-sckc
|
||||
- atmel,sama5d3-sckc
|
||||
- atmel,sama5d4-sckc
|
||||
- microchip,sam9x60-sckc
|
||||
- items:
|
||||
- const: microchip,sama7g5-sckc
|
||||
- const: microchip,sam9x60-sckc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
"#clock-cells":
|
||||
enum: [0, 1]
|
||||
|
||||
atmel,osc-bypass:
|
||||
type: boolean
|
||||
description: set when a clock signal is directly provided on XIN
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- "#clock-cells"
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- microchip,sam9x60-sckc
|
||||
then:
|
||||
properties:
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
else:
|
||||
properties:
|
||||
"#clock-cells":
|
||||
const: 0
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clk32k: clock-controller@fffffe50 {
|
||||
compatible = "microchip,sam9x60-sckc";
|
||||
reg = <0xfffffe50 0x4>;
|
||||
clocks = <&slow_xtal>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
...
|
||||
|
|
@ -24,6 +24,9 @@ properties:
|
|||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 2
|
||||
|
||||
clocks:
|
||||
minItems: 6
|
||||
maxItems: 7
|
||||
|
|
|
|||
|
|
@ -98,9 +98,9 @@ required:
|
|||
|
||||
patternProperties:
|
||||
"^usb-phy@[a-f0-9]+$":
|
||||
allOf: [ $ref: "../phy/ingenic,phy-usb.yaml#" ]
|
||||
$ref: /schemas/phy/ingenic,phy-usb.yaml#
|
||||
"^mac-phy-ctrl@[a-f0-9]+$":
|
||||
allOf: [ $ref: "../net/ingenic,mac.yaml#" ]
|
||||
$ref: /schemas/net/ingenic,mac.yaml#
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
|
|
|
|||
|
|
@ -48,7 +48,7 @@ properties:
|
|||
patternProperties:
|
||||
"^dma-router@[a-f0-9]+$":
|
||||
type: object
|
||||
$ref: "../dma/renesas,rzn1-dmamux.yaml#"
|
||||
$ref: /schemas/dma/renesas,rzn1-dmamux.yaml#
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
|
|
|||
|
|
@ -24,6 +24,7 @@ properties:
|
|||
- samsung,exynos3250-cmu-dmc
|
||||
- samsung,exynos3250-cmu-isp
|
||||
- samsung,exynos4210-clock
|
||||
- samsung,exynos4212-clock
|
||||
- samsung,exynos4412-clock
|
||||
- samsung,exynos5250-clock
|
||||
- items:
|
||||
|
|
|
|||
|
|
@ -0,0 +1,43 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/ti,am62-audio-refclk.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: TI Audio Reference Clock
|
||||
|
||||
maintainers:
|
||||
- Jai Luthra <j-luthra@ti.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: ti,am62-audio-refclk
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#clock-cells":
|
||||
const: 0
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- "#clock-cells"
|
||||
- clocks
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
audio_refclk0: clock@82e0 {
|
||||
compatible = "ti,am62-audio-refclk";
|
||||
reg = <0x82e0 0x4>;
|
||||
clocks = <&k3_clks 157 0>;
|
||||
assigned-clocks = <&k3_clks 157 0>;
|
||||
assigned-clock-parents = <&k3_clks 157 8>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
|
@ -16,7 +16,6 @@ properties:
|
|||
- ti,am654-ehrpwm-tbclk
|
||||
- ti,am64-epwm-tbclk
|
||||
- ti,am62-epwm-tbclk
|
||||
- const: syscon
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
|
@ -33,8 +32,8 @@ additionalProperties: false
|
|||
|
||||
examples:
|
||||
- |
|
||||
ehrpwm_tbclk: syscon@4140 {
|
||||
compatible = "ti,am654-ehrpwm-tbclk", "syscon";
|
||||
ehrpwm_tbclk: clock@4140 {
|
||||
compatible = "ti,am654-ehrpwm-tbclk";
|
||||
reg = <0x4140 0x18>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1877,6 +1877,7 @@ L: linux-amlogic@lists.infradead.org
|
|||
S: Maintained
|
||||
F: Documentation/devicetree/bindings/clock/amlogic*
|
||||
F: drivers/clk/meson/
|
||||
F: include/dt-bindings/clock/amlogic,a1*
|
||||
F: include/dt-bindings/clock/gxbb*
|
||||
F: include/dt-bindings/clock/meson*
|
||||
|
||||
|
|
@ -2353,6 +2354,7 @@ F: arch/arm/configs/mvebu_*_defconfig
|
|||
F: arch/arm/mach-mvebu/
|
||||
F: arch/arm64/boot/dts/marvell/armada*
|
||||
F: arch/arm64/boot/dts/marvell/cn913*
|
||||
F: drivers/clk/mvebu/
|
||||
F: drivers/cpufreq/armada-37xx-cpufreq.c
|
||||
F: drivers/cpufreq/armada-8k-cpufreq.c
|
||||
F: drivers/cpufreq/mvebu-cpufreq.c
|
||||
|
|
|
|||
|
|
@ -53,13 +53,19 @@ static int owl_comp_is_enabled(struct clk_hw *hw)
|
|||
return owl_gate_clk_is_enabled(common, &comp->gate_hw);
|
||||
}
|
||||
|
||||
static long owl_comp_div_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *parent_rate)
|
||||
static int owl_comp_div_determine_rate(struct clk_hw *hw,
|
||||
struct clk_rate_request *req)
|
||||
{
|
||||
struct owl_composite *comp = hw_to_owl_comp(hw);
|
||||
long rate;
|
||||
|
||||
return owl_divider_helper_round_rate(&comp->common, &comp->rate.div_hw,
|
||||
rate, parent_rate);
|
||||
rate = owl_divider_helper_round_rate(&comp->common, &comp->rate.div_hw,
|
||||
req->rate, &req->best_parent_rate);
|
||||
if (rate < 0)
|
||||
return rate;
|
||||
|
||||
req->rate = rate;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static unsigned long owl_comp_div_recalc_rate(struct clk_hw *hw,
|
||||
|
|
@ -80,14 +86,20 @@ static int owl_comp_div_set_rate(struct clk_hw *hw, unsigned long rate,
|
|||
rate, parent_rate);
|
||||
}
|
||||
|
||||
static long owl_comp_fact_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *parent_rate)
|
||||
static int owl_comp_fact_determine_rate(struct clk_hw *hw,
|
||||
struct clk_rate_request *req)
|
||||
{
|
||||
struct owl_composite *comp = hw_to_owl_comp(hw);
|
||||
long rate;
|
||||
|
||||
return owl_factor_helper_round_rate(&comp->common,
|
||||
&comp->rate.factor_hw,
|
||||
rate, parent_rate);
|
||||
rate = owl_factor_helper_round_rate(&comp->common,
|
||||
&comp->rate.factor_hw,
|
||||
req->rate, &req->best_parent_rate);
|
||||
if (rate < 0)
|
||||
return rate;
|
||||
|
||||
req->rate = rate;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static unsigned long owl_comp_fact_recalc_rate(struct clk_hw *hw,
|
||||
|
|
@ -152,7 +164,7 @@ const struct clk_ops owl_comp_div_ops = {
|
|||
.is_enabled = owl_comp_is_enabled,
|
||||
|
||||
/* div_ops */
|
||||
.round_rate = owl_comp_div_round_rate,
|
||||
.determine_rate = owl_comp_div_determine_rate,
|
||||
.recalc_rate = owl_comp_div_recalc_rate,
|
||||
.set_rate = owl_comp_div_set_rate,
|
||||
};
|
||||
|
|
@ -169,7 +181,7 @@ const struct clk_ops owl_comp_fact_ops = {
|
|||
.is_enabled = owl_comp_is_enabled,
|
||||
|
||||
/* fact_ops */
|
||||
.round_rate = owl_comp_fact_round_rate,
|
||||
.determine_rate = owl_comp_fact_determine_rate,
|
||||
.recalc_rate = owl_comp_fact_recalc_rate,
|
||||
.set_rate = owl_comp_fact_set_rate,
|
||||
};
|
||||
|
|
@ -189,6 +201,7 @@ const struct clk_ops owl_comp_fix_fact_ops = {
|
|||
|
||||
const struct clk_ops owl_comp_pass_ops = {
|
||||
/* mux_ops */
|
||||
.determine_rate = clk_hw_determine_rate_no_reparent,
|
||||
.get_parent = owl_comp_get_parent,
|
||||
.set_parent = owl_comp_set_parent,
|
||||
|
||||
|
|
|
|||
|
|
@ -533,6 +533,7 @@ static const struct clk_ops sam9x5_main_ops = {
|
|||
.prepare = clk_sam9x5_main_prepare,
|
||||
.is_prepared = clk_sam9x5_main_is_prepared,
|
||||
.recalc_rate = clk_sam9x5_main_recalc_rate,
|
||||
.determine_rate = clk_hw_determine_rate_no_reparent,
|
||||
.set_parent = clk_sam9x5_main_set_parent,
|
||||
.get_parent = clk_sam9x5_main_get_parent,
|
||||
.save_context = clk_sam9x5_main_save_context,
|
||||
|
|
|
|||
|
|
@ -36,26 +36,31 @@ static unsigned long at91sam9x5_clk_smd_recalc_rate(struct clk_hw *hw,
|
|||
return parent_rate / (smddiv + 1);
|
||||
}
|
||||
|
||||
static long at91sam9x5_clk_smd_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *parent_rate)
|
||||
static int at91sam9x5_clk_smd_determine_rate(struct clk_hw *hw,
|
||||
struct clk_rate_request *req)
|
||||
{
|
||||
unsigned long div;
|
||||
unsigned long bestrate;
|
||||
unsigned long tmp;
|
||||
|
||||
if (rate >= *parent_rate)
|
||||
return *parent_rate;
|
||||
if (req->rate >= req->best_parent_rate) {
|
||||
req->rate = req->best_parent_rate;
|
||||
return 0;
|
||||
}
|
||||
|
||||
div = *parent_rate / rate;
|
||||
if (div > SMD_MAX_DIV)
|
||||
return *parent_rate / (SMD_MAX_DIV + 1);
|
||||
div = req->best_parent_rate / req->rate;
|
||||
if (div > SMD_MAX_DIV) {
|
||||
req->rate = req->best_parent_rate / (SMD_MAX_DIV + 1);
|
||||
return 0;
|
||||
}
|
||||
|
||||
bestrate = *parent_rate / div;
|
||||
tmp = *parent_rate / (div + 1);
|
||||
if (bestrate - rate > rate - tmp)
|
||||
bestrate = req->best_parent_rate / div;
|
||||
tmp = req->best_parent_rate / (div + 1);
|
||||
if (bestrate - req->rate > req->rate - tmp)
|
||||
bestrate = tmp;
|
||||
|
||||
return bestrate;
|
||||
req->rate = bestrate;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int at91sam9x5_clk_smd_set_parent(struct clk_hw *hw, u8 index)
|
||||
|
|
@ -98,7 +103,7 @@ static int at91sam9x5_clk_smd_set_rate(struct clk_hw *hw, unsigned long rate,
|
|||
|
||||
static const struct clk_ops at91sam9x5_smd_ops = {
|
||||
.recalc_rate = at91sam9x5_clk_smd_recalc_rate,
|
||||
.round_rate = at91sam9x5_clk_smd_round_rate,
|
||||
.determine_rate = at91sam9x5_clk_smd_determine_rate,
|
||||
.get_parent = at91sam9x5_clk_smd_get_parent,
|
||||
.set_parent = at91sam9x5_clk_smd_set_parent,
|
||||
.set_rate = at91sam9x5_clk_smd_set_rate,
|
||||
|
|
|
|||
|
|
@ -310,6 +310,7 @@ static u8 clk_sam9x5_slow_get_parent(struct clk_hw *hw)
|
|||
}
|
||||
|
||||
static const struct clk_ops sam9x5_slow_ops = {
|
||||
.determine_rate = clk_hw_determine_rate_no_reparent,
|
||||
.set_parent = clk_sam9x5_slow_set_parent,
|
||||
.get_parent = clk_sam9x5_slow_get_parent,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -356,9 +356,9 @@ static int raspberrypi_discover_clocks(struct raspberrypi_clk *rpi,
|
|||
while (clks->id) {
|
||||
struct raspberrypi_clk_variant *variant;
|
||||
|
||||
if (clks->id > RPI_FIRMWARE_NUM_CLK_ID) {
|
||||
if (clks->id >= RPI_FIRMWARE_NUM_CLK_ID) {
|
||||
dev_err(rpi->dev, "Unknown clock id: %u (max: %u)\n",
|
||||
clks->id, RPI_FIRMWARE_NUM_CLK_ID);
|
||||
clks->id, RPI_FIRMWARE_NUM_CLK_ID - 1);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -210,6 +210,7 @@ static unsigned long berlin2_div_recalc_rate(struct clk_hw *hw,
|
|||
}
|
||||
|
||||
static const struct clk_ops berlin2_div_rate_ops = {
|
||||
.determine_rate = clk_hw_determine_rate_no_reparent,
|
||||
.recalc_rate = berlin2_div_recalc_rate,
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -384,23 +384,25 @@ static int axi_clkgen_set_rate(struct clk_hw *clk_hw,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static long axi_clkgen_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *parent_rate)
|
||||
static int axi_clkgen_determine_rate(struct clk_hw *hw,
|
||||
struct clk_rate_request *req)
|
||||
{
|
||||
struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(hw);
|
||||
const struct axi_clkgen_limits *limits = &axi_clkgen->limits;
|
||||
unsigned int d, m, dout;
|
||||
unsigned long long tmp;
|
||||
|
||||
axi_clkgen_calc_params(limits, *parent_rate, rate, &d, &m, &dout);
|
||||
axi_clkgen_calc_params(limits, req->best_parent_rate, req->rate,
|
||||
&d, &m, &dout);
|
||||
|
||||
if (d == 0 || dout == 0 || m == 0)
|
||||
return -EINVAL;
|
||||
|
||||
tmp = (unsigned long long)*parent_rate * m;
|
||||
tmp = (unsigned long long)req->best_parent_rate * m;
|
||||
tmp = DIV_ROUND_CLOSEST_ULL(tmp, dout * d);
|
||||
|
||||
return min_t(unsigned long long, tmp, LONG_MAX);
|
||||
req->rate = min_t(unsigned long long, tmp, LONG_MAX);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static unsigned int axi_clkgen_get_div(struct axi_clkgen *axi_clkgen,
|
||||
|
|
@ -495,7 +497,7 @@ static u8 axi_clkgen_get_parent(struct clk_hw *clk_hw)
|
|||
|
||||
static const struct clk_ops axi_clkgen_ops = {
|
||||
.recalc_rate = axi_clkgen_recalc_rate,
|
||||
.round_rate = axi_clkgen_round_rate,
|
||||
.determine_rate = axi_clkgen_determine_rate,
|
||||
.set_rate = axi_clkgen_set_rate,
|
||||
.enable = axi_clkgen_enable,
|
||||
.disable = axi_clkgen_disable,
|
||||
|
|
|
|||
|
|
@ -155,6 +155,7 @@ static u8 cdce706_clkin_get_parent(struct clk_hw *hw)
|
|||
}
|
||||
|
||||
static const struct clk_ops cdce706_clkin_ops = {
|
||||
.determine_rate = clk_hw_determine_rate_no_reparent,
|
||||
.set_parent = cdce706_clkin_set_parent,
|
||||
.get_parent = cdce706_clkin_get_parent,
|
||||
};
|
||||
|
|
@ -287,18 +288,19 @@ static unsigned long cdce706_divider_recalc_rate(struct clk_hw *hw,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static long cdce706_divider_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *parent_rate)
|
||||
static int cdce706_divider_determine_rate(struct clk_hw *hw,
|
||||
struct clk_rate_request *req)
|
||||
{
|
||||
struct cdce706_hw_data *hwd = to_hw_data(hw);
|
||||
struct cdce706_dev_data *cdce = hwd->dev_data;
|
||||
unsigned long rate = req->rate;
|
||||
unsigned long mul, div;
|
||||
|
||||
dev_dbg(&hwd->dev_data->client->dev,
|
||||
"%s, rate: %lu, parent_rate: %lu\n",
|
||||
__func__, rate, *parent_rate);
|
||||
__func__, rate, req->best_parent_rate);
|
||||
|
||||
rational_best_approximation(rate, *parent_rate,
|
||||
rational_best_approximation(rate, req->best_parent_rate,
|
||||
1, CDCE706_DIVIDER_DIVIDER_MAX,
|
||||
&mul, &div);
|
||||
if (!mul)
|
||||
|
|
@ -343,8 +345,8 @@ static long cdce706_divider_round_rate(struct clk_hw *hw, unsigned long rate,
|
|||
|
||||
dev_dbg(&hwd->dev_data->client->dev,
|
||||
"%s, altering parent rate: %lu -> %lu\n",
|
||||
__func__, *parent_rate, rate * div);
|
||||
*parent_rate = rate * div;
|
||||
__func__, req->best_parent_rate, rate * div);
|
||||
req->best_parent_rate = rate * div;
|
||||
}
|
||||
hwd->div = div;
|
||||
|
||||
|
|
@ -352,7 +354,8 @@ static long cdce706_divider_round_rate(struct clk_hw *hw, unsigned long rate,
|
|||
"%s, divider: %d, div: %lu\n",
|
||||
__func__, hwd->idx, div);
|
||||
|
||||
return *parent_rate / div;
|
||||
req->rate = req->best_parent_rate / div;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int cdce706_divider_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
|
|
@ -374,7 +377,7 @@ static const struct clk_ops cdce706_divider_ops = {
|
|||
.set_parent = cdce706_divider_set_parent,
|
||||
.get_parent = cdce706_divider_get_parent,
|
||||
.recalc_rate = cdce706_divider_recalc_rate,
|
||||
.round_rate = cdce706_divider_round_rate,
|
||||
.determine_rate = cdce706_divider_determine_rate,
|
||||
.set_rate = cdce706_divider_set_rate,
|
||||
};
|
||||
|
||||
|
|
@ -420,11 +423,12 @@ static unsigned long cdce706_clkout_recalc_rate(struct clk_hw *hw,
|
|||
return parent_rate;
|
||||
}
|
||||
|
||||
static long cdce706_clkout_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *parent_rate)
|
||||
static int cdce706_clkout_determine_rate(struct clk_hw *hw,
|
||||
struct clk_rate_request *req)
|
||||
{
|
||||
*parent_rate = rate;
|
||||
return rate;
|
||||
req->best_parent_rate = req->rate;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int cdce706_clkout_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
|
|
@ -439,7 +443,7 @@ static const struct clk_ops cdce706_clkout_ops = {
|
|||
.set_parent = cdce706_clkout_set_parent,
|
||||
.get_parent = cdce706_clkout_get_parent,
|
||||
.recalc_rate = cdce706_clkout_recalc_rate,
|
||||
.round_rate = cdce706_clkout_round_rate,
|
||||
.determine_rate = cdce706_clkout_determine_rate,
|
||||
.set_rate = cdce706_clkout_set_rate,
|
||||
};
|
||||
|
||||
|
|
@ -684,7 +688,7 @@ static struct i2c_driver cdce706_i2c_driver = {
|
|||
.name = "cdce706",
|
||||
.of_match_table = of_match_ptr(cdce706_dt_match),
|
||||
},
|
||||
.probe_new = cdce706_probe,
|
||||
.probe = cdce706_probe,
|
||||
.id_table = cdce706_id,
|
||||
};
|
||||
module_i2c_driver(cdce706_i2c_driver);
|
||||
|
|
|
|||
|
|
@ -701,6 +701,10 @@ static int cdce925_probe(struct i2c_client *client)
|
|||
for (i = 0; i < data->chip_info->num_plls; ++i) {
|
||||
pll_clk_name[i] = kasprintf(GFP_KERNEL, "%pOFn.pll%d",
|
||||
client->dev.of_node, i);
|
||||
if (!pll_clk_name[i]) {
|
||||
err = -ENOMEM;
|
||||
goto error;
|
||||
}
|
||||
init.name = pll_clk_name[i];
|
||||
data->pll[i].chip = data;
|
||||
data->pll[i].hw.init = &init;
|
||||
|
|
@ -742,6 +746,10 @@ static int cdce925_probe(struct i2c_client *client)
|
|||
init.num_parents = 1;
|
||||
init.parent_names = &parent_name; /* Mux Y1 to input */
|
||||
init.name = kasprintf(GFP_KERNEL, "%pOFn.Y1", client->dev.of_node);
|
||||
if (!init.name) {
|
||||
err = -ENOMEM;
|
||||
goto error;
|
||||
}
|
||||
data->clk[0].chip = data;
|
||||
data->clk[0].hw.init = &init;
|
||||
data->clk[0].index = 0;
|
||||
|
|
@ -760,6 +768,10 @@ static int cdce925_probe(struct i2c_client *client)
|
|||
for (i = 1; i < data->chip_info->num_outputs; ++i) {
|
||||
init.name = kasprintf(GFP_KERNEL, "%pOFn.Y%d",
|
||||
client->dev.of_node, i+1);
|
||||
if (!init.name) {
|
||||
err = -ENOMEM;
|
||||
goto error;
|
||||
}
|
||||
data->clk[i].chip = data;
|
||||
data->clk[i].hw.init = &init;
|
||||
data->clk[i].index = i;
|
||||
|
|
@ -824,7 +836,7 @@ static struct i2c_driver cdce925_driver = {
|
|||
.name = "cdce925",
|
||||
.of_match_table = of_match_ptr(clk_cdce925_of_match),
|
||||
},
|
||||
.probe_new = cdce925_probe,
|
||||
.probe = cdce925_probe,
|
||||
.id_table = cdce925_id,
|
||||
};
|
||||
module_i2c_driver(cdce925_driver);
|
||||
|
|
|
|||
|
|
@ -622,7 +622,7 @@ static struct i2c_driver cs2000_driver = {
|
|||
.pm = &cs2000_pm_ops,
|
||||
.of_match_table = cs2000_of_match,
|
||||
},
|
||||
.probe_new = cs2000_probe,
|
||||
.probe = cs2000_probe,
|
||||
.remove = cs2000_remove,
|
||||
.id_table = cs2000_id,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -537,6 +537,7 @@ static const struct clk_ops k210_pll2_ops = {
|
|||
.disable = k210_pll_disable,
|
||||
.is_enabled = k210_pll_is_enabled,
|
||||
.recalc_rate = k210_pll_get_rate,
|
||||
.determine_rate = clk_hw_determine_rate_no_reparent,
|
||||
.set_parent = k210_pll2_set_parent,
|
||||
.get_parent = k210_pll2_get_parent,
|
||||
};
|
||||
|
|
@ -635,6 +636,7 @@ static unsigned long k210_aclk_get_rate(struct clk_hw *hw,
|
|||
}
|
||||
|
||||
static const struct clk_ops k210_aclk_ops = {
|
||||
.determine_rate = clk_hw_determine_rate_no_reparent,
|
||||
.set_parent = k210_aclk_set_parent,
|
||||
.get_parent = k210_aclk_get_parent,
|
||||
.recalc_rate = k210_aclk_get_rate,
|
||||
|
|
@ -774,6 +776,7 @@ static unsigned long k210_clk_get_rate(struct clk_hw *hw,
|
|||
static const struct clk_ops k210_clk_mux_ops = {
|
||||
.enable = k210_clk_enable,
|
||||
.disable = k210_clk_disable,
|
||||
.determine_rate = clk_hw_determine_rate_no_reparent,
|
||||
.set_parent = k210_clk_set_parent,
|
||||
.get_parent = k210_clk_get_parent,
|
||||
.recalc_rate = k210_clk_get_rate,
|
||||
|
|
|
|||
|
|
@ -103,22 +103,6 @@ static int lan966x_gck_set_rate(struct clk_hw *hw,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static long lan966x_gck_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *parent_rate)
|
||||
{
|
||||
unsigned int div;
|
||||
|
||||
if (rate == 0 || *parent_rate == 0)
|
||||
return -EINVAL;
|
||||
|
||||
if (rate >= *parent_rate)
|
||||
return *parent_rate;
|
||||
|
||||
div = DIV_ROUND_CLOSEST(*parent_rate, rate);
|
||||
|
||||
return *parent_rate / div;
|
||||
}
|
||||
|
||||
static unsigned long lan966x_gck_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
|
|
@ -177,7 +161,6 @@ static const struct clk_ops lan966x_gck_ops = {
|
|||
.enable = lan966x_gck_enable,
|
||||
.disable = lan966x_gck_disable,
|
||||
.set_rate = lan966x_gck_set_rate,
|
||||
.round_rate = lan966x_gck_round_rate,
|
||||
.recalc_rate = lan966x_gck_recalc_rate,
|
||||
.determine_rate = lan966x_gck_determine_rate,
|
||||
.set_parent = lan966x_gck_set_parent,
|
||||
|
|
|
|||
|
|
@ -1279,6 +1279,7 @@ static const struct clk_ops lmk04832_clkout_ops = {
|
|||
.is_enabled = lmk04832_clkout_is_enabled,
|
||||
.prepare = lmk04832_clkout_prepare,
|
||||
.unprepare = lmk04832_clkout_unprepare,
|
||||
.determine_rate = __clk_mux_determine_rate,
|
||||
.set_parent = lmk04832_clkout_set_parent,
|
||||
.get_parent = lmk04832_clkout_get_parent,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -209,6 +209,7 @@ static u8 lochnagar_clk_get_parent(struct clk_hw *hw)
|
|||
static const struct clk_ops lochnagar_clk_ops = {
|
||||
.prepare = lochnagar_clk_prepare,
|
||||
.unprepare = lochnagar_clk_unprepare,
|
||||
.determine_rate = clk_hw_determine_rate_no_reparent,
|
||||
.set_parent = lochnagar_clk_set_parent,
|
||||
.get_parent = lochnagar_clk_get_parent,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -376,7 +376,7 @@ static struct i2c_driver max9485_driver = {
|
|||
.pm = &max9485_pm_ops,
|
||||
.of_match_table = max9485_dt_ids,
|
||||
},
|
||||
.probe_new = max9485_i2c_probe,
|
||||
.probe = max9485_i2c_probe,
|
||||
.id_table = max9485_i2c_ids,
|
||||
};
|
||||
module_i2c_driver(max9485_driver);
|
||||
|
|
|
|||
|
|
@ -878,6 +878,7 @@ static u8 mux_get_parent(struct clk_hw *hw)
|
|||
}
|
||||
|
||||
static const struct clk_ops cmux_ops = {
|
||||
.determine_rate = clk_hw_determine_rate_no_reparent,
|
||||
.get_parent = mux_get_parent,
|
||||
.set_parent = mux_set_parent,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -392,8 +392,8 @@ static const struct rs9_chip_info renesas_9fgv0441_info = {
|
|||
};
|
||||
|
||||
static const struct i2c_device_id rs9_id[] = {
|
||||
{ "9fgv0241", .driver_data = RENESAS_9FGV0241 },
|
||||
{ "9fgv0441", .driver_data = RENESAS_9FGV0441 },
|
||||
{ "9fgv0241", .driver_data = (kernel_ulong_t)&renesas_9fgv0241_info },
|
||||
{ "9fgv0441", .driver_data = (kernel_ulong_t)&renesas_9fgv0441_info },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(i2c, rs9_id);
|
||||
|
|
@ -413,7 +413,7 @@ static struct i2c_driver rs9_driver = {
|
|||
.pm = &rs9_pm_ops,
|
||||
.of_match_table = clk_rs9_of_match,
|
||||
},
|
||||
.probe_new = rs9_probe,
|
||||
.probe = rs9_probe,
|
||||
.id_table = rs9_id,
|
||||
};
|
||||
module_i2c_driver(rs9_driver);
|
||||
|
|
|
|||
|
|
@ -387,7 +387,7 @@ static struct i2c_driver si514_driver = {
|
|||
.name = "si514",
|
||||
.of_match_table = clk_si514_of_match,
|
||||
},
|
||||
.probe_new = si514_probe,
|
||||
.probe = si514_probe,
|
||||
.id_table = si514_id,
|
||||
};
|
||||
module_i2c_driver(si514_driver);
|
||||
|
|
|
|||
|
|
@ -385,7 +385,7 @@ static struct i2c_driver si521xx_driver = {
|
|||
.pm = &si521xx_pm_ops,
|
||||
.of_match_table = clk_si521xx_of_match,
|
||||
},
|
||||
.probe_new = si521xx_probe,
|
||||
.probe = si521xx_probe,
|
||||
.id_table = si521xx_id,
|
||||
};
|
||||
module_i2c_driver(si521xx_driver);
|
||||
|
|
|
|||
|
|
@ -551,6 +551,7 @@ static int si5341_clk_set_parent(struct clk_hw *hw, u8 index)
|
|||
}
|
||||
|
||||
static const struct clk_ops si5341_clk_ops = {
|
||||
.determine_rate = clk_hw_determine_rate_no_reparent,
|
||||
.set_parent = si5341_clk_set_parent,
|
||||
.get_parent = si5341_clk_get_parent,
|
||||
.recalc_rate = si5341_clk_recalc_rate,
|
||||
|
|
@ -827,19 +828,20 @@ static unsigned long si5341_output_clk_recalc_rate(struct clk_hw *hw,
|
|||
return parent_rate / r_divider;
|
||||
}
|
||||
|
||||
static long si5341_output_clk_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *parent_rate)
|
||||
static int si5341_output_clk_determine_rate(struct clk_hw *hw,
|
||||
struct clk_rate_request *req)
|
||||
{
|
||||
unsigned long rate = req->rate;
|
||||
unsigned long r;
|
||||
|
||||
if (!rate)
|
||||
return 0;
|
||||
|
||||
r = *parent_rate >> 1;
|
||||
r = req->best_parent_rate >> 1;
|
||||
|
||||
/* If rate is an even divisor, no changes to parent required */
|
||||
if (r && !(r % rate))
|
||||
return (long)rate;
|
||||
return 0;
|
||||
|
||||
if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
|
||||
if (rate > 200000000) {
|
||||
|
|
@ -849,14 +851,15 @@ static long si5341_output_clk_round_rate(struct clk_hw *hw, unsigned long rate,
|
|||
/* Take a parent frequency near 400 MHz */
|
||||
r = (400000000u / rate) & ~1;
|
||||
}
|
||||
*parent_rate = r * rate;
|
||||
req->best_parent_rate = r * rate;
|
||||
} else {
|
||||
/* We cannot change our parent's rate, report what we can do */
|
||||
r /= rate;
|
||||
rate = *parent_rate / (r << 1);
|
||||
rate = req->best_parent_rate / (r << 1);
|
||||
}
|
||||
|
||||
return rate;
|
||||
req->rate = rate;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int si5341_output_clk_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
|
|
@ -929,7 +932,7 @@ static const struct clk_ops si5341_output_clk_ops = {
|
|||
.prepare = si5341_output_clk_prepare,
|
||||
.unprepare = si5341_output_clk_unprepare,
|
||||
.recalc_rate = si5341_output_clk_recalc_rate,
|
||||
.round_rate = si5341_output_clk_round_rate,
|
||||
.determine_rate = si5341_output_clk_determine_rate,
|
||||
.set_rate = si5341_output_clk_set_rate,
|
||||
.set_parent = si5341_output_set_parent,
|
||||
.get_parent = si5341_output_get_parent,
|
||||
|
|
@ -1553,7 +1556,7 @@ static int si5341_probe(struct i2c_client *client)
|
|||
struct clk_init_data init;
|
||||
struct clk *input;
|
||||
const char *root_clock_name;
|
||||
const char *synth_clock_names[SI5341_NUM_SYNTH];
|
||||
const char *synth_clock_names[SI5341_NUM_SYNTH] = { NULL };
|
||||
int err;
|
||||
unsigned int i;
|
||||
struct clk_si5341_output_config config[SI5341_MAX_NUM_OUTPUTS];
|
||||
|
|
@ -1697,6 +1700,10 @@ static int si5341_probe(struct i2c_client *client)
|
|||
for (i = 0; i < data->num_synth; ++i) {
|
||||
synth_clock_names[i] = devm_kasprintf(&client->dev, GFP_KERNEL,
|
||||
"%s.N%u", client->dev.of_node->name, i);
|
||||
if (!synth_clock_names[i]) {
|
||||
err = -ENOMEM;
|
||||
goto free_clk_names;
|
||||
}
|
||||
init.name = synth_clock_names[i];
|
||||
data->synth[i].index = i;
|
||||
data->synth[i].data = data;
|
||||
|
|
@ -1705,6 +1712,7 @@ static int si5341_probe(struct i2c_client *client)
|
|||
if (err) {
|
||||
dev_err(&client->dev,
|
||||
"synth N%u registration failed\n", i);
|
||||
goto free_clk_names;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1714,6 +1722,10 @@ static int si5341_probe(struct i2c_client *client)
|
|||
for (i = 0; i < data->num_outputs; ++i) {
|
||||
init.name = kasprintf(GFP_KERNEL, "%s.%d",
|
||||
client->dev.of_node->name, i);
|
||||
if (!init.name) {
|
||||
err = -ENOMEM;
|
||||
goto free_clk_names;
|
||||
}
|
||||
init.flags = config[i].synth_master ? CLK_SET_RATE_PARENT : 0;
|
||||
data->clk[i].index = i;
|
||||
data->clk[i].data = data;
|
||||
|
|
@ -1735,7 +1747,7 @@ static int si5341_probe(struct i2c_client *client)
|
|||
if (err) {
|
||||
dev_err(&client->dev,
|
||||
"output %u registration failed\n", i);
|
||||
goto cleanup;
|
||||
goto free_clk_names;
|
||||
}
|
||||
if (config[i].always_on)
|
||||
clk_prepare(data->clk[i].hw.clk);
|
||||
|
|
@ -1745,7 +1757,7 @@ static int si5341_probe(struct i2c_client *client)
|
|||
data);
|
||||
if (err) {
|
||||
dev_err(&client->dev, "unable to add clk provider\n");
|
||||
goto cleanup;
|
||||
goto free_clk_names;
|
||||
}
|
||||
|
||||
if (initialization_required) {
|
||||
|
|
@ -1753,11 +1765,11 @@ static int si5341_probe(struct i2c_client *client)
|
|||
regcache_cache_only(data->regmap, false);
|
||||
err = regcache_sync(data->regmap);
|
||||
if (err < 0)
|
||||
goto cleanup;
|
||||
goto free_clk_names;
|
||||
|
||||
err = si5341_finalize_defaults(data);
|
||||
if (err < 0)
|
||||
goto cleanup;
|
||||
goto free_clk_names;
|
||||
}
|
||||
|
||||
/* wait for device to report input clock present and PLL lock */
|
||||
|
|
@ -1766,32 +1778,31 @@ static int si5341_probe(struct i2c_client *client)
|
|||
10000, 250000);
|
||||
if (err) {
|
||||
dev_err(&client->dev, "Error waiting for input clock or PLL lock\n");
|
||||
goto cleanup;
|
||||
goto free_clk_names;
|
||||
}
|
||||
|
||||
/* clear sticky alarm bits from initialization */
|
||||
err = regmap_write(data->regmap, SI5341_STATUS_STICKY, 0);
|
||||
if (err) {
|
||||
dev_err(&client->dev, "unable to clear sticky status\n");
|
||||
goto cleanup;
|
||||
goto free_clk_names;
|
||||
}
|
||||
|
||||
err = sysfs_create_files(&client->dev.kobj, si5341_attributes);
|
||||
if (err) {
|
||||
if (err)
|
||||
dev_err(&client->dev, "unable to create sysfs files\n");
|
||||
goto cleanup;
|
||||
}
|
||||
|
||||
free_clk_names:
|
||||
/* Free the names, clk framework makes copies */
|
||||
for (i = 0; i < data->num_synth; ++i)
|
||||
devm_kfree(&client->dev, (void *)synth_clock_names[i]);
|
||||
|
||||
return 0;
|
||||
|
||||
cleanup:
|
||||
for (i = 0; i < SI5341_MAX_NUM_OUTPUTS; ++i) {
|
||||
if (data->clk[i].vddo_reg)
|
||||
regulator_disable(data->clk[i].vddo_reg);
|
||||
if (err) {
|
||||
for (i = 0; i < SI5341_MAX_NUM_OUTPUTS; ++i) {
|
||||
if (data->clk[i].vddo_reg)
|
||||
regulator_disable(data->clk[i].vddo_reg);
|
||||
}
|
||||
}
|
||||
return err;
|
||||
}
|
||||
|
|
@ -1834,7 +1845,7 @@ static struct i2c_driver si5341_driver = {
|
|||
.name = "si5341",
|
||||
.of_match_table = clk_si5341_of_match,
|
||||
},
|
||||
.probe_new = si5341_probe,
|
||||
.probe = si5341_probe,
|
||||
.remove = si5341_remove,
|
||||
.id_table = si5341_id,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -442,11 +442,12 @@ static unsigned long si5351_pll_recalc_rate(struct clk_hw *hw,
|
|||
return (unsigned long)rate;
|
||||
}
|
||||
|
||||
static long si5351_pll_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *parent_rate)
|
||||
static int si5351_pll_determine_rate(struct clk_hw *hw,
|
||||
struct clk_rate_request *req)
|
||||
{
|
||||
struct si5351_hw_data *hwdata =
|
||||
container_of(hw, struct si5351_hw_data, hw);
|
||||
unsigned long rate = req->rate;
|
||||
unsigned long rfrac, denom, a, b, c;
|
||||
unsigned long long lltmp;
|
||||
|
||||
|
|
@ -456,18 +457,18 @@ static long si5351_pll_round_rate(struct clk_hw *hw, unsigned long rate,
|
|||
rate = SI5351_PLL_VCO_MAX;
|
||||
|
||||
/* determine integer part of feedback equation */
|
||||
a = rate / *parent_rate;
|
||||
a = rate / req->best_parent_rate;
|
||||
|
||||
if (a < SI5351_PLL_A_MIN)
|
||||
rate = *parent_rate * SI5351_PLL_A_MIN;
|
||||
rate = req->best_parent_rate * SI5351_PLL_A_MIN;
|
||||
if (a > SI5351_PLL_A_MAX)
|
||||
rate = *parent_rate * SI5351_PLL_A_MAX;
|
||||
rate = req->best_parent_rate * SI5351_PLL_A_MAX;
|
||||
|
||||
/* find best approximation for b/c = fVCO mod fIN */
|
||||
denom = 1000 * 1000;
|
||||
lltmp = rate % (*parent_rate);
|
||||
lltmp = rate % (req->best_parent_rate);
|
||||
lltmp *= denom;
|
||||
do_div(lltmp, *parent_rate);
|
||||
do_div(lltmp, req->best_parent_rate);
|
||||
rfrac = (unsigned long)lltmp;
|
||||
|
||||
b = 0;
|
||||
|
|
@ -484,19 +485,20 @@ static long si5351_pll_round_rate(struct clk_hw *hw, unsigned long rate,
|
|||
hwdata->params.p1 -= 512;
|
||||
|
||||
/* recalculate rate by fIN * (a + b/c) */
|
||||
lltmp = *parent_rate;
|
||||
lltmp = req->best_parent_rate;
|
||||
lltmp *= b;
|
||||
do_div(lltmp, c);
|
||||
|
||||
rate = (unsigned long)lltmp;
|
||||
rate += *parent_rate * a;
|
||||
rate += req->best_parent_rate * a;
|
||||
|
||||
dev_dbg(&hwdata->drvdata->client->dev,
|
||||
"%s - %s: a = %lu, b = %lu, c = %lu, parent_rate = %lu, rate = %lu\n",
|
||||
__func__, clk_hw_get_name(hw), a, b, c,
|
||||
*parent_rate, rate);
|
||||
req->best_parent_rate, rate);
|
||||
|
||||
return rate;
|
||||
req->rate = rate;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int si5351_pll_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
|
|
@ -533,7 +535,7 @@ static const struct clk_ops si5351_pll_ops = {
|
|||
.set_parent = si5351_pll_set_parent,
|
||||
.get_parent = si5351_pll_get_parent,
|
||||
.recalc_rate = si5351_pll_recalc_rate,
|
||||
.round_rate = si5351_pll_round_rate,
|
||||
.determine_rate = si5351_pll_determine_rate,
|
||||
.set_rate = si5351_pll_set_rate,
|
||||
};
|
||||
|
||||
|
|
@ -640,11 +642,12 @@ static unsigned long si5351_msynth_recalc_rate(struct clk_hw *hw,
|
|||
return (unsigned long)rate;
|
||||
}
|
||||
|
||||
static long si5351_msynth_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *parent_rate)
|
||||
static int si5351_msynth_determine_rate(struct clk_hw *hw,
|
||||
struct clk_rate_request *req)
|
||||
{
|
||||
struct si5351_hw_data *hwdata =
|
||||
container_of(hw, struct si5351_hw_data, hw);
|
||||
unsigned long rate = req->rate;
|
||||
unsigned long long lltmp;
|
||||
unsigned long a, b, c;
|
||||
int divby4;
|
||||
|
|
@ -679,10 +682,10 @@ static long si5351_msynth_round_rate(struct clk_hw *hw, unsigned long rate,
|
|||
b = 0;
|
||||
c = 1;
|
||||
|
||||
*parent_rate = a * rate;
|
||||
req->best_parent_rate = a * rate;
|
||||
} else if (hwdata->num >= 6) {
|
||||
/* determine the closest integer divider */
|
||||
a = DIV_ROUND_CLOSEST(*parent_rate, rate);
|
||||
a = DIV_ROUND_CLOSEST(req->best_parent_rate, rate);
|
||||
if (a < SI5351_MULTISYNTH_A_MIN)
|
||||
a = SI5351_MULTISYNTH_A_MIN;
|
||||
if (a > SI5351_MULTISYNTH67_A_MAX)
|
||||
|
|
@ -700,7 +703,7 @@ static long si5351_msynth_round_rate(struct clk_hw *hw, unsigned long rate,
|
|||
}
|
||||
|
||||
/* determine integer part of divider equation */
|
||||
a = *parent_rate / rate;
|
||||
a = req->best_parent_rate / rate;
|
||||
if (a < SI5351_MULTISYNTH_A_MIN)
|
||||
a = SI5351_MULTISYNTH_A_MIN;
|
||||
if (a > SI5351_MULTISYNTH_A_MAX)
|
||||
|
|
@ -708,7 +711,7 @@ static long si5351_msynth_round_rate(struct clk_hw *hw, unsigned long rate,
|
|||
|
||||
/* find best approximation for b/c = fVCO mod fOUT */
|
||||
denom = 1000 * 1000;
|
||||
lltmp = (*parent_rate) % rate;
|
||||
lltmp = req->best_parent_rate % rate;
|
||||
lltmp *= denom;
|
||||
do_div(lltmp, rate);
|
||||
rfrac = (unsigned long)lltmp;
|
||||
|
|
@ -722,7 +725,7 @@ static long si5351_msynth_round_rate(struct clk_hw *hw, unsigned long rate,
|
|||
}
|
||||
|
||||
/* recalculate rate by fOUT = fIN / (a + b/c) */
|
||||
lltmp = *parent_rate;
|
||||
lltmp = req->best_parent_rate;
|
||||
lltmp *= c;
|
||||
do_div(lltmp, a * c + b);
|
||||
rate = (unsigned long)lltmp;
|
||||
|
|
@ -747,9 +750,11 @@ static long si5351_msynth_round_rate(struct clk_hw *hw, unsigned long rate,
|
|||
dev_dbg(&hwdata->drvdata->client->dev,
|
||||
"%s - %s: a = %lu, b = %lu, c = %lu, divby4 = %d, parent_rate = %lu, rate = %lu\n",
|
||||
__func__, clk_hw_get_name(hw), a, b, c, divby4,
|
||||
*parent_rate, rate);
|
||||
req->best_parent_rate, rate);
|
||||
|
||||
return rate;
|
||||
req->rate = rate;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int si5351_msynth_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
|
|
@ -789,7 +794,7 @@ static const struct clk_ops si5351_msynth_ops = {
|
|||
.set_parent = si5351_msynth_set_parent,
|
||||
.get_parent = si5351_msynth_get_parent,
|
||||
.recalc_rate = si5351_msynth_recalc_rate,
|
||||
.round_rate = si5351_msynth_round_rate,
|
||||
.determine_rate = si5351_msynth_determine_rate,
|
||||
.set_rate = si5351_msynth_set_rate,
|
||||
};
|
||||
|
||||
|
|
@ -1032,11 +1037,12 @@ static unsigned long si5351_clkout_recalc_rate(struct clk_hw *hw,
|
|||
return parent_rate >> rdiv;
|
||||
}
|
||||
|
||||
static long si5351_clkout_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *parent_rate)
|
||||
static int si5351_clkout_determine_rate(struct clk_hw *hw,
|
||||
struct clk_rate_request *req)
|
||||
{
|
||||
struct si5351_hw_data *hwdata =
|
||||
container_of(hw, struct si5351_hw_data, hw);
|
||||
unsigned long rate = req->rate;
|
||||
unsigned char rdiv;
|
||||
|
||||
/* clkout6/7 can only handle output freqencies < 150MHz */
|
||||
|
|
@ -1058,13 +1064,13 @@ static long si5351_clkout_round_rate(struct clk_hw *hw, unsigned long rate,
|
|||
rdiv += 1;
|
||||
rate *= 2;
|
||||
}
|
||||
*parent_rate = rate;
|
||||
req->best_parent_rate = rate;
|
||||
} else {
|
||||
unsigned long new_rate, new_err, err;
|
||||
|
||||
/* round to closed rdiv */
|
||||
rdiv = SI5351_OUTPUT_CLK_DIV_1;
|
||||
new_rate = *parent_rate;
|
||||
new_rate = req->best_parent_rate;
|
||||
err = abs(new_rate - rate);
|
||||
do {
|
||||
new_rate >>= 1;
|
||||
|
|
@ -1075,14 +1081,15 @@ static long si5351_clkout_round_rate(struct clk_hw *hw, unsigned long rate,
|
|||
err = new_err;
|
||||
} while (1);
|
||||
}
|
||||
rate = *parent_rate >> rdiv;
|
||||
rate = req->best_parent_rate >> rdiv;
|
||||
|
||||
dev_dbg(&hwdata->drvdata->client->dev,
|
||||
"%s - %s: rdiv = %u, parent_rate = %lu, rate = %lu\n",
|
||||
__func__, clk_hw_get_name(hw), (1 << rdiv),
|
||||
*parent_rate, rate);
|
||||
req->best_parent_rate, rate);
|
||||
|
||||
return rate;
|
||||
req->rate = rate;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int si5351_clkout_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
|
|
@ -1142,7 +1149,7 @@ static const struct clk_ops si5351_clkout_ops = {
|
|||
.set_parent = si5351_clkout_set_parent,
|
||||
.get_parent = si5351_clkout_get_parent,
|
||||
.recalc_rate = si5351_clkout_recalc_rate,
|
||||
.round_rate = si5351_clkout_round_rate,
|
||||
.determine_rate = si5351_clkout_determine_rate,
|
||||
.set_rate = si5351_clkout_set_rate,
|
||||
};
|
||||
|
||||
|
|
@ -1656,7 +1663,7 @@ static struct i2c_driver si5351_driver = {
|
|||
.name = "si5351",
|
||||
.of_match_table = of_match_ptr(si5351_dt_ids),
|
||||
},
|
||||
.probe_new = si5351_i2c_probe,
|
||||
.probe = si5351_i2c_probe,
|
||||
.id_table = si5351_i2c_ids,
|
||||
};
|
||||
module_i2c_driver(si5351_driver);
|
||||
|
|
|
|||
|
|
@ -520,7 +520,7 @@ static struct i2c_driver si544_driver = {
|
|||
.name = "si544",
|
||||
.of_match_table = clk_si544_of_match,
|
||||
},
|
||||
.probe_new = si544_probe,
|
||||
.probe = si544_probe,
|
||||
.id_table = si544_id,
|
||||
};
|
||||
module_i2c_driver(si544_driver);
|
||||
|
|
|
|||
|
|
@ -510,7 +510,7 @@ static struct i2c_driver si570_driver = {
|
|||
.name = "si570",
|
||||
.of_match_table = clk_si570_of_match,
|
||||
},
|
||||
.probe_new = si570_probe,
|
||||
.probe = si570_probe,
|
||||
.id_table = si570_id,
|
||||
};
|
||||
module_i2c_driver(si570_driver);
|
||||
|
|
|
|||
|
|
@ -1045,6 +1045,7 @@ static int cclk_mux_set_parent(struct clk_hw *hw, u8 index)
|
|||
}
|
||||
|
||||
static const struct clk_ops cclk_mux_ops = {
|
||||
.determine_rate = clk_hw_determine_rate_no_reparent,
|
||||
.get_parent = cclk_mux_get_parent,
|
||||
.set_parent = cclk_mux_set_parent,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -20,6 +20,7 @@
|
|||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/property.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/slab.h>
|
||||
|
||||
|
|
@ -281,6 +282,7 @@ static int vc5_mux_set_parent(struct clk_hw *hw, u8 index)
|
|||
}
|
||||
|
||||
static const struct clk_ops vc5_mux_ops = {
|
||||
.determine_rate = clk_hw_determine_rate_no_reparent,
|
||||
.set_parent = vc5_mux_set_parent,
|
||||
.get_parent = vc5_mux_get_parent,
|
||||
};
|
||||
|
|
@ -725,6 +727,7 @@ static int vc5_clk_out_set_parent(struct clk_hw *hw, u8 index)
|
|||
static const struct clk_ops vc5_clk_out_ops = {
|
||||
.prepare = vc5_clk_out_prepare,
|
||||
.unprepare = vc5_clk_out_unprepare,
|
||||
.determine_rate = clk_hw_determine_rate_no_reparent,
|
||||
.set_parent = vc5_clk_out_set_parent,
|
||||
.get_parent = vc5_clk_out_get_parent,
|
||||
};
|
||||
|
|
@ -953,7 +956,7 @@ static int vc5_probe(struct i2c_client *client)
|
|||
|
||||
i2c_set_clientdata(client, vc5);
|
||||
vc5->client = client;
|
||||
vc5->chip_info = of_device_get_match_data(&client->dev);
|
||||
vc5->chip_info = device_get_match_data(&client->dev);
|
||||
|
||||
vc5->pin_xin = devm_clk_get(&client->dev, "xin");
|
||||
if (PTR_ERR(vc5->pin_xin) == -EPROBE_DEFER)
|
||||
|
|
@ -1028,6 +1031,11 @@ static int vc5_probe(struct i2c_client *client)
|
|||
}
|
||||
|
||||
init.name = kasprintf(GFP_KERNEL, "%pOFn.mux", client->dev.of_node);
|
||||
if (!init.name) {
|
||||
ret = -ENOMEM;
|
||||
goto err_clk;
|
||||
}
|
||||
|
||||
init.ops = &vc5_mux_ops;
|
||||
init.flags = 0;
|
||||
init.parent_names = parent_names;
|
||||
|
|
@ -1042,6 +1050,10 @@ static int vc5_probe(struct i2c_client *client)
|
|||
memset(&init, 0, sizeof(init));
|
||||
init.name = kasprintf(GFP_KERNEL, "%pOFn.dbl",
|
||||
client->dev.of_node);
|
||||
if (!init.name) {
|
||||
ret = -ENOMEM;
|
||||
goto err_clk;
|
||||
}
|
||||
init.ops = &vc5_dbl_ops;
|
||||
init.flags = CLK_SET_RATE_PARENT;
|
||||
init.parent_names = parent_names;
|
||||
|
|
@ -1057,6 +1069,10 @@ static int vc5_probe(struct i2c_client *client)
|
|||
/* Register PFD */
|
||||
memset(&init, 0, sizeof(init));
|
||||
init.name = kasprintf(GFP_KERNEL, "%pOFn.pfd", client->dev.of_node);
|
||||
if (!init.name) {
|
||||
ret = -ENOMEM;
|
||||
goto err_clk;
|
||||
}
|
||||
init.ops = &vc5_pfd_ops;
|
||||
init.flags = CLK_SET_RATE_PARENT;
|
||||
init.parent_names = parent_names;
|
||||
|
|
@ -1074,6 +1090,10 @@ static int vc5_probe(struct i2c_client *client)
|
|||
/* Register PLL */
|
||||
memset(&init, 0, sizeof(init));
|
||||
init.name = kasprintf(GFP_KERNEL, "%pOFn.pll", client->dev.of_node);
|
||||
if (!init.name) {
|
||||
ret = -ENOMEM;
|
||||
goto err_clk;
|
||||
}
|
||||
init.ops = &vc5_pll_ops;
|
||||
init.flags = CLK_SET_RATE_PARENT;
|
||||
init.parent_names = parent_names;
|
||||
|
|
@ -1093,6 +1113,10 @@ static int vc5_probe(struct i2c_client *client)
|
|||
memset(&init, 0, sizeof(init));
|
||||
init.name = kasprintf(GFP_KERNEL, "%pOFn.fod%d",
|
||||
client->dev.of_node, idx);
|
||||
if (!init.name) {
|
||||
ret = -ENOMEM;
|
||||
goto err_clk;
|
||||
}
|
||||
init.ops = &vc5_fod_ops;
|
||||
init.flags = CLK_SET_RATE_PARENT;
|
||||
init.parent_names = parent_names;
|
||||
|
|
@ -1111,6 +1135,10 @@ static int vc5_probe(struct i2c_client *client)
|
|||
memset(&init, 0, sizeof(init));
|
||||
init.name = kasprintf(GFP_KERNEL, "%pOFn.out0_sel_i2cb",
|
||||
client->dev.of_node);
|
||||
if (!init.name) {
|
||||
ret = -ENOMEM;
|
||||
goto err_clk;
|
||||
}
|
||||
init.ops = &vc5_clk_out_ops;
|
||||
init.flags = CLK_SET_RATE_PARENT;
|
||||
init.parent_names = parent_names;
|
||||
|
|
@ -1137,6 +1165,10 @@ static int vc5_probe(struct i2c_client *client)
|
|||
memset(&init, 0, sizeof(init));
|
||||
init.name = kasprintf(GFP_KERNEL, "%pOFn.out%d",
|
||||
client->dev.of_node, idx + 1);
|
||||
if (!init.name) {
|
||||
ret = -ENOMEM;
|
||||
goto err_clk;
|
||||
}
|
||||
init.ops = &vc5_clk_out_ops;
|
||||
init.flags = CLK_SET_RATE_PARENT;
|
||||
init.parent_names = parent_names;
|
||||
|
|
@ -1271,14 +1303,14 @@ static const struct vc5_chip_info idt_5p49v6975_info = {
|
|||
};
|
||||
|
||||
static const struct i2c_device_id vc5_id[] = {
|
||||
{ "5p49v5923", .driver_data = IDT_VC5_5P49V5923 },
|
||||
{ "5p49v5925", .driver_data = IDT_VC5_5P49V5925 },
|
||||
{ "5p49v5933", .driver_data = IDT_VC5_5P49V5933 },
|
||||
{ "5p49v5935", .driver_data = IDT_VC5_5P49V5935 },
|
||||
{ "5p49v60", .driver_data = IDT_VC6_5P49V60 },
|
||||
{ "5p49v6901", .driver_data = IDT_VC6_5P49V6901 },
|
||||
{ "5p49v6965", .driver_data = IDT_VC6_5P49V6965 },
|
||||
{ "5p49v6975", .driver_data = IDT_VC6_5P49V6975 },
|
||||
{ "5p49v5923", .driver_data = (kernel_ulong_t)&idt_5p49v5923_info },
|
||||
{ "5p49v5925", .driver_data = (kernel_ulong_t)&idt_5p49v5925_info },
|
||||
{ "5p49v5933", .driver_data = (kernel_ulong_t)&idt_5p49v5933_info },
|
||||
{ "5p49v5935", .driver_data = (kernel_ulong_t)&idt_5p49v5935_info },
|
||||
{ "5p49v60", .driver_data = (kernel_ulong_t)&idt_5p49v60_info },
|
||||
{ "5p49v6901", .driver_data = (kernel_ulong_t)&idt_5p49v6901_info },
|
||||
{ "5p49v6965", .driver_data = (kernel_ulong_t)&idt_5p49v6965_info },
|
||||
{ "5p49v6975", .driver_data = (kernel_ulong_t)&idt_5p49v6975_info },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(i2c, vc5_id);
|
||||
|
|
@ -1304,7 +1336,7 @@ static struct i2c_driver vc5_driver = {
|
|||
.pm = &vc5_pm_ops,
|
||||
.of_match_table = clk_vc5_of_match,
|
||||
},
|
||||
.probe_new = vc5_probe,
|
||||
.probe = vc5_probe,
|
||||
.remove = vc5_remove,
|
||||
.id_table = vc5_id,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -15,6 +15,7 @@
|
|||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/property.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/swab.h>
|
||||
|
||||
|
|
@ -1108,7 +1109,7 @@ static int vc7_probe(struct i2c_client *client)
|
|||
|
||||
i2c_set_clientdata(client, vc7);
|
||||
vc7->client = client;
|
||||
vc7->chip_info = of_device_get_match_data(&client->dev);
|
||||
vc7->chip_info = device_get_match_data(&client->dev);
|
||||
|
||||
vc7->pin_xin = devm_clk_get(&client->dev, "xin");
|
||||
if (PTR_ERR(vc7->pin_xin) == -EPROBE_DEFER) {
|
||||
|
|
@ -1282,7 +1283,7 @@ static const struct regmap_config vc7_regmap_config = {
|
|||
};
|
||||
|
||||
static const struct i2c_device_id vc7_i2c_id[] = {
|
||||
{ "rc21008a", VC7_RC21008A },
|
||||
{ "rc21008a", .driver_data = (kernel_ulong_t)&vc7_rc21008a_info },
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(i2c, vc7_i2c_id);
|
||||
|
|
@ -1298,7 +1299,7 @@ static struct i2c_driver vc7_i2c_driver = {
|
|||
.name = "vc7",
|
||||
.of_match_table = vc7_of_match,
|
||||
},
|
||||
.probe_new = vc7_probe,
|
||||
.probe = vc7_probe,
|
||||
.remove = vc7_remove,
|
||||
.id_table = vc7_i2c_id,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -329,6 +329,7 @@ static const struct clk_ops wm831x_clkout_ops = {
|
|||
.is_prepared = wm831x_clkout_is_prepared,
|
||||
.prepare = wm831x_clkout_prepare,
|
||||
.unprepare = wm831x_clkout_unprepare,
|
||||
.determine_rate = clk_hw_determine_rate_no_reparent,
|
||||
.get_parent = wm831x_clkout_get_parent,
|
||||
.set_parent = wm831x_clkout_set_parent,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -594,6 +594,47 @@ clk_core_forward_rate_req(struct clk_core *core,
|
|||
req->max_rate = old_req->max_rate;
|
||||
}
|
||||
|
||||
static int
|
||||
clk_core_determine_rate_no_reparent(struct clk_hw *hw,
|
||||
struct clk_rate_request *req)
|
||||
{
|
||||
struct clk_core *core = hw->core;
|
||||
struct clk_core *parent = core->parent;
|
||||
unsigned long best;
|
||||
int ret;
|
||||
|
||||
if (core->flags & CLK_SET_RATE_PARENT) {
|
||||
struct clk_rate_request parent_req;
|
||||
|
||||
if (!parent) {
|
||||
req->rate = 0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
clk_core_forward_rate_req(core, req, parent, &parent_req,
|
||||
req->rate);
|
||||
|
||||
trace_clk_rate_request_start(&parent_req);
|
||||
|
||||
ret = clk_core_round_rate_nolock(parent, &parent_req);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
trace_clk_rate_request_done(&parent_req);
|
||||
|
||||
best = parent_req.rate;
|
||||
} else if (parent) {
|
||||
best = clk_core_get_rate_nolock(parent);
|
||||
} else {
|
||||
best = clk_core_get_rate_nolock(core);
|
||||
}
|
||||
|
||||
req->best_parent_rate = best;
|
||||
req->rate = best;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int clk_mux_determine_rate_flags(struct clk_hw *hw,
|
||||
struct clk_rate_request *req,
|
||||
unsigned long flags)
|
||||
|
|
@ -603,35 +644,8 @@ int clk_mux_determine_rate_flags(struct clk_hw *hw,
|
|||
unsigned long best = 0;
|
||||
|
||||
/* if NO_REPARENT flag set, pass through to current parent */
|
||||
if (core->flags & CLK_SET_RATE_NO_REPARENT) {
|
||||
parent = core->parent;
|
||||
if (core->flags & CLK_SET_RATE_PARENT) {
|
||||
struct clk_rate_request parent_req;
|
||||
|
||||
if (!parent) {
|
||||
req->rate = 0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
clk_core_forward_rate_req(core, req, parent, &parent_req, req->rate);
|
||||
|
||||
trace_clk_rate_request_start(&parent_req);
|
||||
|
||||
ret = clk_core_round_rate_nolock(parent, &parent_req);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
trace_clk_rate_request_done(&parent_req);
|
||||
|
||||
best = parent_req.rate;
|
||||
} else if (parent) {
|
||||
best = clk_core_get_rate_nolock(parent);
|
||||
} else {
|
||||
best = clk_core_get_rate_nolock(core);
|
||||
}
|
||||
|
||||
goto out;
|
||||
}
|
||||
if (core->flags & CLK_SET_RATE_NO_REPARENT)
|
||||
return clk_core_determine_rate_no_reparent(hw, req);
|
||||
|
||||
/* find the parent that can provide the fastest rate <= rate */
|
||||
num_parents = core->num_parents;
|
||||
|
|
@ -670,9 +684,7 @@ int clk_mux_determine_rate_flags(struct clk_hw *hw,
|
|||
if (!best_parent)
|
||||
return -EINVAL;
|
||||
|
||||
out:
|
||||
if (best_parent)
|
||||
req->best_parent_hw = best_parent->hw;
|
||||
req->best_parent_hw = best_parent->hw;
|
||||
req->best_parent_rate = best;
|
||||
req->rate = best;
|
||||
|
||||
|
|
@ -772,6 +784,25 @@ int __clk_mux_determine_rate_closest(struct clk_hw *hw,
|
|||
}
|
||||
EXPORT_SYMBOL_GPL(__clk_mux_determine_rate_closest);
|
||||
|
||||
/*
|
||||
* clk_hw_determine_rate_no_reparent - clk_ops::determine_rate implementation for a clk that doesn't reparent
|
||||
* @hw: mux type clk to determine rate on
|
||||
* @req: rate request, also used to return preferred frequency
|
||||
*
|
||||
* Helper for finding best parent rate to provide a given frequency.
|
||||
* This can be used directly as a determine_rate callback (e.g. for a
|
||||
* mux), or from a more complex clock that may combine a mux with other
|
||||
* operations.
|
||||
*
|
||||
* Returns: 0 on success, -EERROR value on error
|
||||
*/
|
||||
int clk_hw_determine_rate_no_reparent(struct clk_hw *hw,
|
||||
struct clk_rate_request *req)
|
||||
{
|
||||
return clk_core_determine_rate_no_reparent(hw, req);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(clk_hw_determine_rate_no_reparent);
|
||||
|
||||
/*** clk api ***/
|
||||
|
||||
static void clk_core_rate_unprotect(struct clk_core *core)
|
||||
|
|
@ -1549,6 +1580,7 @@ void clk_hw_forward_rate_request(const struct clk_hw *hw,
|
|||
parent->core, req,
|
||||
parent_rate);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(clk_hw_forward_rate_request);
|
||||
|
||||
static bool clk_core_can_round(struct clk_core * const core)
|
||||
{
|
||||
|
|
@ -3745,6 +3777,13 @@ static int __clk_core_init(struct clk_core *core)
|
|||
goto out;
|
||||
}
|
||||
|
||||
if (core->ops->set_parent && !core->ops->determine_rate) {
|
||||
pr_err("%s: %s must implement .set_parent & .determine_rate\n",
|
||||
__func__, core->name);
|
||||
ret = -EINVAL;
|
||||
goto out;
|
||||
}
|
||||
|
||||
if (core->num_parents > 1 && !core->ops->get_parent) {
|
||||
pr_err("%s: %s must implement .get_parent as it has multi parents\n",
|
||||
__func__, core->name);
|
||||
|
|
@ -4301,11 +4340,18 @@ static int clk_nodrv_set_parent(struct clk_hw *hw, u8 index)
|
|||
return -ENXIO;
|
||||
}
|
||||
|
||||
static int clk_nodrv_determine_rate(struct clk_hw *hw,
|
||||
struct clk_rate_request *req)
|
||||
{
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
static const struct clk_ops clk_nodrv_ops = {
|
||||
.enable = clk_nodrv_prepare_enable,
|
||||
.disable = clk_nodrv_disable_unprepare,
|
||||
.prepare = clk_nodrv_prepare_enable,
|
||||
.unprepare = clk_nodrv_disable_unprepare,
|
||||
.determine_rate = clk_nodrv_determine_rate,
|
||||
.set_rate = clk_nodrv_set_rate,
|
||||
.set_parent = clk_nodrv_set_parent,
|
||||
};
|
||||
|
|
@ -4695,6 +4741,7 @@ int devm_clk_notifier_register(struct device *dev, struct clk *clk,
|
|||
if (!ret) {
|
||||
devres->clk = clk;
|
||||
devres->nb = nb;
|
||||
devres_add(dev, devres);
|
||||
} else {
|
||||
devres_free(devres);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -104,6 +104,23 @@ static const struct clk_ops clk_dummy_minimize_rate_ops = {
|
|||
};
|
||||
|
||||
static const struct clk_ops clk_dummy_single_parent_ops = {
|
||||
/*
|
||||
* FIXME: Even though we should probably be able to use
|
||||
* __clk_mux_determine_rate() here, if we use it and call
|
||||
* clk_round_rate() or clk_set_rate() with a rate lower than
|
||||
* what all the parents can provide, it will return -EINVAL.
|
||||
*
|
||||
* This is due to the fact that it has the undocumented
|
||||
* behaviour to always pick up the closest rate higher than the
|
||||
* requested rate. If we get something lower, it thus considers
|
||||
* that it's not acceptable and will return an error.
|
||||
*
|
||||
* It's somewhat inconsistent and creates a weird threshold
|
||||
* between rates above the parent rate which would be rounded to
|
||||
* what the parent can provide, but rates below will simply
|
||||
* return an error.
|
||||
*/
|
||||
.determine_rate = __clk_mux_determine_rate_closest,
|
||||
.set_parent = clk_dummy_single_set_parent,
|
||||
.get_parent = clk_dummy_single_get_parent,
|
||||
};
|
||||
|
|
@ -141,6 +158,12 @@ static const struct clk_ops clk_multiple_parents_mux_ops = {
|
|||
.determine_rate = __clk_mux_determine_rate_closest,
|
||||
};
|
||||
|
||||
static const struct clk_ops clk_multiple_parents_no_reparent_mux_ops = {
|
||||
.determine_rate = clk_hw_determine_rate_no_reparent,
|
||||
.get_parent = clk_multiple_parents_mux_get_parent,
|
||||
.set_parent = clk_multiple_parents_mux_set_parent,
|
||||
};
|
||||
|
||||
static int clk_test_init_with_ops(struct kunit *test, const struct clk_ops *ops)
|
||||
{
|
||||
struct clk_dummy_context *ctx;
|
||||
|
|
@ -266,7 +289,8 @@ static void clk_test_round_set_get_rate(struct kunit *test)
|
|||
struct clk_dummy_context *ctx = test->priv;
|
||||
struct clk_hw *hw = &ctx->hw;
|
||||
struct clk *clk = clk_hw_get_clk(hw, NULL);
|
||||
unsigned long rounded_rate, set_rate;
|
||||
unsigned long set_rate;
|
||||
long rounded_rate;
|
||||
|
||||
rounded_rate = clk_round_rate(clk, DUMMY_CLOCK_RATE_1);
|
||||
KUNIT_ASSERT_GT(test, rounded_rate, 0);
|
||||
|
|
@ -851,7 +875,7 @@ clk_test_orphan_transparent_multiple_parent_mux_set_range_round_rate(struct kuni
|
|||
struct clk_multiple_parent_ctx *ctx = test->priv;
|
||||
struct clk_hw *hw = &ctx->hw;
|
||||
struct clk *clk = clk_hw_get_clk(hw, NULL);
|
||||
unsigned long rate;
|
||||
long rate;
|
||||
int ret;
|
||||
|
||||
ret = clk_set_rate_range(clk, DUMMY_CLOCK_RATE_1, DUMMY_CLOCK_RATE_2);
|
||||
|
|
@ -1090,7 +1114,7 @@ clk_test_single_parent_mux_set_range_round_rate_parent_only(struct kunit *test)
|
|||
struct clk_hw *hw = &ctx->hw;
|
||||
struct clk *clk = clk_hw_get_clk(hw, NULL);
|
||||
struct clk *parent;
|
||||
unsigned long rate;
|
||||
long rate;
|
||||
int ret;
|
||||
|
||||
parent = clk_get_parent(clk);
|
||||
|
|
@ -1120,7 +1144,7 @@ clk_test_single_parent_mux_set_range_round_rate_child_smaller(struct kunit *test
|
|||
struct clk_hw *hw = &ctx->hw;
|
||||
struct clk *clk = clk_hw_get_clk(hw, NULL);
|
||||
struct clk *parent;
|
||||
unsigned long rate;
|
||||
long rate;
|
||||
int ret;
|
||||
|
||||
parent = clk_get_parent(clk);
|
||||
|
|
@ -1158,7 +1182,7 @@ clk_test_single_parent_mux_set_range_round_rate_parent_smaller(struct kunit *tes
|
|||
struct clk_hw *hw = &ctx->hw;
|
||||
struct clk *clk = clk_hw_get_clk(hw, NULL);
|
||||
struct clk *parent;
|
||||
unsigned long rate;
|
||||
long rate;
|
||||
int ret;
|
||||
|
||||
parent = clk_get_parent(clk);
|
||||
|
|
@ -2394,10 +2418,156 @@ static struct kunit_suite clk_mux_notifier_test_suite = {
|
|||
.test_cases = clk_mux_notifier_test_cases,
|
||||
};
|
||||
|
||||
static int
|
||||
clk_mux_no_reparent_test_init(struct kunit *test)
|
||||
{
|
||||
struct clk_multiple_parent_ctx *ctx;
|
||||
const char *parents[2] = { "parent-0", "parent-1"};
|
||||
int ret;
|
||||
|
||||
ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL);
|
||||
if (!ctx)
|
||||
return -ENOMEM;
|
||||
test->priv = ctx;
|
||||
|
||||
ctx->parents_ctx[0].hw.init = CLK_HW_INIT_NO_PARENT("parent-0",
|
||||
&clk_dummy_rate_ops,
|
||||
0);
|
||||
ctx->parents_ctx[0].rate = DUMMY_CLOCK_RATE_1;
|
||||
ret = clk_hw_register(NULL, &ctx->parents_ctx[0].hw);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ctx->parents_ctx[1].hw.init = CLK_HW_INIT_NO_PARENT("parent-1",
|
||||
&clk_dummy_rate_ops,
|
||||
0);
|
||||
ctx->parents_ctx[1].rate = DUMMY_CLOCK_RATE_2;
|
||||
ret = clk_hw_register(NULL, &ctx->parents_ctx[1].hw);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ctx->current_parent = 0;
|
||||
ctx->hw.init = CLK_HW_INIT_PARENTS("test-mux", parents,
|
||||
&clk_multiple_parents_no_reparent_mux_ops,
|
||||
0);
|
||||
ret = clk_hw_register(NULL, &ctx->hw);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void
|
||||
clk_mux_no_reparent_test_exit(struct kunit *test)
|
||||
{
|
||||
struct clk_multiple_parent_ctx *ctx = test->priv;
|
||||
|
||||
clk_hw_unregister(&ctx->hw);
|
||||
clk_hw_unregister(&ctx->parents_ctx[0].hw);
|
||||
clk_hw_unregister(&ctx->parents_ctx[1].hw);
|
||||
}
|
||||
|
||||
/*
|
||||
* Test that if the we have a mux that cannot change parent and we call
|
||||
* clk_round_rate() on it with a rate that should cause it to change
|
||||
* parent, it won't.
|
||||
*/
|
||||
static void clk_mux_no_reparent_round_rate(struct kunit *test)
|
||||
{
|
||||
struct clk_multiple_parent_ctx *ctx = test->priv;
|
||||
struct clk_hw *hw = &ctx->hw;
|
||||
struct clk *clk = clk_hw_get_clk(hw, NULL);
|
||||
struct clk *other_parent, *parent;
|
||||
unsigned long other_parent_rate;
|
||||
unsigned long parent_rate;
|
||||
long rounded_rate;
|
||||
|
||||
parent = clk_get_parent(clk);
|
||||
KUNIT_ASSERT_PTR_NE(test, parent, NULL);
|
||||
|
||||
parent_rate = clk_get_rate(parent);
|
||||
KUNIT_ASSERT_GT(test, parent_rate, 0);
|
||||
|
||||
other_parent = clk_hw_get_clk(&ctx->parents_ctx[1].hw, NULL);
|
||||
KUNIT_ASSERT_NOT_ERR_OR_NULL(test, other_parent);
|
||||
KUNIT_ASSERT_FALSE(test, clk_is_match(parent, other_parent));
|
||||
|
||||
other_parent_rate = clk_get_rate(other_parent);
|
||||
KUNIT_ASSERT_GT(test, other_parent_rate, 0);
|
||||
clk_put(other_parent);
|
||||
|
||||
rounded_rate = clk_round_rate(clk, other_parent_rate);
|
||||
KUNIT_ASSERT_GT(test, rounded_rate, 0);
|
||||
KUNIT_EXPECT_EQ(test, rounded_rate, parent_rate);
|
||||
|
||||
clk_put(clk);
|
||||
}
|
||||
|
||||
/*
|
||||
* Test that if the we have a mux that cannot change parent and we call
|
||||
* clk_set_rate() on it with a rate that should cause it to change
|
||||
* parent, it won't.
|
||||
*/
|
||||
static void clk_mux_no_reparent_set_rate(struct kunit *test)
|
||||
{
|
||||
struct clk_multiple_parent_ctx *ctx = test->priv;
|
||||
struct clk_hw *hw = &ctx->hw;
|
||||
struct clk *clk = clk_hw_get_clk(hw, NULL);
|
||||
struct clk *other_parent, *parent;
|
||||
unsigned long other_parent_rate;
|
||||
unsigned long parent_rate;
|
||||
unsigned long rate;
|
||||
int ret;
|
||||
|
||||
parent = clk_get_parent(clk);
|
||||
KUNIT_ASSERT_PTR_NE(test, parent, NULL);
|
||||
|
||||
parent_rate = clk_get_rate(parent);
|
||||
KUNIT_ASSERT_GT(test, parent_rate, 0);
|
||||
|
||||
other_parent = clk_hw_get_clk(&ctx->parents_ctx[1].hw, NULL);
|
||||
KUNIT_ASSERT_NOT_ERR_OR_NULL(test, other_parent);
|
||||
KUNIT_ASSERT_FALSE(test, clk_is_match(parent, other_parent));
|
||||
|
||||
other_parent_rate = clk_get_rate(other_parent);
|
||||
KUNIT_ASSERT_GT(test, other_parent_rate, 0);
|
||||
clk_put(other_parent);
|
||||
|
||||
ret = clk_set_rate(clk, other_parent_rate);
|
||||
KUNIT_ASSERT_EQ(test, ret, 0);
|
||||
|
||||
rate = clk_get_rate(clk);
|
||||
KUNIT_ASSERT_GT(test, rate, 0);
|
||||
KUNIT_EXPECT_EQ(test, rate, parent_rate);
|
||||
|
||||
clk_put(clk);
|
||||
}
|
||||
|
||||
static struct kunit_case clk_mux_no_reparent_test_cases[] = {
|
||||
KUNIT_CASE(clk_mux_no_reparent_round_rate),
|
||||
KUNIT_CASE(clk_mux_no_reparent_set_rate),
|
||||
{}
|
||||
};
|
||||
|
||||
/*
|
||||
* Test suite for a clock mux that isn't allowed to change parent, using
|
||||
* the clk_hw_determine_rate_no_reparent() helper.
|
||||
*
|
||||
* These tests exercise that helper, and the proper selection of
|
||||
* rates and parents.
|
||||
*/
|
||||
static struct kunit_suite clk_mux_no_reparent_test_suite = {
|
||||
.name = "clk-mux-no-reparent",
|
||||
.init = clk_mux_no_reparent_test_init,
|
||||
.exit = clk_mux_no_reparent_test_exit,
|
||||
.test_cases = clk_mux_no_reparent_test_cases,
|
||||
};
|
||||
|
||||
kunit_test_suites(
|
||||
&clk_leaf_mux_set_rate_parent_test_suite,
|
||||
&clk_test_suite,
|
||||
&clk_multiple_parents_mux_test_suite,
|
||||
&clk_mux_no_reparent_test_suite,
|
||||
&clk_mux_notifier_test_suite,
|
||||
&clk_orphan_transparent_multiple_parent_mux_test_suite,
|
||||
&clk_orphan_transparent_single_parent_test_suite,
|
||||
|
|
|
|||
|
|
@ -229,6 +229,7 @@ static u8 da8xx_cfgchip_mux_clk_get_parent(struct clk_hw *hw)
|
|||
}
|
||||
|
||||
static const struct clk_ops da8xx_cfgchip_mux_clk_ops = {
|
||||
.determine_rate = clk_hw_determine_rate_no_reparent,
|
||||
.set_parent = da8xx_cfgchip_mux_clk_set_parent,
|
||||
.get_parent = da8xx_cfgchip_mux_clk_get_parent,
|
||||
};
|
||||
|
|
@ -461,10 +462,12 @@ static unsigned long da8xx_usb0_clk48_recalc_rate(struct clk_hw *hw,
|
|||
return 48000000;
|
||||
}
|
||||
|
||||
static long da8xx_usb0_clk48_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *parent_rate)
|
||||
static int da8xx_usb0_clk48_determine_rate(struct clk_hw *hw,
|
||||
struct clk_rate_request *req)
|
||||
{
|
||||
return 48000000;
|
||||
req->rate = 48000000;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int da8xx_usb0_clk48_set_parent(struct clk_hw *hw, u8 index)
|
||||
|
|
@ -493,7 +496,7 @@ static const struct clk_ops da8xx_usb0_clk48_ops = {
|
|||
.disable = da8xx_usb0_clk48_disable,
|
||||
.is_enabled = da8xx_usb0_clk48_is_enabled,
|
||||
.recalc_rate = da8xx_usb0_clk48_recalc_rate,
|
||||
.round_rate = da8xx_usb0_clk48_round_rate,
|
||||
.determine_rate = da8xx_usb0_clk48_determine_rate,
|
||||
.set_parent = da8xx_usb0_clk48_set_parent,
|
||||
.get_parent = da8xx_usb0_clk48_get_parent,
|
||||
};
|
||||
|
|
@ -564,6 +567,7 @@ static u8 da8xx_usb1_clk48_get_parent(struct clk_hw *hw)
|
|||
}
|
||||
|
||||
static const struct clk_ops da8xx_usb1_clk48_ops = {
|
||||
.determine_rate = clk_hw_determine_rate_no_reparent,
|
||||
.set_parent = da8xx_usb1_clk48_set_parent,
|
||||
.get_parent = da8xx_usb1_clk48_get_parent,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -148,6 +148,7 @@ static int clk_busy_mux_set_parent(struct clk_hw *hw, u8 index)
|
|||
}
|
||||
|
||||
static const struct clk_ops clk_busy_mux_ops = {
|
||||
.determine_rate = clk_hw_determine_rate_no_reparent,
|
||||
.get_parent = clk_busy_mux_get_parent,
|
||||
.set_parent = clk_busy_mux_set_parent,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -119,10 +119,41 @@ static int imx8m_clk_composite_divider_set_rate(struct clk_hw *hw,
|
|||
return ret;
|
||||
}
|
||||
|
||||
static int imx8m_divider_determine_rate(struct clk_hw *hw,
|
||||
struct clk_rate_request *req)
|
||||
{
|
||||
struct clk_divider *divider = to_clk_divider(hw);
|
||||
int prediv_value;
|
||||
int div_value;
|
||||
|
||||
/* if read only, just return current value */
|
||||
if (divider->flags & CLK_DIVIDER_READ_ONLY) {
|
||||
u32 val;
|
||||
|
||||
val = readl(divider->reg);
|
||||
prediv_value = val >> divider->shift;
|
||||
prediv_value &= clk_div_mask(divider->width);
|
||||
prediv_value++;
|
||||
|
||||
div_value = val >> PCG_DIV_SHIFT;
|
||||
div_value &= clk_div_mask(PCG_DIV_WIDTH);
|
||||
div_value++;
|
||||
|
||||
return divider_ro_determine_rate(hw, req, divider->table,
|
||||
PCG_PREDIV_WIDTH + PCG_DIV_WIDTH,
|
||||
divider->flags, prediv_value * div_value);
|
||||
}
|
||||
|
||||
return divider_determine_rate(hw, req, divider->table,
|
||||
PCG_PREDIV_WIDTH + PCG_DIV_WIDTH,
|
||||
divider->flags);
|
||||
}
|
||||
|
||||
static const struct clk_ops imx8m_clk_composite_divider_ops = {
|
||||
.recalc_rate = imx8m_clk_composite_divider_recalc_rate,
|
||||
.round_rate = imx8m_clk_composite_divider_round_rate,
|
||||
.set_rate = imx8m_clk_composite_divider_set_rate,
|
||||
.determine_rate = imx8m_divider_determine_rate,
|
||||
};
|
||||
|
||||
static u8 imx8m_clk_composite_mux_get_parent(struct clk_hw *hw)
|
||||
|
|
|
|||
|
|
@ -60,6 +60,7 @@ static int clk_fixup_mux_set_parent(struct clk_hw *hw, u8 index)
|
|||
}
|
||||
|
||||
static const struct clk_ops clk_fixup_mux_ops = {
|
||||
.determine_rate = clk_hw_determine_rate_no_reparent,
|
||||
.get_parent = clk_fixup_mux_get_parent,
|
||||
.set_parent = clk_fixup_mux_set_parent,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -302,10 +302,10 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
|
|||
hws[IMX6SX_CLK_CKO2_SEL] = imx_clk_hw_mux("cko2_sel", base + 0x60, 16, 5, cko2_sels, ARRAY_SIZE(cko2_sels));
|
||||
hws[IMX6SX_CLK_CKO] = imx_clk_hw_mux("cko", base + 0x60, 8, 1, cko_sels, ARRAY_SIZE(cko_sels));
|
||||
|
||||
hws[IMX6SX_CLK_LDB_DI1_DIV_SEL] = imx_clk_hw_mux_flags("ldb_di1_div_sel", base + 0x20, 11, 1, ldb_di1_div_sels, ARRAY_SIZE(ldb_di1_div_sels), CLK_SET_RATE_PARENT);
|
||||
hws[IMX6SX_CLK_LDB_DI0_DIV_SEL] = imx_clk_hw_mux_flags("ldb_di0_div_sel", base + 0x20, 10, 1, ldb_di0_div_sels, ARRAY_SIZE(ldb_di0_div_sels), CLK_SET_RATE_PARENT);
|
||||
hws[IMX6SX_CLK_LDB_DI1_SEL] = imx_clk_hw_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di1_sels, ARRAY_SIZE(ldb_di1_sels), CLK_SET_RATE_PARENT);
|
||||
hws[IMX6SX_CLK_LDB_DI0_SEL] = imx_clk_hw_mux_flags("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di0_sels, ARRAY_SIZE(ldb_di0_sels), CLK_SET_RATE_PARENT);
|
||||
hws[IMX6SX_CLK_LDB_DI1_DIV_SEL] = imx_clk_hw_mux("ldb_di1_div_sel", base + 0x20, 11, 1, ldb_di1_div_sels, ARRAY_SIZE(ldb_di1_div_sels));
|
||||
hws[IMX6SX_CLK_LDB_DI0_DIV_SEL] = imx_clk_hw_mux("ldb_di0_div_sel", base + 0x20, 10, 1, ldb_di0_div_sels, ARRAY_SIZE(ldb_di0_div_sels));
|
||||
hws[IMX6SX_CLK_LDB_DI1_SEL] = imx_clk_hw_mux("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di1_sels, ARRAY_SIZE(ldb_di1_sels));
|
||||
hws[IMX6SX_CLK_LDB_DI0_SEL] = imx_clk_hw_mux("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di0_sels, ARRAY_SIZE(ldb_di0_sels));
|
||||
hws[IMX6SX_CLK_LCDIF1_PRE_SEL] = imx_clk_hw_mux_flags("lcdif1_pre_sel", base + 0x38, 15, 3, lcdif1_pre_sels, ARRAY_SIZE(lcdif1_pre_sels), CLK_SET_RATE_PARENT);
|
||||
hws[IMX6SX_CLK_LCDIF1_SEL] = imx_clk_hw_mux_flags("lcdif1_sel", base + 0x38, 9, 3, lcdif1_sels, ARRAY_SIZE(lcdif1_sels), CLK_SET_RATE_PARENT);
|
||||
|
||||
|
|
|
|||
|
|
@ -544,6 +544,8 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
|
|||
|
||||
clk_set_parent(hws[IMX6UL_CLK_ENET1_REF_SEL]->clk, hws[IMX6UL_CLK_ENET_REF]->clk);
|
||||
clk_set_parent(hws[IMX6UL_CLK_ENET2_REF_SEL]->clk, hws[IMX6UL_CLK_ENET2_REF]->clk);
|
||||
|
||||
imx_register_uart_clocks();
|
||||
}
|
||||
|
||||
CLK_OF_DECLARE(imx6ul, "fsl,imx6ul-ccm", imx6ul_clocks_init);
|
||||
|
|
|
|||
|
|
@ -323,7 +323,7 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
|
|||
void __iomem *base;
|
||||
int ret;
|
||||
|
||||
clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,
|
||||
clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws,
|
||||
IMX8MN_CLK_END), GFP_KERNEL);
|
||||
if (WARN_ON(!clk_hw_data))
|
||||
return -ENOMEM;
|
||||
|
|
@ -340,10 +340,10 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
|
|||
hws[IMX8MN_CLK_EXT4] = imx_get_clk_hw_by_name(np, "clk_ext4");
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,imx8mn-anatop");
|
||||
base = of_iomap(np, 0);
|
||||
base = devm_of_iomap(dev, np, 0, NULL);
|
||||
of_node_put(np);
|
||||
if (WARN_ON(!base)) {
|
||||
ret = -ENOMEM;
|
||||
if (WARN_ON(IS_ERR(base))) {
|
||||
ret = PTR_ERR(base);
|
||||
goto unregister_hws;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -414,25 +414,22 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
|
|||
struct device *dev = &pdev->dev;
|
||||
struct device_node *np;
|
||||
void __iomem *anatop_base, *ccm_base;
|
||||
int err;
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,imx8mp-anatop");
|
||||
anatop_base = of_iomap(np, 0);
|
||||
anatop_base = devm_of_iomap(dev, np, 0, NULL);
|
||||
of_node_put(np);
|
||||
if (WARN_ON(!anatop_base))
|
||||
return -ENOMEM;
|
||||
if (WARN_ON(IS_ERR(anatop_base)))
|
||||
return PTR_ERR(anatop_base);
|
||||
|
||||
np = dev->of_node;
|
||||
ccm_base = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (WARN_ON(IS_ERR(ccm_base))) {
|
||||
iounmap(anatop_base);
|
||||
if (WARN_ON(IS_ERR(ccm_base)))
|
||||
return PTR_ERR(ccm_base);
|
||||
}
|
||||
|
||||
clk_hw_data = kzalloc(struct_size(clk_hw_data, hws, IMX8MP_CLK_END), GFP_KERNEL);
|
||||
if (WARN_ON(!clk_hw_data)) {
|
||||
iounmap(anatop_base);
|
||||
clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws, IMX8MP_CLK_END), GFP_KERNEL);
|
||||
if (WARN_ON(!clk_hw_data))
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
clk_hw_data->num = IMX8MP_CLK_END;
|
||||
hws = clk_hw_data->hws;
|
||||
|
|
@ -722,7 +719,12 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
|
|||
|
||||
imx_check_clk_hws(hws, IMX8MP_CLK_END);
|
||||
|
||||
of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);
|
||||
err = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);
|
||||
if (err < 0) {
|
||||
dev_err(dev, "failed to register hws for i.MX8MP\n");
|
||||
imx_unregister_hw_clocks(hws, IMX8MP_CLK_END);
|
||||
return err;
|
||||
}
|
||||
|
||||
imx_register_uart_clocks();
|
||||
|
||||
|
|
|
|||
|
|
@ -264,7 +264,7 @@ static int imx93_clocks_probe(struct platform_device *pdev)
|
|||
void __iomem *base, *anatop_base;
|
||||
int i, ret;
|
||||
|
||||
clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,
|
||||
clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws,
|
||||
IMX93_CLK_END), GFP_KERNEL);
|
||||
if (!clk_hw_data)
|
||||
return -ENOMEM;
|
||||
|
|
@ -288,10 +288,12 @@ static int imx93_clocks_probe(struct platform_device *pdev)
|
|||
"sys_pll_pfd2", 1, 2);
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,imx93-anatop");
|
||||
anatop_base = of_iomap(np, 0);
|
||||
anatop_base = devm_of_iomap(dev, np, 0, NULL);
|
||||
of_node_put(np);
|
||||
if (WARN_ON(!anatop_base))
|
||||
return -ENOMEM;
|
||||
if (WARN_ON(IS_ERR(anatop_base))) {
|
||||
ret = PTR_ERR(base);
|
||||
goto unregister_hws;
|
||||
}
|
||||
|
||||
clks[IMX93_CLK_ARM_PLL] = imx_clk_fracn_gppll_integer("arm_pll", "osc_24m",
|
||||
anatop_base + 0x1000,
|
||||
|
|
@ -304,8 +306,8 @@ static int imx93_clocks_probe(struct platform_device *pdev)
|
|||
np = dev->of_node;
|
||||
base = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (WARN_ON(IS_ERR(base))) {
|
||||
iounmap(anatop_base);
|
||||
return PTR_ERR(base);
|
||||
ret = PTR_ERR(base);
|
||||
goto unregister_hws;
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(root_array); i++) {
|
||||
|
|
@ -345,7 +347,6 @@ static int imx93_clocks_probe(struct platform_device *pdev)
|
|||
|
||||
unregister_hws:
|
||||
imx_unregister_hw_clocks(clks, IMX93_CLK_END);
|
||||
iounmap(anatop_base);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -42,7 +42,7 @@ static int imxrt1050_clocks_probe(struct platform_device *pdev)
|
|||
struct device_node *anp;
|
||||
int ret;
|
||||
|
||||
clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,
|
||||
clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws,
|
||||
IMXRT1050_CLK_END), GFP_KERNEL);
|
||||
if (WARN_ON(!clk_hw_data))
|
||||
return -ENOMEM;
|
||||
|
|
@ -53,10 +53,12 @@ static int imxrt1050_clocks_probe(struct platform_device *pdev)
|
|||
hws[IMXRT1050_CLK_OSC] = imx_get_clk_hw_by_name(np, "osc");
|
||||
|
||||
anp = of_find_compatible_node(NULL, NULL, "fsl,imxrt-anatop");
|
||||
pll_base = of_iomap(anp, 0);
|
||||
pll_base = devm_of_iomap(dev, anp, 0, NULL);
|
||||
of_node_put(anp);
|
||||
if (WARN_ON(!pll_base))
|
||||
return -ENOMEM;
|
||||
if (WARN_ON(IS_ERR(pll_base))) {
|
||||
ret = PTR_ERR(pll_base);
|
||||
goto unregister_hws;
|
||||
}
|
||||
|
||||
/* Anatop clocks */
|
||||
hws[IMXRT1050_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0UL);
|
||||
|
|
@ -104,8 +106,10 @@ static int imxrt1050_clocks_probe(struct platform_device *pdev)
|
|||
|
||||
/* CCM clocks */
|
||||
ccm_base = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (WARN_ON(IS_ERR(ccm_base)))
|
||||
return PTR_ERR(ccm_base);
|
||||
if (WARN_ON(IS_ERR(ccm_base))) {
|
||||
ret = PTR_ERR(ccm_base);
|
||||
goto unregister_hws;
|
||||
}
|
||||
|
||||
hws[IMXRT1050_CLK_ARM_PODF] = imx_clk_hw_divider("arm_podf", "pll1_arm", ccm_base + 0x10, 0, 3);
|
||||
hws[IMXRT1050_CLK_PRE_PERIPH_SEL] = imx_clk_hw_mux("pre_periph_sel", ccm_base + 0x18, 18, 2,
|
||||
|
|
@ -149,8 +153,12 @@ static int imxrt1050_clocks_probe(struct platform_device *pdev)
|
|||
ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "Failed to register clks for i.MXRT1050.\n");
|
||||
imx_unregister_hw_clocks(hws, IMXRT1050_CLK_END);
|
||||
goto unregister_hws;
|
||||
}
|
||||
return 0;
|
||||
|
||||
unregister_hws:
|
||||
imx_unregister_hw_clocks(hws, IMXRT1050_CLK_END);
|
||||
return ret;
|
||||
}
|
||||
static const struct of_device_id imxrt1050_clk_of_match[] = {
|
||||
|
|
|
|||
|
|
@ -250,6 +250,23 @@ static unsigned long clk_scu_recalc_rate(struct clk_hw *hw,
|
|||
return le32_to_cpu(msg.data.resp.rate);
|
||||
}
|
||||
|
||||
/*
|
||||
* clk_scu_determine_rate - Returns the closest rate for a SCU clock
|
||||
* @hw: clock to round rate for
|
||||
* @req: clock rate request
|
||||
*
|
||||
* Returns 0 on success, a negative error on failure
|
||||
*/
|
||||
static int clk_scu_determine_rate(struct clk_hw *hw,
|
||||
struct clk_rate_request *req)
|
||||
{
|
||||
/*
|
||||
* Assume we support all the requested rate and let the SCU firmware
|
||||
* to handle the left work
|
||||
*/
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* clk_scu_round_rate - Round clock rate for a SCU clock
|
||||
* @hw: clock to round rate for
|
||||
|
|
@ -425,7 +442,7 @@ static void clk_scu_unprepare(struct clk_hw *hw)
|
|||
|
||||
static const struct clk_ops clk_scu_ops = {
|
||||
.recalc_rate = clk_scu_recalc_rate,
|
||||
.round_rate = clk_scu_round_rate,
|
||||
.determine_rate = clk_scu_determine_rate,
|
||||
.set_rate = clk_scu_set_rate,
|
||||
.get_parent = clk_scu_get_parent,
|
||||
.set_parent = clk_scu_set_parent,
|
||||
|
|
@ -707,11 +724,11 @@ struct clk_hw *imx_clk_scu_alloc_dev(const char *name,
|
|||
|
||||
void imx_clk_scu_unregister(void)
|
||||
{
|
||||
struct imx_scu_clk_node *clk;
|
||||
struct imx_scu_clk_node *clk, *n;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < IMX_SC_R_LAST; i++) {
|
||||
list_for_each_entry(clk, &imx_scu_clks[i], node) {
|
||||
list_for_each_entry_safe(clk, n, &imx_scu_clks[i], node) {
|
||||
clk_hw_unregister(clk->hw);
|
||||
kfree(clk);
|
||||
}
|
||||
|
|
@ -785,6 +802,7 @@ static int clk_gpr_mux_scu_set_parent(struct clk_hw *hw, u8 index)
|
|||
}
|
||||
|
||||
static const struct clk_ops clk_gpr_mux_scu_ops = {
|
||||
.determine_rate = clk_hw_determine_rate_no_reparent,
|
||||
.get_parent = clk_gpr_mux_scu_get_parent,
|
||||
.set_parent = clk_gpr_mux_scu_set_parent,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -20,14 +20,6 @@ EXPORT_SYMBOL_GPL(imx_ccm_lock);
|
|||
bool mcore_booted;
|
||||
EXPORT_SYMBOL_GPL(mcore_booted);
|
||||
|
||||
void imx_unregister_clocks(struct clk *clks[], unsigned int count)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < count; i++)
|
||||
clk_unregister(clks[i]);
|
||||
}
|
||||
|
||||
void imx_unregister_hw_clocks(struct clk_hw *hws[], unsigned int count)
|
||||
{
|
||||
unsigned int i;
|
||||
|
|
|
|||
|
|
@ -19,7 +19,6 @@ static inline void imx_register_uart_clocks(void)
|
|||
}
|
||||
#endif
|
||||
void imx_mmdc_mask_handshake(void __iomem *ccm_base, unsigned int chn);
|
||||
void imx_unregister_clocks(struct clk *clks[], unsigned int count);
|
||||
void imx_unregister_hw_clocks(struct clk_hw *hws[], unsigned int count);
|
||||
|
||||
extern void imx_cscmr1_fixup(u32 *val);
|
||||
|
|
|
|||
|
|
@ -491,22 +491,23 @@ ingenic_clk_calc_div(struct clk_hw *hw,
|
|||
return div;
|
||||
}
|
||||
|
||||
static long
|
||||
ingenic_clk_round_rate(struct clk_hw *hw, unsigned long req_rate,
|
||||
unsigned long *parent_rate)
|
||||
static int ingenic_clk_determine_rate(struct clk_hw *hw,
|
||||
struct clk_rate_request *req)
|
||||
{
|
||||
struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw);
|
||||
const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);
|
||||
unsigned int div = 1;
|
||||
|
||||
if (clk_info->type & CGU_CLK_DIV)
|
||||
div = ingenic_clk_calc_div(hw, clk_info, *parent_rate, req_rate);
|
||||
div = ingenic_clk_calc_div(hw, clk_info, req->best_parent_rate,
|
||||
req->rate);
|
||||
else if (clk_info->type & CGU_CLK_FIXDIV)
|
||||
div = clk_info->fixdiv.div;
|
||||
else if (clk_hw_can_set_rate_parent(hw))
|
||||
*parent_rate = req_rate;
|
||||
req->best_parent_rate = req->rate;
|
||||
|
||||
return DIV_ROUND_UP(*parent_rate, div);
|
||||
req->rate = DIV_ROUND_UP(req->best_parent_rate, div);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int ingenic_clk_check_stable(struct ingenic_cgu *cgu,
|
||||
|
|
@ -626,7 +627,7 @@ static const struct clk_ops ingenic_clk_ops = {
|
|||
.set_parent = ingenic_clk_set_parent,
|
||||
|
||||
.recalc_rate = ingenic_clk_recalc_rate,
|
||||
.round_rate = ingenic_clk_round_rate,
|
||||
.determine_rate = ingenic_clk_determine_rate,
|
||||
.set_rate = ingenic_clk_set_rate,
|
||||
|
||||
.enable = ingenic_clk_enable,
|
||||
|
|
|
|||
|
|
@ -178,18 +178,21 @@ static u8 ingenic_tcu_get_prescale(unsigned long rate, unsigned long req_rate)
|
|||
return 5; /* /1024 divider */
|
||||
}
|
||||
|
||||
static long ingenic_tcu_round_rate(struct clk_hw *hw, unsigned long req_rate,
|
||||
unsigned long *parent_rate)
|
||||
static int ingenic_tcu_determine_rate(struct clk_hw *hw,
|
||||
struct clk_rate_request *req)
|
||||
{
|
||||
unsigned long rate = *parent_rate;
|
||||
unsigned long rate = req->best_parent_rate;
|
||||
u8 prescale;
|
||||
|
||||
if (req_rate > rate)
|
||||
return rate;
|
||||
if (req->rate > rate) {
|
||||
req->rate = rate;
|
||||
return 0;
|
||||
}
|
||||
|
||||
prescale = ingenic_tcu_get_prescale(rate, req_rate);
|
||||
prescale = ingenic_tcu_get_prescale(rate, req->rate);
|
||||
|
||||
return rate >> (prescale * 2);
|
||||
req->rate = rate >> (prescale * 2);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int ingenic_tcu_set_rate(struct clk_hw *hw, unsigned long req_rate,
|
||||
|
|
@ -219,7 +222,7 @@ static const struct clk_ops ingenic_tcu_clk_ops = {
|
|||
.set_parent = ingenic_tcu_set_parent,
|
||||
|
||||
.recalc_rate = ingenic_tcu_recalc_rate,
|
||||
.round_rate = ingenic_tcu_round_rate,
|
||||
.determine_rate = ingenic_tcu_determine_rate,
|
||||
.set_rate = ingenic_tcu_set_rate,
|
||||
|
||||
.enable = ingenic_tcu_enable,
|
||||
|
|
|
|||
|
|
@ -294,6 +294,8 @@ static int _sci_clk_build(struct sci_clk_provider *provider,
|
|||
|
||||
name = kasprintf(GFP_KERNEL, "clk:%d:%d", sci_clk->dev_id,
|
||||
sci_clk->clk_id);
|
||||
if (!name)
|
||||
return -ENOMEM;
|
||||
|
||||
init.name = name;
|
||||
|
||||
|
|
|
|||
|
|
@ -4,10 +4,12 @@
|
|||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/mfd/syscon.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/slab.h>
|
||||
|
||||
struct ti_syscon_gate_clk_priv {
|
||||
struct clk_hw hw;
|
||||
|
|
@ -61,21 +63,31 @@ static const struct clk_ops ti_syscon_gate_clk_ops = {
|
|||
|
||||
static struct clk_hw
|
||||
*ti_syscon_gate_clk_register(struct device *dev, struct regmap *regmap,
|
||||
const char *parent_name,
|
||||
const struct ti_syscon_gate_clk_data *data)
|
||||
{
|
||||
struct ti_syscon_gate_clk_priv *priv;
|
||||
struct clk_init_data init;
|
||||
char *name = NULL;
|
||||
int ret;
|
||||
|
||||
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
|
||||
if (!priv)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
init.name = data->name;
|
||||
init.ops = &ti_syscon_gate_clk_ops;
|
||||
init.parent_names = NULL;
|
||||
init.num_parents = 0;
|
||||
init.flags = 0;
|
||||
if (parent_name) {
|
||||
name = kasprintf(GFP_KERNEL, "%s:%s", data->name, parent_name);
|
||||
init.name = name;
|
||||
init.parent_names = &parent_name;
|
||||
init.num_parents = 1;
|
||||
init.flags = CLK_SET_RATE_PARENT;
|
||||
} else {
|
||||
init.name = data->name;
|
||||
init.parent_names = NULL;
|
||||
init.num_parents = 0;
|
||||
init.flags = 0;
|
||||
}
|
||||
|
||||
priv->regmap = regmap;
|
||||
priv->reg = data->offset;
|
||||
|
|
@ -83,6 +95,10 @@ static struct clk_hw
|
|||
priv->hw.init = &init;
|
||||
|
||||
ret = devm_clk_hw_register(dev, &priv->hw);
|
||||
|
||||
if (name)
|
||||
kfree(init.name);
|
||||
|
||||
if (ret)
|
||||
return ERR_PTR(ret);
|
||||
|
||||
|
|
@ -94,22 +110,30 @@ static int ti_syscon_gate_clk_probe(struct platform_device *pdev)
|
|||
const struct ti_syscon_gate_clk_data *data, *p;
|
||||
struct clk_hw_onecell_data *hw_data;
|
||||
struct device *dev = &pdev->dev;
|
||||
int num_clks, num_parents, i;
|
||||
const char *parent_name;
|
||||
struct regmap *regmap;
|
||||
int num_clks, i;
|
||||
|
||||
data = device_get_match_data(dev);
|
||||
if (!data)
|
||||
return -EINVAL;
|
||||
|
||||
regmap = syscon_node_to_regmap(dev->of_node);
|
||||
regmap = device_node_to_regmap(dev->of_node);
|
||||
if (IS_ERR(regmap))
|
||||
return dev_err_probe(dev, PTR_ERR(regmap),
|
||||
"failed to find parent regmap\n");
|
||||
"failed to get regmap\n");
|
||||
|
||||
num_clks = 0;
|
||||
for (p = data; p->name; p++)
|
||||
num_clks++;
|
||||
|
||||
num_parents = of_clk_get_parent_count(dev->of_node);
|
||||
if (of_device_is_compatible(dev->of_node, "ti,am62-audio-refclk") &&
|
||||
num_parents == 0) {
|
||||
return dev_err_probe(dev, -EINVAL,
|
||||
"must specify a parent clock\n");
|
||||
}
|
||||
|
||||
hw_data = devm_kzalloc(dev, struct_size(hw_data, hws, num_clks),
|
||||
GFP_KERNEL);
|
||||
if (!hw_data)
|
||||
|
|
@ -117,8 +141,10 @@ static int ti_syscon_gate_clk_probe(struct platform_device *pdev)
|
|||
|
||||
hw_data->num = num_clks;
|
||||
|
||||
parent_name = of_clk_get_parent_name(dev->of_node, 0);
|
||||
for (i = 0; i < num_clks; i++) {
|
||||
hw_data->hws[i] = ti_syscon_gate_clk_register(dev, regmap,
|
||||
parent_name,
|
||||
&data[i]);
|
||||
if (IS_ERR(hw_data->hws[i]))
|
||||
dev_warn(dev, "failed to register %s\n",
|
||||
|
|
@ -166,6 +192,11 @@ static const struct ti_syscon_gate_clk_data am62_clk_data[] = {
|
|||
{ /* Sentinel */ },
|
||||
};
|
||||
|
||||
static const struct ti_syscon_gate_clk_data am62_audio_clk_data[] = {
|
||||
TI_SYSCON_CLK_GATE("audio_refclk", 0x0, 15),
|
||||
{ /* Sentinel */ },
|
||||
};
|
||||
|
||||
static const struct of_device_id ti_syscon_gate_clk_ids[] = {
|
||||
{
|
||||
.compatible = "ti,am654-ehrpwm-tbclk",
|
||||
|
|
@ -179,6 +210,10 @@ static const struct of_device_id ti_syscon_gate_clk_ids[] = {
|
|||
.compatible = "ti,am62-epwm-tbclk",
|
||||
.data = &am62_clk_data,
|
||||
},
|
||||
{
|
||||
.compatible = "ti,am62-audio-refclk",
|
||||
.data = &am62_audio_clk_data,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, ti_syscon_gate_clk_ids);
|
||||
|
|
|
|||
|
|
@ -781,72 +781,84 @@ config COMMON_CLK_MT8192
|
|||
config COMMON_CLK_MT8192_AUDSYS
|
||||
tristate "Clock driver for MediaTek MT8192 audsys"
|
||||
depends on COMMON_CLK_MT8192
|
||||
default COMMON_CLK_MT8192
|
||||
help
|
||||
This driver supports MediaTek MT8192 audsys clocks.
|
||||
|
||||
config COMMON_CLK_MT8192_CAMSYS
|
||||
tristate "Clock driver for MediaTek MT8192 camsys"
|
||||
depends on COMMON_CLK_MT8192
|
||||
default COMMON_CLK_MT8192
|
||||
help
|
||||
This driver supports MediaTek MT8192 camsys and camsys_raw clocks.
|
||||
|
||||
config COMMON_CLK_MT8192_IMGSYS
|
||||
tristate "Clock driver for MediaTek MT8192 imgsys"
|
||||
depends on COMMON_CLK_MT8192
|
||||
default COMMON_CLK_MT8192
|
||||
help
|
||||
This driver supports MediaTek MT8192 imgsys and imgsys2 clocks.
|
||||
|
||||
config COMMON_CLK_MT8192_IMP_IIC_WRAP
|
||||
tristate "Clock driver for MediaTek MT8192 imp_iic_wrap"
|
||||
depends on COMMON_CLK_MT8192
|
||||
default COMMON_CLK_MT8192
|
||||
help
|
||||
This driver supports MediaTek MT8192 imp_iic_wrap clocks.
|
||||
|
||||
config COMMON_CLK_MT8192_IPESYS
|
||||
tristate "Clock driver for MediaTek MT8192 ipesys"
|
||||
depends on COMMON_CLK_MT8192
|
||||
default COMMON_CLK_MT8192
|
||||
help
|
||||
This driver supports MediaTek MT8192 ipesys clocks.
|
||||
|
||||
config COMMON_CLK_MT8192_MDPSYS
|
||||
tristate "Clock driver for MediaTek MT8192 mdpsys"
|
||||
depends on COMMON_CLK_MT8192
|
||||
default COMMON_CLK_MT8192
|
||||
help
|
||||
This driver supports MediaTek MT8192 mdpsys clocks.
|
||||
|
||||
config COMMON_CLK_MT8192_MFGCFG
|
||||
tristate "Clock driver for MediaTek MT8192 mfgcfg"
|
||||
depends on COMMON_CLK_MT8192
|
||||
default COMMON_CLK_MT8192
|
||||
help
|
||||
This driver supports MediaTek MT8192 mfgcfg clocks.
|
||||
|
||||
config COMMON_CLK_MT8192_MMSYS
|
||||
tristate "Clock driver for MediaTek MT8192 mmsys"
|
||||
depends on COMMON_CLK_MT8192
|
||||
default COMMON_CLK_MT8192
|
||||
help
|
||||
This driver supports MediaTek MT8192 mmsys clocks.
|
||||
|
||||
config COMMON_CLK_MT8192_MSDC
|
||||
tristate "Clock driver for MediaTek MT8192 msdc"
|
||||
depends on COMMON_CLK_MT8192
|
||||
default COMMON_CLK_MT8192
|
||||
help
|
||||
This driver supports MediaTek MT8192 msdc and msdc_top clocks.
|
||||
|
||||
config COMMON_CLK_MT8192_SCP_ADSP
|
||||
tristate "Clock driver for MediaTek MT8192 scp_adsp"
|
||||
depends on COMMON_CLK_MT8192
|
||||
default COMMON_CLK_MT8192
|
||||
help
|
||||
This driver supports MediaTek MT8192 scp_adsp clocks.
|
||||
|
||||
config COMMON_CLK_MT8192_VDECSYS
|
||||
tristate "Clock driver for MediaTek MT8192 vdecsys"
|
||||
depends on COMMON_CLK_MT8192
|
||||
default COMMON_CLK_MT8192
|
||||
help
|
||||
This driver supports MediaTek MT8192 vdecsys and vdecsys_soc clocks.
|
||||
|
||||
config COMMON_CLK_MT8192_VENCSYS
|
||||
tristate "Clock driver for MediaTek MT8192 vencsys"
|
||||
depends on COMMON_CLK_MT8192
|
||||
default COMMON_CLK_MT8192
|
||||
help
|
||||
This driver supports MediaTek MT8192 vencsys clocks.
|
||||
|
||||
|
|
|
|||
|
|
@ -53,6 +53,7 @@ static int clk_cpumux_set_parent(struct clk_hw *hw, u8 index)
|
|||
}
|
||||
|
||||
static const struct clk_ops clk_cpumux_ops = {
|
||||
.determine_rate = clk_hw_determine_rate_no_reparent,
|
||||
.get_parent = clk_cpumux_get_parent,
|
||||
.set_parent = clk_cpumux_set_parent,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -150,15 +150,15 @@ err_plat_populate:
|
|||
return r;
|
||||
}
|
||||
|
||||
static int clk_mt2701_aud_remove(struct platform_device *pdev)
|
||||
static void clk_mt2701_aud_remove(struct platform_device *pdev)
|
||||
{
|
||||
of_platform_depopulate(&pdev->dev);
|
||||
return mtk_clk_simple_remove(pdev);
|
||||
mtk_clk_simple_remove(pdev);
|
||||
}
|
||||
|
||||
static struct platform_driver clk_mt2701_aud_drv = {
|
||||
.probe = clk_mt2701_aud_probe,
|
||||
.remove = clk_mt2701_aud_remove,
|
||||
.remove_new = clk_mt2701_aud_remove,
|
||||
.driver = {
|
||||
.name = "clk-mt2701-aud",
|
||||
.of_match_table = of_match_clk_mt2701_aud,
|
||||
|
|
|
|||
|
|
@ -99,7 +99,7 @@ MODULE_DEVICE_TABLE(of, of_match_clk_mt2701_bdp);
|
|||
|
||||
static struct platform_driver clk_mt2701_bdp_drv = {
|
||||
.probe = mtk_clk_simple_probe,
|
||||
.remove = mtk_clk_simple_remove,
|
||||
.remove_new = mtk_clk_simple_remove,
|
||||
.driver = {
|
||||
.name = "clk-mt2701-bdp",
|
||||
.of_match_table = of_match_clk_mt2701_bdp,
|
||||
|
|
|
|||
|
|
@ -53,7 +53,7 @@ MODULE_DEVICE_TABLE(of, of_match_clk_mt2701_eth);
|
|||
|
||||
static struct platform_driver clk_mt2701_eth_drv = {
|
||||
.probe = mtk_clk_simple_probe,
|
||||
.remove = mtk_clk_simple_remove,
|
||||
.remove_new = mtk_clk_simple_remove,
|
||||
.driver = {
|
||||
.name = "clk-mt2701-eth",
|
||||
.of_match_table = of_match_clk_mt2701_eth,
|
||||
|
|
|
|||
|
|
@ -52,7 +52,7 @@ MODULE_DEVICE_TABLE(of, of_match_clk_mt2701_g3d);
|
|||
|
||||
static struct platform_driver clk_mt2701_g3d_drv = {
|
||||
.probe = mtk_clk_simple_probe,
|
||||
.remove = mtk_clk_simple_remove,
|
||||
.remove_new = mtk_clk_simple_remove,
|
||||
.driver = {
|
||||
.name = "clk-mt2701-g3d",
|
||||
.of_match_table = of_match_clk_mt2701_g3d,
|
||||
|
|
|
|||
|
|
@ -50,7 +50,7 @@ MODULE_DEVICE_TABLE(of, of_match_clk_mt2701_hif);
|
|||
|
||||
static struct platform_driver clk_mt2701_hif_drv = {
|
||||
.probe = mtk_clk_simple_probe,
|
||||
.remove = mtk_clk_simple_remove,
|
||||
.remove_new = mtk_clk_simple_remove,
|
||||
.driver = {
|
||||
.name = "clk-mt2701-hif",
|
||||
.of_match_table = of_match_clk_mt2701_hif,
|
||||
|
|
|
|||
|
|
@ -47,7 +47,7 @@ MODULE_DEVICE_TABLE(of, of_match_clk_mt2701_img);
|
|||
|
||||
static struct platform_driver clk_mt2701_img_drv = {
|
||||
.probe = mtk_clk_simple_probe,
|
||||
.remove = mtk_clk_simple_remove,
|
||||
.remove_new = mtk_clk_simple_remove,
|
||||
.driver = {
|
||||
.name = "clk-mt2701-img",
|
||||
.of_match_table = of_match_clk_mt2701_img,
|
||||
|
|
|
|||
|
|
@ -80,7 +80,7 @@ MODULE_DEVICE_TABLE(platform, clk_mt2701_mm_id_table);
|
|||
|
||||
static struct platform_driver clk_mt2701_mm_drv = {
|
||||
.probe = mtk_clk_pdev_probe,
|
||||
.remove = mtk_clk_pdev_remove,
|
||||
.remove_new = mtk_clk_pdev_remove,
|
||||
.driver = {
|
||||
.name = "clk-mt2701-mm",
|
||||
},
|
||||
|
|
|
|||
|
|
@ -52,7 +52,7 @@ MODULE_DEVICE_TABLE(of, of_match_clk_mt2701_vdec);
|
|||
|
||||
static struct platform_driver clk_mt2701_vdec_drv = {
|
||||
.probe = mtk_clk_simple_probe,
|
||||
.remove = mtk_clk_simple_remove,
|
||||
.remove_new = mtk_clk_simple_remove,
|
||||
.driver = {
|
||||
.name = "clk-mt2701-vdec",
|
||||
.of_match_table = of_match_clk_mt2701_vdec,
|
||||
|
|
|
|||
|
|
@ -138,7 +138,7 @@ free_clk_data:
|
|||
return r;
|
||||
}
|
||||
|
||||
static int clk_mt2712_apmixed_remove(struct platform_device *pdev)
|
||||
static void clk_mt2712_apmixed_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
|
||||
|
|
@ -146,8 +146,6 @@ static int clk_mt2712_apmixed_remove(struct platform_device *pdev)
|
|||
of_clk_del_provider(node);
|
||||
mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
|
||||
mtk_free_clk_data(clk_data);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id of_match_clk_mt2712_apmixed[] = {
|
||||
|
|
@ -158,7 +156,7 @@ MODULE_DEVICE_TABLE(of, of_match_clk_mt2712_apmixed);
|
|||
|
||||
static struct platform_driver clk_mt2712_apmixed_drv = {
|
||||
.probe = clk_mt2712_apmixed_probe,
|
||||
.remove = clk_mt2712_apmixed_remove,
|
||||
.remove_new = clk_mt2712_apmixed_remove,
|
||||
.driver = {
|
||||
.name = "clk-mt2712-apmixed",
|
||||
.of_match_table = of_match_clk_mt2712_apmixed,
|
||||
|
|
|
|||
|
|
@ -69,7 +69,7 @@ MODULE_DEVICE_TABLE(of, of_match_clk_mt2712_bdp);
|
|||
|
||||
static struct platform_driver clk_mt2712_bdp_drv = {
|
||||
.probe = mtk_clk_simple_probe,
|
||||
.remove = mtk_clk_simple_remove,
|
||||
.remove_new = mtk_clk_simple_remove,
|
||||
.driver = {
|
||||
.name = "clk-mt2712-bdp",
|
||||
.of_match_table = of_match_clk_mt2712_bdp,
|
||||
|
|
|
|||
|
|
@ -47,7 +47,7 @@ MODULE_DEVICE_TABLE(of, of_match_clk_mt2712_img);
|
|||
|
||||
static struct platform_driver clk_mt2712_img_drv = {
|
||||
.probe = mtk_clk_simple_probe,
|
||||
.remove = mtk_clk_simple_remove,
|
||||
.remove_new = mtk_clk_simple_remove,
|
||||
.driver = {
|
||||
.name = "clk-mt2712-img",
|
||||
.of_match_table = of_match_clk_mt2712_img,
|
||||
|
|
|
|||
|
|
@ -43,7 +43,7 @@ MODULE_DEVICE_TABLE(of, of_match_clk_mt2712_jpgdec);
|
|||
|
||||
static struct platform_driver clk_mt2712_jpgdec_drv = {
|
||||
.probe = mtk_clk_simple_probe,
|
||||
.remove = mtk_clk_simple_remove,
|
||||
.remove_new = mtk_clk_simple_remove,
|
||||
.driver = {
|
||||
.name = "clk-mt2712-jpgdec",
|
||||
.of_match_table = of_match_clk_mt2712_jpgdec,
|
||||
|
|
|
|||
|
|
@ -42,7 +42,7 @@ MODULE_DEVICE_TABLE(of, of_match_clk_mt2712_mfg);
|
|||
|
||||
static struct platform_driver clk_mt2712_mfg_drv = {
|
||||
.probe = mtk_clk_simple_probe,
|
||||
.remove = mtk_clk_simple_remove,
|
||||
.remove_new = mtk_clk_simple_remove,
|
||||
.driver = {
|
||||
.name = "clk-mt2712-mfg",
|
||||
.of_match_table = of_match_clk_mt2712_mfg,
|
||||
|
|
|
|||
|
|
@ -121,7 +121,7 @@ MODULE_DEVICE_TABLE(platform, clk_mt2712_mm_id_table);
|
|||
|
||||
static struct platform_driver clk_mt2712_mm_drv = {
|
||||
.probe = mtk_clk_pdev_probe,
|
||||
.remove = mtk_clk_pdev_remove,
|
||||
.remove_new = mtk_clk_pdev_remove,
|
||||
.driver = {
|
||||
.name = "clk-mt2712-mm",
|
||||
},
|
||||
|
|
|
|||
|
|
@ -55,7 +55,7 @@ MODULE_DEVICE_TABLE(of, of_match_clk_mt2712_vdec);
|
|||
|
||||
static struct platform_driver clk_mt2712_vdec_drv = {
|
||||
.probe = mtk_clk_simple_probe,
|
||||
.remove = mtk_clk_simple_remove,
|
||||
.remove_new = mtk_clk_simple_remove,
|
||||
.driver = {
|
||||
.name = "clk-mt2712-vdec",
|
||||
.of_match_table = of_match_clk_mt2712_vdec,
|
||||
|
|
|
|||
|
|
@ -44,7 +44,7 @@ MODULE_DEVICE_TABLE(of, of_match_clk_mt2712_venc);
|
|||
|
||||
static struct platform_driver clk_mt2712_venc_drv = {
|
||||
.probe = mtk_clk_simple_probe,
|
||||
.remove = mtk_clk_simple_remove,
|
||||
.remove_new = mtk_clk_simple_remove,
|
||||
.driver = {
|
||||
.name = "clk-mt2712-venc",
|
||||
.of_match_table = of_match_clk_mt2712_venc,
|
||||
|
|
|
|||
|
|
@ -995,7 +995,7 @@ MODULE_DEVICE_TABLE(of, of_match_clk_mt2712);
|
|||
|
||||
static struct platform_driver clk_mt2712_drv = {
|
||||
.probe = mtk_clk_simple_probe,
|
||||
.remove = mtk_clk_simple_remove,
|
||||
.remove_new = mtk_clk_simple_remove,
|
||||
.driver = {
|
||||
.name = "clk-mt2712",
|
||||
.of_match_table = of_match_clk_mt2712,
|
||||
|
|
|
|||
|
|
@ -69,7 +69,7 @@ MODULE_DEVICE_TABLE(of, of_match_clk_mt6765_audio);
|
|||
|
||||
static struct platform_driver clk_mt6765_audio_drv = {
|
||||
.probe = mtk_clk_simple_probe,
|
||||
.remove = mtk_clk_simple_remove,
|
||||
.remove_new = mtk_clk_simple_remove,
|
||||
.driver = {
|
||||
.name = "clk-mt6765-audio",
|
||||
.of_match_table = of_match_clk_mt6765_audio,
|
||||
|
|
|
|||
|
|
@ -50,7 +50,7 @@ MODULE_DEVICE_TABLE(of, of_match_clk_mt6765_cam);
|
|||
|
||||
static struct platform_driver clk_mt6765_cam_drv = {
|
||||
.probe = mtk_clk_simple_probe,
|
||||
.remove = mtk_clk_simple_remove,
|
||||
.remove_new = mtk_clk_simple_remove,
|
||||
.driver = {
|
||||
.name = "clk-mt6765-cam",
|
||||
.of_match_table = of_match_clk_mt6765_cam,
|
||||
|
|
|
|||
|
|
@ -46,7 +46,7 @@ MODULE_DEVICE_TABLE(of, of_match_clk_mt6765_img);
|
|||
|
||||
static struct platform_driver clk_mt6765_img_drv = {
|
||||
.probe = mtk_clk_simple_probe,
|
||||
.remove = mtk_clk_simple_remove,
|
||||
.remove_new = mtk_clk_simple_remove,
|
||||
.driver = {
|
||||
.name = "clk-mt6765-img",
|
||||
.of_match_table = of_match_clk_mt6765_img,
|
||||
|
|
|
|||
|
|
@ -43,7 +43,7 @@ MODULE_DEVICE_TABLE(of, of_match_clk_mt6765_mipi0a);
|
|||
|
||||
static struct platform_driver clk_mt6765_mipi0a_drv = {
|
||||
.probe = mtk_clk_simple_probe,
|
||||
.remove = mtk_clk_simple_remove,
|
||||
.remove_new = mtk_clk_simple_remove,
|
||||
.driver = {
|
||||
.name = "clk-mt6765-mipi0a",
|
||||
.of_match_table = of_match_clk_mt6765_mipi0a,
|
||||
|
|
|
|||
|
|
@ -72,7 +72,7 @@ MODULE_DEVICE_TABLE(of, of_match_clk_mt6765_mm);
|
|||
|
||||
static struct platform_driver clk_mt6765_mm_drv = {
|
||||
.probe = mtk_clk_simple_probe,
|
||||
.remove = mtk_clk_simple_remove,
|
||||
.remove_new = mtk_clk_simple_remove,
|
||||
.driver = {
|
||||
.name = "clk-mt6765-mm",
|
||||
.of_match_table = of_match_clk_mt6765_mm,
|
||||
|
|
|
|||
|
|
@ -45,7 +45,7 @@ MODULE_DEVICE_TABLE(of, of_match_clk_mt6765_vcodec);
|
|||
|
||||
static struct platform_driver clk_mt6765_vcodec_drv = {
|
||||
.probe = mtk_clk_simple_probe,
|
||||
.remove = mtk_clk_simple_remove,
|
||||
.remove_new = mtk_clk_simple_remove,
|
||||
.driver = {
|
||||
.name = "clk-mt6765-vcodec",
|
||||
.of_match_table = of_match_clk_mt6765_vcodec,
|
||||
|
|
|
|||
|
|
@ -367,10 +367,12 @@ static const struct mtk_mux top_muxes[] = {
|
|||
/* CLK_CFG_0 */
|
||||
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
|
||||
CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_CLR,
|
||||
0, 2, 7, CLK_CFG_UPDATE, 0, CLK_IS_CRITICAL),
|
||||
0, 2, 7, CLK_CFG_UPDATE, 0,
|
||||
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
|
||||
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
|
||||
CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_CLR,
|
||||
8, 2, 15, CLK_CFG_UPDATE, 1, CLK_IS_CRITICAL),
|
||||
8, 2, 15, CLK_CFG_UPDATE, 1,
|
||||
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_MM_SEL, "mm_sel", mm_parents, CLK_CFG_0,
|
||||
CLK_CFG_0_SET, CLK_CFG_0_CLR, 16, 3, 23,
|
||||
CLK_CFG_UPDATE, 2),
|
||||
|
|
@ -404,15 +406,15 @@ static const struct mtk_mux top_muxes[] = {
|
|||
CLK_CFG_2_SET, CLK_CFG_2_CLR, 24, 2, 31,
|
||||
CLK_CFG_UPDATE, 11),
|
||||
/* CLK_CFG_3 */
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_HCLK_SEL, "msdc5hclk",
|
||||
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_HCLK_SEL, "msdc5hclk",
|
||||
msdc5hclk_parents, CLK_CFG_3, CLK_CFG_3_SET,
|
||||
CLK_CFG_3_CLR, 0, 2, 7, CLK_CFG_UPDATE, 12),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel",
|
||||
CLK_CFG_3_CLR, 0, 2, 7, CLK_CFG_UPDATE, 12, 0),
|
||||
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel",
|
||||
msdc50_0_parents, CLK_CFG_3, CLK_CFG_3_SET,
|
||||
CLK_CFG_3_CLR, 8, 3, 15, CLK_CFG_UPDATE, 13),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel",
|
||||
CLK_CFG_3_CLR, 8, 3, 15, CLK_CFG_UPDATE, 13, 0),
|
||||
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel",
|
||||
msdc30_1_parents, CLK_CFG_3, CLK_CFG_3_SET,
|
||||
CLK_CFG_3_CLR, 16, 3, 23, CLK_CFG_UPDATE, 14),
|
||||
CLK_CFG_3_CLR, 16, 3, 23, CLK_CFG_UPDATE, 14, 0),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents,
|
||||
CLK_CFG_3, CLK_CFG_3_SET, CLK_CFG_3_CLR,
|
||||
24, 2, 31, CLK_CFG_UPDATE, 15),
|
||||
|
|
@ -459,7 +461,7 @@ static const struct mtk_mux top_muxes[] = {
|
|||
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_PWRAP_ULPOSC_SEL, "ulposc_sel",
|
||||
ulposc_parents, CLK_CFG_7, CLK_CFG_7_SET,
|
||||
CLK_CFG_7_CLR, 0, 3, 7, CLK_CFG_UPDATE, 28,
|
||||
CLK_IS_CRITICAL),
|
||||
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM_SEL, "camtm_sel", camtm_parents,
|
||||
CLK_CFG_7, CLK_CFG_7_SET, CLK_CFG_7_CLR, 8, 2, 15,
|
||||
CLK_CFG_UPDATE, 29),
|
||||
|
|
|
|||
|
|
@ -106,7 +106,7 @@ MODULE_DEVICE_TABLE(of, of_match_clk_mt6779_aud);
|
|||
|
||||
static struct platform_driver clk_mt6779_aud_drv = {
|
||||
.probe = mtk_clk_simple_probe,
|
||||
.remove = mtk_clk_simple_remove,
|
||||
.remove_new = mtk_clk_simple_remove,
|
||||
.driver = {
|
||||
.name = "clk-mt6779-aud",
|
||||
.of_match_table = of_match_clk_mt6779_aud,
|
||||
|
|
|
|||
|
|
@ -55,7 +55,7 @@ MODULE_DEVICE_TABLE(of, of_match_clk_mt6779_cam);
|
|||
|
||||
static struct platform_driver clk_mt6779_cam_drv = {
|
||||
.probe = mtk_clk_simple_probe,
|
||||
.remove = mtk_clk_simple_remove,
|
||||
.remove_new = mtk_clk_simple_remove,
|
||||
.driver = {
|
||||
.name = "clk-mt6779-cam",
|
||||
.of_match_table = of_match_clk_mt6779_cam,
|
||||
|
|
|
|||
|
|
@ -47,7 +47,7 @@ MODULE_DEVICE_TABLE(of, of_match_clk_mt6779_img);
|
|||
|
||||
static struct platform_driver clk_mt6779_img_drv = {
|
||||
.probe = mtk_clk_simple_probe,
|
||||
.remove = mtk_clk_simple_remove,
|
||||
.remove_new = mtk_clk_simple_remove,
|
||||
.driver = {
|
||||
.name = "clk-mt6779-img",
|
||||
.of_match_table = of_match_clk_mt6779_img,
|
||||
|
|
|
|||
|
|
@ -49,7 +49,7 @@ MODULE_DEVICE_TABLE(of, of_match_clk_mt6779_ipe);
|
|||
|
||||
static struct platform_driver clk_mt6779_ipe_drv = {
|
||||
.probe = mtk_clk_simple_probe,
|
||||
.remove = mtk_clk_simple_remove,
|
||||
.remove_new = mtk_clk_simple_remove,
|
||||
.driver = {
|
||||
.name = "clk-mt6779-ipe",
|
||||
.of_match_table = of_match_clk_mt6779_ipe,
|
||||
|
|
|
|||
|
|
@ -44,7 +44,7 @@ MODULE_DEVICE_TABLE(of, of_match_clk_mt6779_mfg);
|
|||
|
||||
static struct platform_driver clk_mt6779_mfg_drv = {
|
||||
.probe = mtk_clk_simple_probe,
|
||||
.remove = mtk_clk_simple_remove,
|
||||
.remove_new = mtk_clk_simple_remove,
|
||||
.driver = {
|
||||
.name = "clk-mt6779-mfg",
|
||||
.of_match_table = of_match_clk_mt6779_mfg,
|
||||
|
|
|
|||
|
|
@ -98,7 +98,7 @@ MODULE_DEVICE_TABLE(platform, clk_mt6779_mm_id_table);
|
|||
|
||||
static struct platform_driver clk_mt6779_mm_drv = {
|
||||
.probe = mtk_clk_pdev_probe,
|
||||
.remove = mtk_clk_pdev_remove,
|
||||
.remove_new = mtk_clk_pdev_remove,
|
||||
.driver = {
|
||||
.name = "clk-mt6779-mm",
|
||||
},
|
||||
|
|
|
|||
|
|
@ -56,7 +56,7 @@ MODULE_DEVICE_TABLE(of, of_match_clk_mt6779_vdec);
|
|||
|
||||
static struct platform_driver clk_mt6779_vdec_drv = {
|
||||
.probe = mtk_clk_simple_probe,
|
||||
.remove = mtk_clk_simple_remove,
|
||||
.remove_new = mtk_clk_simple_remove,
|
||||
.driver = {
|
||||
.name = "clk-mt6779-vdec",
|
||||
.of_match_table = of_match_clk_mt6779_vdec,
|
||||
|
|
|
|||
|
|
@ -47,7 +47,7 @@ MODULE_DEVICE_TABLE(of, of_match_clk_mt6779_venc);
|
|||
|
||||
static struct platform_driver clk_mt6779_venc_drv = {
|
||||
.probe = mtk_clk_simple_probe,
|
||||
.remove = mtk_clk_simple_remove,
|
||||
.remove_new = mtk_clk_simple_remove,
|
||||
.driver = {
|
||||
.name = "clk-mt6779-venc",
|
||||
.of_match_table = of_match_clk_mt6779_venc,
|
||||
|
|
|
|||
|
|
@ -640,7 +640,7 @@ static const struct mtk_mux top_muxes[] = {
|
|||
/* CLK_CFG_0 */
|
||||
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI, "axi_sel", axi_parents,
|
||||
0x20, 0x24, 0x28, 0, 2, 7,
|
||||
0x004, 0, CLK_IS_CRITICAL),
|
||||
0x004, 0, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_MM, "mm_sel", mm_parents,
|
||||
0x20, 0x24, 0x28, 8, 3, 15, 0x004, 1),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP, "scp_sel", scp_parents,
|
||||
|
|
@ -687,16 +687,16 @@ static const struct mtk_mux top_muxes[] = {
|
|||
0x70, 0x74, 0x78, 0, 1, 7, 0x004, 20),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI, "spi_sel", spi_parents,
|
||||
0x70, 0x74, 0x78, 8, 2, 15, 0x004, 21),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_HCLK, "msdc50_hclk_sel",
|
||||
msdc50_hclk_parents, 0x70, 0x74, 0x78,
|
||||
16, 2, 23, 0x004, 22),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0, "msdc50_0_sel",
|
||||
msdc50_0_parents, 0x70, 0x74, 0x78,
|
||||
24, 3, 31, 0x004, 23),
|
||||
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_HCLK, "msdc50_hclk_sel",
|
||||
msdc50_hclk_parents, 0x70, 0x74, 0x78,
|
||||
16, 2, 23, 0x004, 22, 0),
|
||||
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0, "msdc50_0_sel",
|
||||
msdc50_0_parents, 0x70, 0x74, 0x78,
|
||||
24, 3, 31, 0x004, 23, 0),
|
||||
/* CLK_CFG_6 */
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1, "msdc30_1_sel",
|
||||
msdc30_1_parents, 0x80, 0x84, 0x88,
|
||||
0, 3, 7, 0x004, 24),
|
||||
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_1, "msdc30_1_sel",
|
||||
msdc30_1_parents, 0x80, 0x84, 0x88,
|
||||
0, 3, 7, 0x004, 24, 0),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD, "audio_sel", audio_parents,
|
||||
0x80, 0x84, 0x88, 8, 2, 15, 0x004, 25),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS, "aud_intbus_sel",
|
||||
|
|
@ -710,7 +710,7 @@ static const struct mtk_mux top_muxes[] = {
|
|||
0x90, 0x94, 0x98, 0, 2, 7, 0x004, 28),
|
||||
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SSPM, "sspm_sel", sspm_parents,
|
||||
0x90, 0x94, 0x98, 8, 3, 15,
|
||||
0x004, 29, CLK_IS_CRITICAL),
|
||||
0x004, 29, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI0, "dpi0_sel", dpi0_parents,
|
||||
0x90, 0x94, 0x98, 16, 3, 23, 0x004, 30),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_SCAM, "scam_sel", scam_parents,
|
||||
|
|
@ -727,7 +727,7 @@ static const struct mtk_mux top_muxes[] = {
|
|||
16, 2, 23, 0x008, 3),
|
||||
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SPM, "spm_sel", spm_parents,
|
||||
0xa0, 0xa4, 0xa8, 24, 2, 31,
|
||||
0x008, 4, CLK_IS_CRITICAL),
|
||||
0x008, 4, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
|
||||
/* CLK_CFG_9 */
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C, "i2c_sel", i2c_parents,
|
||||
0xb0, 0xb4, 0xb8, 0, 2, 7, 0x008, 5),
|
||||
|
|
@ -1303,7 +1303,7 @@ MODULE_DEVICE_TABLE(of, of_match_clk_mt6779);
|
|||
|
||||
static struct platform_driver clk_mt6779_infra_drv = {
|
||||
.probe = mtk_clk_simple_probe,
|
||||
.remove = mtk_clk_simple_remove,
|
||||
.remove_new = mtk_clk_simple_remove,
|
||||
.driver = {
|
||||
.name = "clk-mt6779-infra",
|
||||
.of_match_table = of_match_clk_mt6779_infra,
|
||||
|
|
|
|||
|
|
@ -187,7 +187,7 @@ free_clk_data:
|
|||
return ret;
|
||||
}
|
||||
|
||||
static int clk_mt6795_apmixed_remove(struct platform_device *pdev)
|
||||
static void clk_mt6795_apmixed_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
|
||||
|
|
@ -197,13 +197,11 @@ static int clk_mt6795_apmixed_remove(struct platform_device *pdev)
|
|||
mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs,
|
||||
ARRAY_SIZE(pllfhs), clk_data);
|
||||
mtk_free_clk_data(clk_data);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver clk_mt6795_apmixed_drv = {
|
||||
.probe = clk_mt6795_apmixed_probe,
|
||||
.remove = clk_mt6795_apmixed_remove,
|
||||
.remove_new = clk_mt6795_apmixed_remove,
|
||||
.driver = {
|
||||
.name = "clk-mt6795-apmixed",
|
||||
.of_match_table = of_match_clk_mt6795_apmixed,
|
||||
|
|
|
|||
|
|
@ -127,7 +127,7 @@ free_clk_data:
|
|||
return ret;
|
||||
}
|
||||
|
||||
static int clk_mt6795_infracfg_remove(struct platform_device *pdev)
|
||||
static void clk_mt6795_infracfg_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
|
||||
|
|
@ -136,8 +136,6 @@ static int clk_mt6795_infracfg_remove(struct platform_device *pdev)
|
|||
mtk_clk_unregister_cpumuxes(cpu_muxes, ARRAY_SIZE(cpu_muxes), clk_data);
|
||||
mtk_clk_unregister_gates(infra_gates, ARRAY_SIZE(infra_gates), clk_data);
|
||||
mtk_free_clk_data(clk_data);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver clk_mt6795_infracfg_drv = {
|
||||
|
|
@ -146,7 +144,7 @@ static struct platform_driver clk_mt6795_infracfg_drv = {
|
|||
.of_match_table = of_match_clk_mt6795_infracfg,
|
||||
},
|
||||
.probe = clk_mt6795_infracfg_probe,
|
||||
.remove = clk_mt6795_infracfg_remove,
|
||||
.remove_new = clk_mt6795_infracfg_remove,
|
||||
};
|
||||
module_platform_driver(clk_mt6795_infracfg_drv);
|
||||
|
||||
|
|
|
|||
|
|
@ -43,7 +43,7 @@ static struct platform_driver clk_mt6795_mfg_drv = {
|
|||
.of_match_table = of_match_clk_mt6795_mfg,
|
||||
},
|
||||
.probe = mtk_clk_simple_probe,
|
||||
.remove = mtk_clk_simple_remove,
|
||||
.remove_new = mtk_clk_simple_remove,
|
||||
};
|
||||
module_platform_driver(clk_mt6795_mfg_drv);
|
||||
|
||||
|
|
|
|||
|
|
@ -93,7 +93,7 @@ static struct platform_driver clk_mt6795_mm_drv = {
|
|||
},
|
||||
.id_table = clk_mt6795_mm_id_table,
|
||||
.probe = mtk_clk_pdev_probe,
|
||||
.remove = mtk_clk_pdev_remove,
|
||||
.remove_new = mtk_clk_pdev_remove,
|
||||
};
|
||||
module_platform_driver(clk_mt6795_mm_drv);
|
||||
|
||||
|
|
|
|||
|
|
@ -136,7 +136,7 @@ free_clk_data:
|
|||
return ret;
|
||||
}
|
||||
|
||||
static int clk_mt6795_pericfg_remove(struct platform_device *pdev)
|
||||
static void clk_mt6795_pericfg_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
|
||||
|
|
@ -145,8 +145,6 @@ static int clk_mt6795_pericfg_remove(struct platform_device *pdev)
|
|||
mtk_clk_unregister_composites(peri_clks, ARRAY_SIZE(peri_clks), clk_data);
|
||||
mtk_clk_unregister_gates(peri_gates, ARRAY_SIZE(peri_gates), clk_data);
|
||||
mtk_free_clk_data(clk_data);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver clk_mt6795_pericfg_drv = {
|
||||
|
|
@ -155,7 +153,7 @@ static struct platform_driver clk_mt6795_pericfg_drv = {
|
|||
.of_match_table = of_match_clk_mt6795_pericfg,
|
||||
},
|
||||
.probe = clk_mt6795_pericfg_probe,
|
||||
.remove = clk_mt6795_pericfg_remove,
|
||||
.remove_new = clk_mt6795_pericfg_remove,
|
||||
};
|
||||
module_platform_driver(clk_mt6795_pericfg_drv);
|
||||
|
||||
|
|
|
|||
|
|
@ -547,7 +547,7 @@ static struct platform_driver clk_mt6795_topckgen_drv = {
|
|||
.of_match_table = of_match_clk_mt6795_topckgen,
|
||||
},
|
||||
.probe = mtk_clk_simple_probe,
|
||||
.remove = mtk_clk_simple_remove,
|
||||
.remove_new = mtk_clk_simple_remove,
|
||||
};
|
||||
module_platform_driver(clk_mt6795_topckgen_drv);
|
||||
|
||||
|
|
|
|||
|
|
@ -44,7 +44,7 @@ MODULE_DEVICE_TABLE(of, of_match_clk_mt6795_vdecsys);
|
|||
|
||||
static struct platform_driver clk_mt6795_vdecsys_drv = {
|
||||
.probe = mtk_clk_simple_probe,
|
||||
.remove = mtk_clk_simple_remove,
|
||||
.remove_new = mtk_clk_simple_remove,
|
||||
.driver = {
|
||||
.name = "clk-mt6795-vdecsys",
|
||||
.of_match_table = of_match_clk_mt6795_vdecsys,
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue