Break up monolithic iommu table/lock into finer graularity pools and lock
Investigation of multithreaded iperf experiments on an ethernet interface show the iommu->lock as the hottest lock identified by lockstat, with something of the order of 21M contentions out of 27M acquisitions, and an average wait time of 26 us for the lock. This is not efficient. A more scalable design is to follow the ppc model, where the iommu_map_table has multiple pools, each stretching over a segment of the map, and with a separate lock for each pool. This model allows for better parallelization of the iommu map search. This patch adds the iommu range alloc/free function infrastructure. Signed-off-by: Sowmini Varadhan <sowmini.varadhan@oracle.com> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Sowmini Varadhan
David S. Miller
parent
c12f048ffd
commit
ff7d37a502
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@ -0,0 +1,51 @@
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#ifndef _LINUX_IOMMU_COMMON_H
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#define _LINUX_IOMMU_COMMON_H
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#include <linux/spinlock_types.h>
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#include <linux/device.h>
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#include <asm/page.h>
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#define IOMMU_POOL_HASHBITS 4
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#define IOMMU_NR_POOLS (1 << IOMMU_POOL_HASHBITS)
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struct iommu_pool {
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unsigned long start;
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unsigned long end;
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unsigned long hint;
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spinlock_t lock;
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};
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struct iommu_map_table {
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unsigned long table_map_base;
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unsigned long table_shift;
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unsigned long nr_pools;
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void (*lazy_flush)(struct iommu_map_table *);
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unsigned long poolsize;
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struct iommu_pool pools[IOMMU_NR_POOLS];
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u32 flags;
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#define IOMMU_HAS_LARGE_POOL 0x00000001
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#define IOMMU_NO_SPAN_BOUND 0x00000002
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#define IOMMU_NEED_FLUSH 0x00000004
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struct iommu_pool large_pool;
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unsigned long *map;
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};
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extern void iommu_tbl_pool_init(struct iommu_map_table *iommu,
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unsigned long num_entries,
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u32 table_shift,
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void (*lazy_flush)(struct iommu_map_table *),
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bool large_pool, u32 npools,
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bool skip_span_boundary_check);
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extern unsigned long iommu_tbl_range_alloc(struct device *dev,
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struct iommu_map_table *iommu,
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unsigned long npages,
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unsigned long *handle,
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unsigned long mask,
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unsigned int align_order);
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extern void iommu_tbl_range_free(struct iommu_map_table *iommu,
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u64 dma_addr, unsigned long npages,
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unsigned long entry);
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#endif
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@ -106,7 +106,7 @@ obj-$(CONFIG_AUDIT_GENERIC) += audit.o
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obj-$(CONFIG_AUDIT_COMPAT_GENERIC) += compat_audit.o
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obj-$(CONFIG_SWIOTLB) += swiotlb.o
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obj-$(CONFIG_IOMMU_HELPER) += iommu-helper.o
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obj-$(CONFIG_IOMMU_HELPER) += iommu-helper.o iommu-common.o
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obj-$(CONFIG_FAULT_INJECTION) += fault-inject.o
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obj-$(CONFIG_NOTIFIER_ERROR_INJECTION) += notifier-error-inject.o
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obj-$(CONFIG_CPU_NOTIFIER_ERROR_INJECT) += cpu-notifier-error-inject.o
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@ -0,0 +1,266 @@
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/*
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* IOMMU mmap management and range allocation functions.
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* Based almost entirely upon the powerpc iommu allocator.
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*/
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#include <linux/export.h>
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#include <linux/bitmap.h>
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#include <linux/bug.h>
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#include <linux/iommu-helper.h>
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#include <linux/iommu-common.h>
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#include <linux/dma-mapping.h>
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#include <linux/hash.h>
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unsigned long iommu_large_alloc = 15;
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static DEFINE_PER_CPU(unsigned int, iommu_pool_hash);
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static inline bool need_flush(struct iommu_map_table *iommu)
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{
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return (iommu->lazy_flush != NULL &&
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(iommu->flags & IOMMU_NEED_FLUSH) != 0);
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}
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static inline void set_flush(struct iommu_map_table *iommu)
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{
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iommu->flags |= IOMMU_NEED_FLUSH;
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}
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static inline void clear_flush(struct iommu_map_table *iommu)
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{
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iommu->flags &= ~IOMMU_NEED_FLUSH;
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}
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static void setup_iommu_pool_hash(void)
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{
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unsigned int i;
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static bool do_once;
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if (do_once)
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return;
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do_once = true;
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for_each_possible_cpu(i)
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per_cpu(iommu_pool_hash, i) = hash_32(i, IOMMU_POOL_HASHBITS);
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}
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/*
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* Initialize iommu_pool entries for the iommu_map_table. `num_entries'
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* is the number of table entries. If `large_pool' is set to true,
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* the top 1/4 of the table will be set aside for pool allocations
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* of more than iommu_large_alloc pages.
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*/
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extern void iommu_tbl_pool_init(struct iommu_map_table *iommu,
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unsigned long num_entries,
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u32 table_shift,
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void (*lazy_flush)(struct iommu_map_table *),
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bool large_pool, u32 npools,
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bool skip_span_boundary_check)
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{
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unsigned int start, i;
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struct iommu_pool *p = &(iommu->large_pool);
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setup_iommu_pool_hash();
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if (npools == 0)
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iommu->nr_pools = IOMMU_NR_POOLS;
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else
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iommu->nr_pools = npools;
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BUG_ON(npools > IOMMU_NR_POOLS);
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iommu->table_shift = table_shift;
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iommu->lazy_flush = lazy_flush;
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start = 0;
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if (skip_span_boundary_check)
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iommu->flags |= IOMMU_NO_SPAN_BOUND;
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if (large_pool)
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iommu->flags |= IOMMU_HAS_LARGE_POOL;
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if (!large_pool)
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iommu->poolsize = num_entries/iommu->nr_pools;
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else
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iommu->poolsize = (num_entries * 3 / 4)/iommu->nr_pools;
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for (i = 0; i < iommu->nr_pools; i++) {
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spin_lock_init(&(iommu->pools[i].lock));
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iommu->pools[i].start = start;
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iommu->pools[i].hint = start;
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start += iommu->poolsize; /* start for next pool */
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iommu->pools[i].end = start - 1;
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}
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if (!large_pool)
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return;
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/* initialize large_pool */
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spin_lock_init(&(p->lock));
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p->start = start;
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p->hint = p->start;
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p->end = num_entries;
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}
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EXPORT_SYMBOL(iommu_tbl_pool_init);
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unsigned long iommu_tbl_range_alloc(struct device *dev,
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struct iommu_map_table *iommu,
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unsigned long npages,
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unsigned long *handle,
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unsigned long mask,
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unsigned int align_order)
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{
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unsigned int pool_hash = __this_cpu_read(iommu_pool_hash);
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unsigned long n, end, start, limit, boundary_size;
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struct iommu_pool *pool;
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int pass = 0;
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unsigned int pool_nr;
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unsigned int npools = iommu->nr_pools;
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unsigned long flags;
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bool large_pool = ((iommu->flags & IOMMU_HAS_LARGE_POOL) != 0);
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bool largealloc = (large_pool && npages > iommu_large_alloc);
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unsigned long shift;
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unsigned long align_mask = 0;
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if (align_order > 0)
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align_mask = 0xffffffffffffffffl >> (64 - align_order);
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/* Sanity check */
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if (unlikely(npages == 0)) {
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WARN_ON_ONCE(1);
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return DMA_ERROR_CODE;
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}
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if (largealloc) {
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pool = &(iommu->large_pool);
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pool_nr = 0; /* to keep compiler happy */
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} else {
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/* pick out pool_nr */
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pool_nr = pool_hash & (npools - 1);
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pool = &(iommu->pools[pool_nr]);
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}
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spin_lock_irqsave(&pool->lock, flags);
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again:
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if (pass == 0 && handle && *handle &&
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(*handle >= pool->start) && (*handle < pool->end))
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start = *handle;
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else
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start = pool->hint;
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limit = pool->end;
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/* The case below can happen if we have a small segment appended
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* to a large, or when the previous alloc was at the very end of
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* the available space. If so, go back to the beginning. If a
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* flush is needed, it will get done based on the return value
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* from iommu_area_alloc() below.
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*/
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if (start >= limit)
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start = pool->start;
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shift = iommu->table_map_base >> iommu->table_shift;
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if (limit + shift > mask) {
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limit = mask - shift + 1;
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/* If we're constrained on address range, first try
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* at the masked hint to avoid O(n) search complexity,
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* but on second pass, start at 0 in pool 0.
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*/
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if ((start & mask) >= limit || pass > 0) {
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spin_unlock(&(pool->lock));
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pool = &(iommu->pools[0]);
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spin_lock(&(pool->lock));
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start = pool->start;
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} else {
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start &= mask;
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}
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}
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if (dev)
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boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
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1 << iommu->table_shift);
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else
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boundary_size = ALIGN(1UL << 32, 1 << iommu->table_shift);
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boundary_size = boundary_size >> iommu->table_shift;
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/*
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* if the skip_span_boundary_check had been set during init, we set
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* things up so that iommu_is_span_boundary() merely checks if the
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* (index + npages) < num_tsb_entries
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*/
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if ((iommu->flags & IOMMU_NO_SPAN_BOUND) != 0) {
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shift = 0;
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boundary_size = iommu->poolsize * iommu->nr_pools;
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}
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n = iommu_area_alloc(iommu->map, limit, start, npages, shift,
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boundary_size, align_mask);
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if (n == -1) {
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if (likely(pass == 0)) {
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/* First failure, rescan from the beginning. */
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pool->hint = pool->start;
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set_flush(iommu);
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pass++;
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goto again;
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} else if (!largealloc && pass <= iommu->nr_pools) {
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spin_unlock(&(pool->lock));
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pool_nr = (pool_nr + 1) & (iommu->nr_pools - 1);
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pool = &(iommu->pools[pool_nr]);
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spin_lock(&(pool->lock));
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pool->hint = pool->start;
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set_flush(iommu);
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pass++;
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goto again;
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} else {
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/* give up */
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n = DMA_ERROR_CODE;
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goto bail;
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}
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}
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if (n < pool->hint || need_flush(iommu)) {
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clear_flush(iommu);
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iommu->lazy_flush(iommu);
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}
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end = n + npages;
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pool->hint = end;
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/* Update handle for SG allocations */
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if (handle)
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*handle = end;
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bail:
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spin_unlock_irqrestore(&(pool->lock), flags);
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return n;
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}
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EXPORT_SYMBOL(iommu_tbl_range_alloc);
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static struct iommu_pool *get_pool(struct iommu_map_table *tbl,
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unsigned long entry)
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{
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struct iommu_pool *p;
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unsigned long largepool_start = tbl->large_pool.start;
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bool large_pool = ((tbl->flags & IOMMU_HAS_LARGE_POOL) != 0);
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/* The large pool is the last pool at the top of the table */
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if (large_pool && entry >= largepool_start) {
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p = &tbl->large_pool;
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} else {
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unsigned int pool_nr = entry / tbl->poolsize;
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BUG_ON(pool_nr >= tbl->nr_pools);
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p = &tbl->pools[pool_nr];
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}
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return p;
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}
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/* Caller supplies the index of the entry into the iommu map table
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* itself when the mapping from dma_addr to the entry is not the
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* default addr->entry mapping below.
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*/
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void iommu_tbl_range_free(struct iommu_map_table *iommu, u64 dma_addr,
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unsigned long npages, unsigned long entry)
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{
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struct iommu_pool *pool;
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unsigned long flags;
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unsigned long shift = iommu->table_shift;
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if (entry == DMA_ERROR_CODE) /* use default addr->entry mapping */
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entry = (dma_addr - iommu->table_map_base) >> shift;
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pool = get_pool(iommu, entry);
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spin_lock_irqsave(&(pool->lock), flags);
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bitmap_clear(iommu->map, entry, npages);
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spin_unlock_irqrestore(&(pool->lock), flags);
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}
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EXPORT_SYMBOL(iommu_tbl_range_free);
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