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perf vendor events amd: Use lowercases for all the eventcodes and umasks 

The values of event codes and umasks are inconsistent with letter cases.
Enforce a unique style and default everything to lower case as this
helps in tracking changes of automatically generated event tables.

Reviewed-by: Robert Richter <rrichter@amd.com>
Signed-off-by: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Ian Rogers <irogers@google.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Kim Phillips <kim.phillips@amd.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Martin Liška <mliska@suse.cz>
Cc: Michael Petlan <mpetlan@redhat.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Vijay Thakkar <vijaythakkar@me.com>
Cc: linux-perf-users@vger.kernel.org
Link: https://lore.kernel.org/r/20210406215944.113332-3-Smita.KoralahalliChannabasappa@amd.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
Smita Koralahalli 2021-04-06 16:59:42 -05:00 committed by Arnaldo Carvalho de Melo
parent 86c2bc3da7
commit ff64c98195
3 changed files with 10 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
tools/perf/pmu-events/arch/x86/amdzen2/branch.json
View File

@ -24,7 +24,7 @@
"EventName": "bp_l1_tlb_fetch_hit",
"EventCode": "0x94",
"BriefDescription": "The number of instruction fetches that hit in the L1 ITLB.",
"UMask": "0xFF"
"UMask": "0xff"
},
{
"EventName": "bp_l1_tlb_fetch_hit.if1g",

2
tools/perf/pmu-events/arch/x86/amdzen2/cache.json
View File

@ -353,7 +353,7 @@
},
{
"EventName": "xi_ccx_sdp_req1.all_l3_miss_req_typs",
"EventCode": "0x9A",
"EventCode": "0x9a",
"BriefDescription": "All L3 Miss Request Types. Ignores SliceMask and ThreadMask.",
"UMask": "0x3f",
"Unit": "L3PMC"

16
tools/perf/pmu-events/arch/x86/amdzen2/memory.json
View File

@ -60,17 +60,17 @@
},
{
"EventName": "ls_smi_rx",
"EventCode": "0x2B",
"EventCode": "0x2b",
"BriefDescription": "Number of SMIs received."
},
{
"EventName": "ls_int_taken",
"EventCode": "0x2C",
"EventCode": "0x2c",
"BriefDescription": "Number of interrupts taken."
},
{
"EventName": "ls_rdtsc",
"EventCode": "0x2D",
"EventCode": "0x2d",
"BriefDescription": "Number of reads of the TSC (RDTSC instructions). The count is speculative."
},
{
@ -300,31 +300,31 @@
},
{
"EventName": "ls_hw_pf_dc_fill.ls_mabresp_rmt_dram",
"EventCode": "0x5A",
"EventCode": "0x5a",
"BriefDescription": "Hardware Prefetch Data Cache Fills by Data Source. From DRAM (home node remote).",
"UMask": "0x40"
},
{
"EventName": "ls_hw_pf_dc_fill.ls_mabresp_rmt_cache",
"EventCode": "0x5A",
"EventCode": "0x5a",
"BriefDescription": "Hardware Prefetch Data Cache Fills by Data Source. From another cache (home node remote).",
"UMask": "0x10"
},
{
"EventName": "ls_hw_pf_dc_fill.ls_mabresp_lcl_dram",
"EventCode": "0x5A",
"EventCode": "0x5a",
"BriefDescription": "Hardware Prefetch Data Cache Fills by Data Source. From DRAM (home node local).",
"UMask": "0x8"
},
{
"EventName": "ls_hw_pf_dc_fill.ls_mabresp_lcl_cache",
"EventCode": "0x5A",
"EventCode": "0x5a",
"BriefDescription": "Hardware Prefetch Data Cache Fills by Data Source. From another cache (home node local).",
"UMask": "0x2"
},
{
"EventName": "ls_hw_pf_dc_fill.ls_mabresp_lcl_l2",
"EventCode": "0x5A",
"EventCode": "0x5a",
"BriefDescription": "Hardware Prefetch Data Cache Fills by Data Source. Local L2 hit.",
"UMask": "0x1"
},