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clk: sunxi: Let divs clocks read the base factor clock name from devicetree 

Currently, the sunxi clock driver gets the name for the base factor clock
of divs clocks from the name field in factors_data. This prevents reusing
of the factor clock for clocks with same properties, but different name.

This commit makes the divs setup function try to get a name from
clock-output-names in the devicetree. It also removes the name field where
possible and merges the sun4i PLL5 and PLL6 clocks.

[Andre: Make temporary name allocation dynamic.]

Signed-off-by: Jens Kuske <jenskuske@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This commit is contained in:
Jens Kuske 2016-03-18 09:44:15 +00:00 committed by Maxime Ripard
parent cc510c736b
commit ff2bb89335
1 changed files with 30 additions and 11 deletions
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41
drivers/clk/sunxi/clk-sunxi.c
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@ -523,21 +523,12 @@ static const struct factors_data sun4i_pll5_data __initconst = {
.enable = 31, .enable = 31,
.table = &sun4i_pll5_config, .table = &sun4i_pll5_config,
.getter = sun4i_get_pll5_factors, .getter = sun4i_get_pll5_factors,
.name = "pll5",
};
static const struct factors_data sun4i_pll6_data __initconst = {
.enable = 31,
.table = &sun4i_pll5_config,
.getter = sun4i_get_pll5_factors,
.name = "pll6",
}; };
static const struct factors_data sun6i_a31_pll6_data __initconst = { static const struct factors_data sun6i_a31_pll6_data __initconst = {
.enable = 31, .enable = 31,
.table = &sun6i_a31_pll6_config, .table = &sun6i_a31_pll6_config,
.getter = sun6i_a31_get_pll6_factors, .getter = sun6i_a31_get_pll6_factors,
.name = "pll6x2",
}; };
static const struct factors_data sun5i_a13_ahb_data __initconst = { static const struct factors_data sun5i_a13_ahb_data __initconst = {
@ -933,7 +924,7 @@ static const struct divs_data pll5_divs_data __initconst = {
}; };
static const struct divs_data pll6_divs_data __initconst = { static const struct divs_data pll6_divs_data __initconst = {
.factors = &sun4i_pll6_data, .factors = &sun4i_pll5_data,
.ndivs = 4, .ndivs = 4,
.div = { .div = {
{ .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */ { .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */
@ -975,6 +966,8 @@ static struct clk ** __init sunxi_divs_clk_setup(struct device_node *node,
struct clk_gate *gate = NULL; struct clk_gate *gate = NULL;
struct clk_fixed_factor *fix_factor; struct clk_fixed_factor *fix_factor;
struct clk_divider *divider; struct clk_divider *divider;
struct factors_data factors = *data->factors;
char *derived_name = NULL;
void __iomem *reg; void __iomem *reg;
int ndivs = SUNXI_DIVS_MAX_QTY, i = 0; int ndivs = SUNXI_DIVS_MAX_QTY, i = 0;
int flags, clkflags; int flags, clkflags;
@ -983,11 +976,37 @@ static struct clk ** __init sunxi_divs_clk_setup(struct device_node *node,
if (data->ndivs) if (data->ndivs)
ndivs = data->ndivs; ndivs = data->ndivs;
/* Try to find a name for base factor clock */
for (i = 0; i < ndivs; i++) {
if (data->div[i].self) {
of_property_read_string_index(node, "clock-output-names",
i, &factors.name);
break;
}
}
/* If we don't have a .self clk use the first output-name up to '_' */
if (factors.name == NULL) {
char *endp;
of_property_read_string_index(node, "clock-output-names",
0, &clk_name);
endp = strchr(clk_name, '_');
if (endp) {
derived_name = kstrndup(clk_name, endp - clk_name,
GFP_KERNEL);
factors.name = derived_name;
} else {
factors.name = clk_name;
}
}
/* Set up factor clock that we will be dividing */ /* Set up factor clock that we will be dividing */
pclk = sunxi_factors_clk_setup(node, data->factors); pclk = sunxi_factors_clk_setup(node, &factors);
if (!pclk) if (!pclk)
return NULL; return NULL;
parent = __clk_get_name(pclk); parent = __clk_get_name(pclk);
kfree(derived_name);
reg = of_iomap(node, 0); reg = of_iomap(node, 0);
if (!reg) { if (!reg) {