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drm/i915/icl: Correctly clear lost ctx-switch interrupts across reset for Gen11 

Interrupt handling in Gen11 is quite different from previous platforms.

v2: Rebased (Michel)
v3: Rebased with wiggle
v4: Rebased, remove TODO warning correctly (Daniele)
v5: Rebased, made gen11_gtiir const while at it (Michel)
v6: Rebased
v7: Adapt to the style currently in upstream

Suggested-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/1524605995-22324-1-git-send-email-oscar.mateo@intel.com
This commit is contained in:
Oscar Mateo 2018-04-24 14:39:55 -07:00 committed by Chris Wilson
parent f6f109155f
commit ff047a87cf
3 changed files with 48 additions and 21 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
drivers/gpu/drm/i915/i915_irq.c
View File

@ -247,9 +247,9 @@ static u32
gen11_gt_engine_identity(struct drm_i915_private * const i915, gen11_gt_engine_identity(struct drm_i915_private * const i915,
const unsigned int bank, const unsigned int bit); const unsigned int bank, const unsigned int bit);
static bool gen11_reset_one_iir(struct drm_i915_private * const i915, bool gen11_reset_one_iir(struct drm_i915_private * const i915,
const unsigned int bank, const unsigned int bank,
const unsigned int bit) const unsigned int bit)
{ {
void __iomem * const regs = i915->regs; void __iomem * const regs = i915->regs;
u32 dw; u32 dw;

3
drivers/gpu/drm/i915/intel_drv.h
View File

@ -1333,6 +1333,9 @@ void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv); void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
/* i915_irq.c */ /* i915_irq.c */
bool gen11_reset_one_iir(struct drm_i915_private * const i915,
const unsigned int bank,
const unsigned int bit);
void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask); void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);

60
drivers/gpu/drm/i915/intel_lrc.c
View File

@ -789,22 +789,9 @@ execlists_cancel_port_requests(struct intel_engine_execlists * const execlists)
static void clear_gtiir(struct intel_engine_cs *engine) static void clear_gtiir(struct intel_engine_cs *engine)
{ {
static const u8 gtiir[] = {
[RCS] = 0,
[BCS] = 0,
[VCS] = 1,
[VCS2] = 1,
[VECS] = 3,
};
struct drm_i915_private *dev_priv = engine->i915; struct drm_i915_private *dev_priv = engine->i915;
int i; int i;
/* TODO: correctly reset irqs for gen11 */
if (WARN_ON_ONCE(INTEL_GEN(engine->i915) >= 11))
return;
GEM_BUG_ON(engine->id >= ARRAY_SIZE(gtiir));
/* /*
* Clear any pending interrupt state. * Clear any pending interrupt state.
* *
@ -812,13 +799,50 @@ static void clear_gtiir(struct intel_engine_cs *engine)
* double buffered, and so if we only reset it once there may * double buffered, and so if we only reset it once there may
* still be an interrupt pending. * still be an interrupt pending.
*/ */
for (i = 0; i < 2; i++) { if (INTEL_GEN(dev_priv) >= 11) {
I915_WRITE(GEN8_GT_IIR(gtiir[engine->id]), static const struct {
u8 bank;
u8 bit;
} gen11_gtiir[] = {
[RCS] = {0, GEN11_RCS0},
[BCS] = {0, GEN11_BCS},
[_VCS(0)] = {1, GEN11_VCS(0)},
[_VCS(1)] = {1, GEN11_VCS(1)},
[_VCS(2)] = {1, GEN11_VCS(2)},
[_VCS(3)] = {1, GEN11_VCS(3)},
[_VECS(0)] = {1, GEN11_VECS(0)},
[_VECS(1)] = {1, GEN11_VECS(1)},
};
unsigned long irqflags;
GEM_BUG_ON(engine->id >= ARRAY_SIZE(gen11_gtiir));
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
for (i = 0; i < 2; i++) {
gen11_reset_one_iir(dev_priv,
gen11_gtiir[engine->id].bank,
gen11_gtiir[engine->id].bit);
}
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
} else {
static const u8 gtiir[] = {
[RCS] = 0,
[BCS] = 0,
[VCS] = 1,
[VCS2] = 1,
[VECS] = 3,
};
GEM_BUG_ON(engine->id >= ARRAY_SIZE(gtiir));
for (i = 0; i < 2; i++) {
I915_WRITE(GEN8_GT_IIR(gtiir[engine->id]),
engine->irq_keep_mask);
POSTING_READ(GEN8_GT_IIR(gtiir[engine->id]));
}
GEM_BUG_ON(I915_READ(GEN8_GT_IIR(gtiir[engine->id])) &
engine->irq_keep_mask); engine->irq_keep_mask);
POSTING_READ(GEN8_GT_IIR(gtiir[engine->id]));
} }
GEM_BUG_ON(I915_READ(GEN8_GT_IIR(gtiir[engine->id])) &
engine->irq_keep_mask);
} }
static void reset_irq(struct intel_engine_cs *engine) static void reset_irq(struct intel_engine_cs *engine)