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Drop legacy platform data omap variants for v5.4 

We can now drop more platform data in favor of dts data for most
 devices like cpsw, gpio, i2c, mmc, uart and watchdog.
 
 In general we can do this by dropping legacy "ti,hwmods" custom dts
 property, and the platform data assuming the related dts data is correct.
 This is best done as single patch as otherwise we'd have to revert two
 patches in case of any unexpected issues, and we're just removing data.
 
 Fro cpsw, before we can do this, we need to configure the cpsw mdio clocks
 properly in dts though in the first patch. For omap4 i2c, we've already
 dropped the platform data earlier, but have been still allocting it
 dynamically based on the dts data based on the "ti,hwmods" property, but
 that is no longer needed. For d2d, we are missing the dts data, so we
 first add it and then drop the platform data.
 
 For dra7, we drop platform data and "ti,hwmods" for mcasp and mcspi.
 We've already dropped platform data earlier for gpio, i2c, mmc, and
 uart so we just need to drop "ti,hwmods" property for those.
 
 Note that this branch is based on earlier ti-sysc-fixes branch.
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Merge tag 'omap-for-v5.4/ti-sysc-drop-pdata-take2-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/late

Drop legacy platform data omap variants for v5.4

We can now drop more platform data in favor of dts data for most
devices like cpsw, gpio, i2c, mmc, uart and watchdog.

In general we can do this by dropping legacy "ti,hwmods" custom dts
property, and the platform data assuming the related dts data is correct.
This is best done as single patch as otherwise we'd have to revert two
patches in case of any unexpected issues, and we're just removing data.

Fro cpsw, before we can do this, we need to configure the cpsw mdio clocks
properly in dts though in the first patch. For omap4 i2c, we've already
dropped the platform data earlier, but have been still allocting it
dynamically based on the dts data based on the "ti,hwmods" property, but
that is no longer needed. For d2d, we are missing the dts data, so we
first add it and then drop the platform data.

For dra7, we drop platform data and "ti,hwmods" for mcasp and mcspi.
We've already dropped platform data earlier for gpio, i2c, mmc, and
uart so we just need to drop "ti,hwmods" property for those.

Note that this branch is based on earlier ti-sysc-fixes branch.

* tag 'omap-for-v5.4/ti-sysc-drop-pdata-take2-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: dts: Drop legacy custom hwmods property for dra7 gpio
  ARM: dts: Drop legacy custom hwmods property for dra7 mmc
  ARM: dts: Drop legacy custom hwmods property for dra7 i2c
  ARM: dts: Drop legacy custom hwmods property for dra7 uart
  ARM: OMAP2+: Drop legacy platform data for dra7 mcasp
  ARM: OMAP2+: Drop legacy platform data for dra7 mcspi
  ARM: OMAP2+: Drop legacy platform data for omap4 d2d
  ARM: dts: Configure d2d dts data for omap4
  ARM: OMAP2+: Drop legacy watchdog platform data for omap4
  ARM: dts: Drop custom hwmod property for omap4 i2c
  ARM: OMAP2+: Drop legacy platform data for cpsw on dra7
  ARM: OMAP2+: Drop legacy platform data for cpsw on am3 and am4
  ARM: dts: Add fck for cpsw mdio for omap variants

Link: https://lore.kernel.org/r/pull-1567016893-318461@atomide.com-3
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2019-09-04 17:21:30 +02:00
parent 30d8bb9003 1170f23583
commit feeb04ce91
12 changed files with 36 additions and 724 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm/boot/dts/am33xx-l4.dtsi
View File

@ -673,7 +673,6 @@
target-module@100000 { /* 0x4a100000, ap 3 08.0 */
compatible = "ti,sysc-omap4-simple", "ti,sysc";
ti,hwmods = "cpgmac0";
reg = <0x101200 0x4>,
<0x101208 0x4>,
<0x101204 0x4>;
@ -719,9 +718,10 @@
davinci_mdio: mdio@1000 {
compatible = "ti,cpsw-mdio","ti,davinci_mdio";
clocks = <&cpsw_125mhz_clkctrl AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "davinci_mdio";
bus_freq = <1000000>;
reg = <0x1000 0x100>;
status = "disabled";

6
arch/arm/boot/dts/am437x-l4.dtsi
View File

@ -512,7 +512,6 @@
target-module@100000 { /* 0x4a100000, ap 3 04.0 */
compatible = "ti,sysc-omap4-simple", "ti,sysc";
ti,hwmods = "cpgmac0";
reg = <0x101200 0x4>,
<0x101208 0x4>,
<0x101204 0x4>;
@ -559,11 +558,10 @@
davinci_mdio: mdio@1000 {
compatible = "ti,am4372-mdio","ti,cpsw-mdio","ti,davinci_mdio";
reg = <0x1000 0x100>;
clocks = <&cpsw_125mhz_clkctrl AM4_CPSW_125MHZ_CPGMAC0_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&cpsw_125mhz_gclk>;
clock-names = "fck";
ti,hwmods = "davinci_mdio";
bus_freq = <1000000>;
status = "disabled";
};

43
arch/arm/boot/dts/dra7-l4.dtsi
View File

@ -1118,7 +1118,6 @@
target-module@20000 { /* 0x48020000, ap 3 04.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "uart3";
reg = <0x20050 0x4>,
<0x20054 0x4>,
<0x20058 0x4>;
@ -1263,7 +1262,6 @@
gpio7_target: target-module@51000 { /* 0x48051000, ap 45 2e.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "gpio7";
reg = <0x51000 0x4>,
<0x51010 0x4>,
<0x51114 0x4>;
@ -1297,7 +1295,6 @@
target-module@53000 { /* 0x48053000, ap 35 36.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "gpio8";
reg = <0x53000 0x4>,
<0x53010 0x4>,
<0x53114 0x4>;
@ -1331,7 +1328,6 @@
target-module@55000 { /* 0x48055000, ap 13 0e.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "gpio2";
reg = <0x55000 0x4>,
<0x55010 0x4>,
<0x55114 0x4>;
@ -1365,7 +1361,6 @@
target-module@57000 { /* 0x48057000, ap 15 06.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "gpio3";
reg = <0x57000 0x4>,
<0x57010 0x4>,
<0x57114 0x4>;
@ -1399,7 +1394,6 @@
target-module@59000 { /* 0x48059000, ap 17 16.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "gpio4";
reg = <0x59000 0x4>,
<0x59010 0x4>,
<0x59114 0x4>;
@ -1433,7 +1427,6 @@
target-module@5b000 { /* 0x4805b000, ap 19 1e.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "gpio5";
reg = <0x5b000 0x4>,
<0x5b010 0x4>,
<0x5b114 0x4>;
@ -1467,7 +1460,6 @@
target-module@5d000 { /* 0x4805d000, ap 21 26.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "gpio6";
reg = <0x5d000 0x4>,
<0x5d010 0x4>,
<0x5d114 0x4>;
@ -1501,7 +1493,6 @@
target-module@60000 { /* 0x48060000, ap 23 32.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "i2c3";
reg = <0x60000 0x8>,
<0x60010 0x8>,
<0x60090 0x8>;
@ -1534,7 +1525,6 @@
target-module@66000 { /* 0x48066000, ap 63 14.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "uart5";
reg = <0x66050 0x4>,
<0x66054 0x4>,
<0x66058 0x4>;
@ -1567,7 +1557,6 @@
target-module@68000 { /* 0x48068000, ap 53 1c.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "uart6";
reg = <0x68050 0x4>,
<0x68054 0x4>,
<0x68058 0x4>;
@ -1600,7 +1589,6 @@
target-module@6a000 { /* 0x4806a000, ap 24 24.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "uart1";
reg = <0x6a050 0x4>,
<0x6a054 0x4>,
<0x6a058 0x4>;
@ -1633,7 +1621,6 @@
target-module@6c000 { /* 0x4806c000, ap 26 2c.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "uart2";
reg = <0x6c050 0x4>,
<0x6c054 0x4>,
<0x6c058 0x4>;
@ -1666,7 +1653,6 @@
target-module@6e000 { /* 0x4806e000, ap 28 0c.1 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "uart4";
reg = <0x6e050 0x4>,
<0x6e054 0x4>,
<0x6e058 0x4>;
@ -1699,7 +1685,6 @@
target-module@70000 { /* 0x48070000, ap 30 22.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "i2c1";
reg = <0x70000 0x8>,
<0x70010 0x8>,
<0x70090 0x8>;
@ -1732,7 +1717,6 @@
target-module@72000 { /* 0x48072000, ap 32 2a.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "i2c2";
reg = <0x72000 0x8>,
<0x72010 0x8>,
<0x72090 0x8>;
@ -1795,7 +1779,6 @@
target-module@7a000 { /* 0x4807a000, ap 81 3a.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "i2c4";
reg = <0x7a000 0x8>,
<0x7a010 0x8>,
<0x7a090 0x8>;
@ -1828,7 +1811,6 @@
target-module@7c000 { /* 0x4807c000, ap 83 4a.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "i2c5";
reg = <0x7c000 0x8>,
<0x7c010 0x8>,
<0x7c090 0x8>;
@ -1942,7 +1924,6 @@
target-module@98000 { /* 0x48098000, ap 47 08.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "mcspi1";
reg = <0x98000 0x4>,
<0x98010 0x4>;
reg-names = "rev", "sysc";
@ -1982,7 +1963,6 @@
target-module@9a000 { /* 0x4809a000, ap 49 10.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "mcspi2";
reg = <0x9a000 0x4>,
<0x9a010 0x4>;
reg-names = "rev", "sysc";
@ -2017,7 +1997,6 @@
target-module@9c000 { /* 0x4809c000, ap 51 38.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "mmc1";
reg = <0x9c000 0x4>,
<0x9c010 0x4>;
reg-names = "rev", "sysc";
@ -2077,7 +2056,6 @@
target-module@ad000 { /* 0x480ad000, ap 61 20.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "mmc3";
reg = <0xad000 0x4>,
<0xad010 0x4>;
reg-names = "rev", "sysc";
@ -2137,7 +2115,6 @@
target-module@b4000 { /* 0x480b4000, ap 65 40.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "mmc2";
reg = <0xb4000 0x4>,
<0xb4010 0x4>;
reg-names = "rev", "sysc";
@ -2174,7 +2151,6 @@
target-module@b8000 { /* 0x480b8000, ap 67 48.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "mcspi3";
reg = <0xb8000 0x4>,
<0xb8010 0x4>;
reg-names = "rev", "sysc";
@ -2206,7 +2182,6 @@
target-module@ba000 { /* 0x480ba000, ap 69 18.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "mcspi4";
reg = <0xba000 0x4>,
<0xba010 0x4>;
reg-names = "rev", "sysc";
@ -2238,7 +2213,6 @@
target-module@d1000 { /* 0x480d1000, ap 71 28.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "mmc4";
reg = <0xd1000 0x4>,
<0xd1010 0x4>;
reg-names = "rev", "sysc";
@ -2384,7 +2358,6 @@
target-module@20000 { /* 0x48420000, ap 47 02.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "uart7";
reg = <0x20050 0x4>,
<0x20054 0x4>,
<0x20058 0x4>;
@ -2415,7 +2388,6 @@
target-module@22000 { /* 0x48422000, ap 49 0a.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "uart8";
reg = <0x22050 0x4>,
<0x22054 0x4>,
<0x22058 0x4>;
@ -2446,7 +2418,6 @@
target-module@24000 { /* 0x48424000, ap 51 12.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "uart9";
reg = <0x24050 0x4>,
<0x24054 0x4>,
<0x24058 0x4>;
@ -2735,7 +2706,6 @@
target-module@60000 { /* 0x48460000, ap 9 0e.0 */
compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
ti,hwmods = "mcasp1";
reg = <0x60000 0x4>,
<0x60004 0x4>;
reg-names = "rev", "sysc";
@ -2772,7 +2742,6 @@
target-module@64000 { /* 0x48464000, ap 11 1e.0 */
compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
ti,hwmods = "mcasp2";
reg = <0x64000 0x4>,
<0x64004 0x4>;
reg-names = "rev", "sysc";
@ -2809,7 +2778,6 @@
target-module@68000 { /* 0x48468000, ap 13 26.0 */
compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
ti,hwmods = "mcasp3";
reg = <0x68000 0x4>,
<0x68004 0x4>;
reg-names = "rev", "sysc";
@ -2845,7 +2813,6 @@
target-module@6c000 { /* 0x4846c000, ap 15 2e.0 */
compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
ti,hwmods = "mcasp4";
reg = <0x6c000 0x4>,
<0x6c004 0x4>;
reg-names = "rev", "sysc";
@ -2881,7 +2848,6 @@
target-module@70000 { /* 0x48470000, ap 19 36.0 */
compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
ti,hwmods = "mcasp5";
reg = <0x70000 0x4>,
<0x70004 0x4>;
reg-names = "rev", "sysc";
@ -2917,7 +2883,6 @@
target-module@74000 { /* 0x48474000, ap 35 14.0 */
compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
ti,hwmods = "mcasp6";
reg = <0x74000 0x4>,
<0x74004 0x4>;
reg-names = "rev", "sysc";
@ -2953,7 +2918,6 @@
target-module@78000 { /* 0x48478000, ap 39 0c.0 */
compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
ti,hwmods = "mcasp7";
reg = <0x78000 0x4>,
<0x78004 0x4>;
reg-names = "rev", "sysc";
@ -2989,7 +2953,6 @@
target-module@7c000 { /* 0x4847c000, ap 43 04.0 */
compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
ti,hwmods = "mcasp8";
reg = <0x7c000 0x4>,
<0x7c004 0x4>;
reg-names = "rev", "sysc";
@ -3045,7 +3008,6 @@
target-module@84000 { /* 0x48484000, ap 3 10.0 */
compatible = "ti,sysc-omap4-simple", "ti,sysc";
ti,hwmods = "gmac";
reg = <0x85200 0x4>,
<0x85208 0x4>,
<0x85204 0x4>;
@ -3103,9 +3065,10 @@
davinci_mdio: mdio@1000 {
compatible = "ti,cpsw-mdio","ti,davinci_mdio";
clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "davinci_mdio";
bus_freq = <1000000>;
reg = <0x1000 0x100>;
};
@ -4311,7 +4274,6 @@
target-module@0 { /* 0x4ae10000, ap 5 20.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "gpio1";
reg = <0x0 0x4>,
<0x10 0x4>,
<0x114 0x4>;
@ -4479,7 +4441,6 @@
target-module@b000 { /* 0x4ae2b000, ap 28 02.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "uart10";
reg = <0xb050 0x4>,
<0xb054 0x4>,
<0xb058 0x4>;

1
arch/arm/boot/dts/omap4-l4-abe.dtsi
View File

@ -255,7 +255,6 @@
target-module@30000 { /* 0x40130000, ap 14 0e.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "wd_timer3";
reg = <0x30000 0x4>,
<0x30010 0x4>,
<0x30014 0x4>;

39
arch/arm/boot/dts/omap4-l4.dtsi
View File

@ -456,17 +456,43 @@
};
};
/* d2d mdm */
target-module@36000 { /* 0x4a0b6000, ap 69 60.0 */
compatible = "ti,sysc";
status = "disabled";
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x36000 0x4>,
<0x36010 0x4>,
<0x36014 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
ti,syss-mask = <1>;
/* Domains (V, P, C): core, core_pwrdm, d2d_clkdm */
clocks = <&d2d_clkctrl OMAP4_C2C_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x36000 0x1000>;
};
/* d2d mpu */
target-module@4d000 { /* 0x4a0cd000, ap 78 58.0 */
compatible = "ti,sysc";
status = "disabled";
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x4d000 0x4>,
<0x4d010 0x4>,
<0x4d014 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
ti,syss-mask = <1>;
/* Domains (V, P, C): core, core_pwrdm, d2d_clkdm */
clocks = <&d2d_clkctrl OMAP4_C2C_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x4d000 0x1000>;
@ -1094,7 +1120,6 @@
target-module@4000 { /* 0x4a314000, ap 7 18.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "wd_timer2";
reg = <0x4000 0x4>,
<0x4010 0x4>,
<0x4014 0x4>;
@ -1695,7 +1720,6 @@
target-module@60000 { /* 0x48060000, ap 25 1e.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "i2c3";
reg = <0x60000 0x8>,
<0x60010 0x8>,
<0x60090 0x8>;
@ -1814,7 +1838,6 @@
target-module@70000 { /* 0x48070000, ap 32 28.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "i2c1";
reg = <0x70000 0x8>,
<0x70010 0x8>,
<0x70090 0x8>;
@ -1846,7 +1869,6 @@
target-module@72000 { /* 0x48072000, ap 34 30.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "i2c2";
reg = <0x72000 0x8>,
<0x72010 0x8>,
<0x72090 0x8>;
@ -2401,7 +2423,6 @@
target-module@150000 { /* 0x48350000, ap 77 4c.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "i2c4";
reg = <0x150000 0x8>,
<0x150010 0x8>,
<0x150090 0x8>;

3
arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h
View File

@ -30,7 +30,6 @@ extern struct omap_hwmod_ocp_if am33xx_l3_main__gfx;
extern struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc;
extern struct omap_hwmod_ocp_if am33xx_l4_per__dcan0;
extern struct omap_hwmod_ocp_if am33xx_l4_per__dcan1;
extern struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio;
extern struct omap_hwmod_ocp_if am33xx_l4_ls__elm;
extern struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0;
extern struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1;
@ -72,8 +71,6 @@ extern struct omap_hwmod am33xx_rng_hwmod;
extern struct omap_hwmod am33xx_ocmcram_hwmod;
extern struct omap_hwmod am33xx_smartreflex0_hwmod;
extern struct omap_hwmod am33xx_smartreflex1_hwmod;
extern struct omap_hwmod am33xx_cpgmac0_hwmod;
extern struct omap_hwmod am33xx_mdio_hwmod;
extern struct omap_hwmod am33xx_dcan0_hwmod;
extern struct omap_hwmod am33xx_dcan1_hwmod;
extern struct omap_hwmod am33xx_elm_hwmod;

6
arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c
View File

@ -122,12 +122,6 @@ struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = {
.master = &am33xx_cpgmac0_hwmod,
.slave = &am33xx_mdio_hwmod,
.user = OCP_USER_MPU,
};
struct omap_hwmod_ocp_if am33xx_l4_ls__elm = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_elm_hwmod,

50
arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c
View File

@ -349,54 +349,6 @@ struct omap_hwmod_class am33xx_control_hwmod_class = {
.name = "control",
};
/*
* 'cpgmac' class
* cpsw/cpgmac sub system
*/
static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = {
.rev_offs = 0x0,
.sysc_offs = 0x8,
.syss_offs = 0x4,
.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
SYSS_HAS_RESET_STATUS),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
MSTANDBY_NO),
.sysc_fields = &omap_hwmod_sysc_type3,
};
static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
.name = "cpgmac0",
.sysc = &am33xx_cpgmac_sysc,
};
struct omap_hwmod am33xx_cpgmac0_hwmod = {
.name = "cpgmac0",
.class = &am33xx_cpgmac0_hwmod_class,
.clkdm_name = "cpsw_125mhz_clkdm",
.flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
.main_clk = "cpsw_125mhz_gclk",
.mpu_rt_idx = 1,
.prcm = {
.omap4 = {
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/*
* mdio class
*/
static struct omap_hwmod_class am33xx_mdio_hwmod_class = {
.name = "davinci_mdio",
};
struct omap_hwmod am33xx_mdio_hwmod = {
.name = "davinci_mdio",
.class = &am33xx_mdio_hwmod_class,
.clkdm_name = "cpsw_125mhz_clkdm",
.main_clk = "cpsw_125mhz_gclk",
};
/*
* dcan class
*/
@ -1072,7 +1024,6 @@ static void omap_hwmod_am33xx_clkctrl(void)
CLKCTRL(am33xx_tptc1_hwmod, AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
CLKCTRL(am33xx_tptc2_hwmod, AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
CLKCTRL(am33xx_gfx_hwmod, AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET);
CLKCTRL(am33xx_cpgmac0_hwmod, AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET);
CLKCTRL(am33xx_pruss_hwmod, AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
CLKCTRL(am33xx_mpu_hwmod , AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET);
CLKCTRL(am33xx_l3_instr_hwmod , AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
@ -1134,7 +1085,6 @@ static void omap_hwmod_am43xx_clkctrl(void)
CLKCTRL(am33xx_tptc1_hwmod, AM43XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
CLKCTRL(am33xx_tptc2_hwmod, AM43XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
CLKCTRL(am33xx_gfx_hwmod, AM43XX_CM_GFX_GFX_CLKCTRL_OFFSET);
CLKCTRL(am33xx_cpgmac0_hwmod, AM43XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET);
CLKCTRL(am33xx_pruss_hwmod, AM43XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
CLKCTRL(am33xx_mpu_hwmod , AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET);
CLKCTRL(am33xx_l3_instr_hwmod , AM43XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);

9
arch/arm/mach-omap2/omap_hwmod_33xx_data.c
View File

@ -372,13 +372,6 @@ static struct omap_hwmod_ocp_if am33xx_l4_wkup__adc_tsc = {
.user = OCP_USER_MPU,
};
static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = {
.master = &am33xx_l4_hs_hwmod,
.slave = &am33xx_cpgmac0_hwmod,
.clk = "cpsw_125mhz_gclk",
.user = OCP_USER_MPU,
};
static struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = {
.master = &am33xx_l3_main_hwmod,
.slave = &am33xx_lcdc_hwmod,
@ -462,8 +455,6 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
&am33xx_l3_main__tptc2,
&am33xx_l3_main__ocmc,
&am33xx_l3_s__usbss,
&am33xx_l4_hs__cpgmac0,
&am33xx_cpgmac0__mdio,
&am33xx_l3_main__sha0,
&am33xx_l3_main__aes0,
&am33xx_l4_per__rng,

9
arch/arm/mach-omap2/omap_hwmod_43xx_data.c
View File

@ -597,13 +597,6 @@ static struct omap_hwmod_ocp_if am43xx_l4_wkup__adc_tsc = {
.user = OCP_USER_MPU,
};
static struct omap_hwmod_ocp_if am43xx_l4_hs__cpgmac0 = {
.master = &am43xx_l4_hs_hwmod,
.slave = &am33xx_cpgmac0_hwmod,
.clk = "cpsw_125mhz_gclk",
.user = OCP_USER_MPU,
};
static struct omap_hwmod_ocp_if am43xx_l4_wkup__timer1 = {
.master = &am33xx_l4_wkup_hwmod,
.slave = &am33xx_timer1_hwmod,
@ -859,8 +852,6 @@ static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
&am33xx_l3_main__tptc1,
&am33xx_l3_main__tptc2,
&am33xx_l3_main__ocmc,
&am43xx_l4_hs__cpgmac0,
&am33xx_cpgmac0__mdio,
&am33xx_l3_main__sha0,
&am33xx_l3_main__aes0,
&am43xx_l3_main__des,

115
arch/arm/mach-omap2/omap_hwmod_44xx_data.c
View File

@ -28,7 +28,6 @@
#include "cm2_44xx.h"
#include "prm44xx.h"
#include "prm-regbits-44xx.h"
#include "wd_timer.h"
/* Base offset for all OMAP4 interrupts external to MPUSS */
#define OMAP44XX_IRQ_GIC_START 32
@ -275,29 +274,6 @@ static struct omap_hwmod omap44xx_aess_hwmod = {
},
};
/*
* 'c2c' class
* chip 2 chip interface used to plug the ape soc (omap) with an external modem
* soc
*/
static struct omap_hwmod_class omap44xx_c2c_hwmod_class = {
.name = "c2c",
};
/* c2c */
static struct omap_hwmod omap44xx_c2c_hwmod = {
.name = "c2c",
.class = &omap44xx_c2c_hwmod_class,
.clkdm_name = "d2d_clkdm",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET,
.context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET,
},
},
};
/*
* 'counter' class
* 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
@ -2433,61 +2409,6 @@ static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
},
};
/*
* 'wd_timer' class
* 32-bit watchdog upward counter that generates a pulse on the reset pin on
* overflow condition
*/
static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
SIDLE_SMART_WKUP),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
.name = "wd_timer",
.sysc = &omap44xx_wd_timer_sysc,
.pre_shutdown = &omap2_wd_timer_disable,
.reset = &omap2_wd_timer_reset,
};
/* wd_timer2 */
static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
.name = "wd_timer2",
.class = &omap44xx_wd_timer_hwmod_class,
.clkdm_name = "l4_wkup_clkdm",
.main_clk = "sys_32k_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
.context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/* wd_timer3 */
static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
.name = "wd_timer3",
.class = &omap44xx_wd_timer_hwmod_class,
.clkdm_name = "abe_clkdm",
.main_clk = "sys_32k_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
.context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/*
* interfaces
*/
@ -2788,14 +2709,6 @@ static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma = {
.user = OCP_USER_SDMA,
};
/* l3_main_2 -> c2c */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = {
.master = &omap44xx_l3_main_2_hwmod,
.slave = &omap44xx_c2c_hwmod,
.clk = "l3_div_ck",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_wkup -> counter_32k */
static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
.master = &omap44xx_l4_wkup_hwmod,
@ -3396,30 +3309,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_wkup -> wd_timer2 */
static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
.master = &omap44xx_l4_wkup_hwmod,
.slave = &omap44xx_wd_timer2_hwmod,
.clk = "l4_wkup_clk_mux_ck",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_abe -> wd_timer3 */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
.master = &omap44xx_l4_abe_hwmod,
.slave = &omap44xx_wd_timer3_hwmod,
.clk = "ocp_abe_iclk",
.user = OCP_USER_MPU,
};
/* l4_abe -> wd_timer3 (dma) */
static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
.master = &omap44xx_l4_abe_hwmod,
.slave = &omap44xx_wd_timer3_hwmod,
.clk = "ocp_abe_iclk",
.user = OCP_USER_SDMA,
};
/* mpu -> emif1 */
static struct omap_hwmod_ocp_if omap44xx_mpu__emif1 = {
.master = &omap44xx_mpu_hwmod,
@ -3474,7 +3363,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
&omap44xx_l4_cfg__ocp_wp_noc,
&omap44xx_l4_abe__aess,
&omap44xx_l4_abe__aess_dma,
&omap44xx_l3_main_2__c2c,
&omap44xx_l4_wkup__counter_32k,
&omap44xx_l4_cfg__ctrl_module_core,
&omap44xx_l4_cfg__ctrl_module_pad_core,
@ -3551,9 +3439,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
&omap44xx_l4_cfg__usb_host_hs,
&omap44xx_l4_cfg__usb_otg_hs,
&omap44xx_l4_cfg__usb_tll_hs,
&omap44xx_l4_wkup__wd_timer2,
&omap44xx_l4_abe__wd_timer3,
&omap44xx_l4_abe__wd_timer3_dma,
&omap44xx_mpu__emif1,
&omap44xx_mpu__emif2,
&omap44xx_l3_main_2__aes1,

475
arch/arm/mach-omap2/omap_hwmod_7xx_data.c
View File

@ -284,56 +284,6 @@ static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
},
};
/*
* 'gmac' class
* cpsw/gmac sub system
*/
static struct omap_hwmod_class_sysconfig dra7xx_gmac_sysc = {
.rev_offs = 0x0,
.sysc_offs = 0x8,
.syss_offs = 0x4,
.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
SYSS_HAS_RESET_STATUS),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
MSTANDBY_NO),
.sysc_fields = &omap_hwmod_sysc_type3,
};
static struct omap_hwmod_class dra7xx_gmac_hwmod_class = {
.name = "gmac",
.sysc = &dra7xx_gmac_sysc,
};
static struct omap_hwmod dra7xx_gmac_hwmod = {
.name = "gmac",
.class = &dra7xx_gmac_hwmod_class,
.clkdm_name = "gmac_clkdm",
.flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
.main_clk = "dpll_gmac_ck",
.mpu_rt_idx = 1,
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/*
* 'mdio' class
*/
static struct omap_hwmod_class dra7xx_mdio_hwmod_class = {
.name = "davinci_mdio",
};
static struct omap_hwmod dra7xx_mdio_hwmod = {
.name = "davinci_mdio",
.class = &dra7xx_mdio_hwmod_class,
.clkdm_name = "gmac_clkdm",
.main_clk = "dpll_gmac_ck",
};
/*
* 'dcan' class
*
@ -1046,281 +996,6 @@ static struct omap_hwmod dra7xx_mailbox13_hwmod = {
},
};
/*
* 'mcspi' class
*
*/
static struct omap_hwmod_class_sysconfig dra7xx_mcspi_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
SIDLE_SMART_WKUP),
.sysc_fields = &omap_hwmod_sysc_type2,
};
static struct omap_hwmod_class dra7xx_mcspi_hwmod_class = {
.name = "mcspi",
.sysc = &dra7xx_mcspi_sysc,
};
/* mcspi1 */
static struct omap_hwmod dra7xx_mcspi1_hwmod = {
.name = "mcspi1",
.class = &dra7xx_mcspi_hwmod_class,
.clkdm_name = "l4per_clkdm",
.main_clk = "func_48m_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/* mcspi2 */
static struct omap_hwmod dra7xx_mcspi2_hwmod = {
.name = "mcspi2",
.class = &dra7xx_mcspi_hwmod_class,
.clkdm_name = "l4per_clkdm",
.main_clk = "func_48m_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/* mcspi3 */
static struct omap_hwmod dra7xx_mcspi3_hwmod = {
.name = "mcspi3",
.class = &dra7xx_mcspi_hwmod_class,
.clkdm_name = "l4per_clkdm",
.main_clk = "func_48m_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/* mcspi4 */
static struct omap_hwmod dra7xx_mcspi4_hwmod = {
.name = "mcspi4",
.class = &dra7xx_mcspi_hwmod_class,
.clkdm_name = "l4per_clkdm",
.main_clk = "func_48m_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/*
* 'mcasp' class
*
*/
static struct omap_hwmod_class_sysconfig dra7xx_mcasp_sysc = {
.rev_offs = 0,
.sysc_offs = 0x0004,
.sysc_flags = SYSC_HAS_SIDLEMODE,
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type3,
};
static struct omap_hwmod_class dra7xx_mcasp_hwmod_class = {
.name = "mcasp",
.sysc = &dra7xx_mcasp_sysc,
};
/* mcasp1 */
static struct omap_hwmod_opt_clk mcasp1_opt_clks[] = {
{ .role = "ahclkx", .clk = "mcasp1_ahclkx_mux" },
{ .role = "ahclkr", .clk = "mcasp1_ahclkr_mux" },
};
static struct omap_hwmod dra7xx_mcasp1_hwmod = {
.name = "mcasp1",
.class = &dra7xx_mcasp_hwmod_class,
.clkdm_name = "ipu_clkdm",
.main_clk = "mcasp1_aux_gfclk_mux",
.flags = HWMOD_OPT_CLKS_NEEDED,
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_IPU_MCASP1_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_IPU_MCASP1_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
.opt_clks = mcasp1_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(mcasp1_opt_clks),
};
/* mcasp2 */
static struct omap_hwmod_opt_clk mcasp2_opt_clks[] = {
{ .role = "ahclkx", .clk = "mcasp2_ahclkx_mux" },
{ .role = "ahclkr", .clk = "mcasp2_ahclkr_mux" },
};
static struct omap_hwmod dra7xx_mcasp2_hwmod = {
.name = "mcasp2",
.class = &dra7xx_mcasp_hwmod_class,
.clkdm_name = "l4per2_clkdm",
.main_clk = "mcasp2_aux_gfclk_mux",
.flags = HWMOD_OPT_CLKS_NEEDED,
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP2_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_L4PER2_MCASP2_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
.opt_clks = mcasp2_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(mcasp2_opt_clks),
};
/* mcasp3 */
static struct omap_hwmod_opt_clk mcasp3_opt_clks[] = {
{ .role = "ahclkx", .clk = "mcasp3_ahclkx_mux" },
};
static struct omap_hwmod dra7xx_mcasp3_hwmod = {
.name = "mcasp3",
.class = &dra7xx_mcasp_hwmod_class,
.clkdm_name = "l4per2_clkdm",
.main_clk = "mcasp3_aux_gfclk_mux",
.flags = HWMOD_OPT_CLKS_NEEDED,
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP3_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_L4PER2_MCASP3_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
.opt_clks = mcasp3_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(mcasp3_opt_clks),
};
/* mcasp4 */
static struct omap_hwmod_opt_clk mcasp4_opt_clks[] = {
{ .role = "ahclkx", .clk = "mcasp4_ahclkx_mux" },
};
static struct omap_hwmod dra7xx_mcasp4_hwmod = {
.name = "mcasp4",
.class = &dra7xx_mcasp_hwmod_class,
.clkdm_name = "l4per2_clkdm",
.main_clk = "mcasp4_aux_gfclk_mux",
.flags = HWMOD_OPT_CLKS_NEEDED,
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP4_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_L4PER2_MCASP4_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
.opt_clks = mcasp4_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(mcasp4_opt_clks),
};
/* mcasp5 */
static struct omap_hwmod_opt_clk mcasp5_opt_clks[] = {
{ .role = "ahclkx", .clk = "mcasp5_ahclkx_mux" },
};
static struct omap_hwmod dra7xx_mcasp5_hwmod = {
.name = "mcasp5",
.class = &dra7xx_mcasp_hwmod_class,
.clkdm_name = "l4per2_clkdm",
.main_clk = "mcasp5_aux_gfclk_mux",
.flags = HWMOD_OPT_CLKS_NEEDED,
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP5_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_L4PER2_MCASP5_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
.opt_clks = mcasp5_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(mcasp5_opt_clks),
};
/* mcasp6 */
static struct omap_hwmod_opt_clk mcasp6_opt_clks[] = {
{ .role = "ahclkx", .clk = "mcasp6_ahclkx_mux" },
};
static struct omap_hwmod dra7xx_mcasp6_hwmod = {
.name = "mcasp6",
.class = &dra7xx_mcasp_hwmod_class,
.clkdm_name = "l4per2_clkdm",
.main_clk = "mcasp6_aux_gfclk_mux",
.flags = HWMOD_OPT_CLKS_NEEDED,
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP6_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_L4PER2_MCASP6_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
.opt_clks = mcasp6_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(mcasp6_opt_clks),
};
/* mcasp7 */
static struct omap_hwmod_opt_clk mcasp7_opt_clks[] = {
{ .role = "ahclkx", .clk = "mcasp7_ahclkx_mux" },
};
static struct omap_hwmod dra7xx_mcasp7_hwmod = {
.name = "mcasp7",
.class = &dra7xx_mcasp_hwmod_class,
.clkdm_name = "l4per2_clkdm",
.main_clk = "mcasp7_aux_gfclk_mux",
.flags = HWMOD_OPT_CLKS_NEEDED,
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP7_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_L4PER2_MCASP7_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
.opt_clks = mcasp7_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(mcasp7_opt_clks),
};
/* mcasp8 */
static struct omap_hwmod_opt_clk mcasp8_opt_clks[] = {
{ .role = "ahclkx", .clk = "mcasp8_ahclkx_mux" },
};
static struct omap_hwmod dra7xx_mcasp8_hwmod = {
.name = "mcasp8",
.class = &dra7xx_mcasp_hwmod_class,
.clkdm_name = "l4per2_clkdm",
.main_clk = "mcasp8_aux_gfclk_mux",
.flags = HWMOD_OPT_CLKS_NEEDED,
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP8_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_L4PER2_MCASP8_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
.opt_clks = mcasp8_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(mcasp8_opt_clks),
};
/*
* 'mpu' class
*
@ -2303,19 +1978,6 @@ static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_ocp_if dra7xx_l4_per2__cpgmac0 = {
.master = &dra7xx_l4_per2_hwmod,
.slave = &dra7xx_gmac_hwmod,
.clk = "dpll_gmac_ck",
.user = OCP_USER_MPU,
};
static struct omap_hwmod_ocp_if dra7xx_gmac__mdio = {
.master = &dra7xx_gmac_hwmod,
.slave = &dra7xx_mdio_hwmod,
.user = OCP_USER_MPU,
};
/* l4_wkup -> dcan1 */
static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = {
.master = &dra7xx_l4_wkup_hwmod,
@ -2412,94 +2074,6 @@ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__sha0 = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per2 -> mcasp1 */
static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp1 = {
.master = &dra7xx_l4_per2_hwmod,
.slave = &dra7xx_mcasp1_hwmod,
.clk = "l4_root_clk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l3_main_1 -> mcasp1 */
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp1 = {
.master = &dra7xx_l3_main_1_hwmod,
.slave = &dra7xx_mcasp1_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per2 -> mcasp2 */
static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp2 = {
.master = &dra7xx_l4_per2_hwmod,
.slave = &dra7xx_mcasp2_hwmod,
.clk = "l4_root_clk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l3_main_1 -> mcasp2 */
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp2 = {
.master = &dra7xx_l3_main_1_hwmod,
.slave = &dra7xx_mcasp2_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per2 -> mcasp3 */
static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp3 = {
.master = &dra7xx_l4_per2_hwmod,
.slave = &dra7xx_mcasp3_hwmod,
.clk = "l4_root_clk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l3_main_1 -> mcasp3 */
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp3 = {
.master = &dra7xx_l3_main_1_hwmod,
.slave = &dra7xx_mcasp3_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per2 -> mcasp4 */
static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp4 = {
.master = &dra7xx_l4_per2_hwmod,
.slave = &dra7xx_mcasp4_hwmod,
.clk = "l4_root_clk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per2 -> mcasp5 */
static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp5 = {
.master = &dra7xx_l4_per2_hwmod,
.slave = &dra7xx_mcasp5_hwmod,
.clk = "l4_root_clk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per2 -> mcasp6 */
static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp6 = {
.master = &dra7xx_l4_per2_hwmod,
.slave = &dra7xx_mcasp6_hwmod,
.clk = "l4_root_clk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per2 -> mcasp7 */
static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp7 = {
.master = &dra7xx_l4_per2_hwmod,
.slave = &dra7xx_mcasp7_hwmod,
.clk = "l4_root_clk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per2 -> mcasp8 */
static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp8 = {
.master = &dra7xx_l4_per2_hwmod,
.slave = &dra7xx_mcasp8_hwmod,
.clk = "l4_root_clk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per1 -> elm */
static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {
.master = &dra7xx_l4_per1_hwmod,
@ -2628,38 +2202,6 @@ static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox13 = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per1 -> mcspi1 */
static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = {
.master = &dra7xx_l4_per1_hwmod,
.slave = &dra7xx_mcspi1_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per1 -> mcspi2 */
static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi2 = {
.master = &dra7xx_l4_per1_hwmod,
.slave = &dra7xx_mcspi2_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per1 -> mcspi3 */
static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi3 = {
.master = &dra7xx_l4_per1_hwmod,
.slave = &dra7xx_mcspi3_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_per1 -> mcspi4 */
static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi4 = {
.master = &dra7xx_l4_per1_hwmod,
.slave = &dra7xx_mcspi4_hwmod,
.clk = "l3_iclk_div",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_cfg -> mpu */
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
.master = &dra7xx_l4_cfg_hwmod,
@ -3021,19 +2563,6 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
&dra7xx_l4_wkup__ctrl_module_wkup,
&dra7xx_l4_wkup__dcan1,
&dra7xx_l4_per2__dcan2,
&dra7xx_l4_per2__cpgmac0,
&dra7xx_l4_per2__mcasp1,
&dra7xx_l3_main_1__mcasp1,
&dra7xx_l4_per2__mcasp2,
&dra7xx_l3_main_1__mcasp2,
&dra7xx_l4_per2__mcasp3,
&dra7xx_l3_main_1__mcasp3,
&dra7xx_l4_per2__mcasp4,
&dra7xx_l4_per2__mcasp5,
&dra7xx_l4_per2__mcasp6,
&dra7xx_l4_per2__mcasp7,
&dra7xx_l4_per2__mcasp8,
&dra7xx_gmac__mdio,
&dra7xx_l4_cfg__dma_system,
&dra7xx_l3_main_1__tpcc,
&dra7xx_l3_main_1__tptc0,
@ -3060,10 +2589,6 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
&dra7xx_l4_per3__mailbox11,
&dra7xx_l4_per3__mailbox12,
&dra7xx_l4_per3__mailbox13,
&dra7xx_l4_per1__mcspi1,
&dra7xx_l4_per1__mcspi2,
&dra7xx_l4_per1__mcspi3,
&dra7xx_l4_per1__mcspi4,
&dra7xx_l4_cfg__mpu,
&dra7xx_l4_cfg__ocp2scp1,
&dra7xx_l4_cfg__ocp2scp3,