drm/amdgpu: add Sienna_Cichlid VCN PG and CG support (v2)
This is for static powergating and clockgating v2: fix registers (Alex) Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Leo Liu
Alex Deucher
parent
cf14826cdf
commit
fedac0155a
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@ -381,6 +381,309 @@ static void vcn_v3_0_mc_resume(struct amdgpu_device *adev, int inst)
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WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
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}
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static void vcn_v3_0_disable_static_power_gating(struct amdgpu_device *adev, int inst)
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{
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uint32_t data = 0;
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int ret;
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if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
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data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
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| 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
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| 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
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| 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
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| 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
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| 2 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT
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| 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT
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| 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
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| 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
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| 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
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| 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT
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| 2 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT
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| 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT
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| 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT);
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WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data);
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SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS,
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UVD_PGFSM_STATUS__UVDM_UVDU_UVDLM_PWR_ON_3_0, 0x3F3FFFFF, ret);
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} else {
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data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
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| 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
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| 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
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| 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
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| 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
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| 1 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT
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| 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT
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| 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
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| 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
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| 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
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| 1 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT
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| 1 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT
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| 1 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT
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| 1 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT);
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WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data);
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SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, 0, 0x3F3FFFFF, ret);
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}
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data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS);
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data &= ~0x103;
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if (adev->pg_flags & AMD_PG_SUPPORT_VCN)
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data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON |
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UVD_POWER_STATUS__UVD_PG_EN_MASK;
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WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data);
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}
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static void vcn_v3_0_enable_static_power_gating(struct amdgpu_device *adev, int inst)
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{
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uint32_t data;
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int ret;
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if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
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/* Before power off, this indicator has to be turned on */
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data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS);
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data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK;
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data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF;
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WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data);
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data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
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| 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
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| 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
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| 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
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| 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
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| 2 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT
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| 2 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT
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| 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
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| 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
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| 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
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| 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT
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| 2 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT
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| 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT
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| 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT);
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WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data);
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data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT
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| 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT
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| 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT
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| 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT
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| 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT
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| 2 << UVD_PGFSM_STATUS__UVDIRL_PWR_STATUS__SHIFT
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| 2 << UVD_PGFSM_STATUS__UVDLM_PWR_STATUS__SHIFT
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| 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT
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| 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT
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| 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT
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| 2 << UVD_PGFSM_STATUS__UVDAB_PWR_STATUS__SHIFT
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| 2 << UVD_PGFSM_STATUS__UVDATD_PWR_STATUS__SHIFT
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| 2 << UVD_PGFSM_STATUS__UVDNA_PWR_STATUS__SHIFT
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| 2 << UVD_PGFSM_STATUS__UVDNB_PWR_STATUS__SHIFT);
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SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, data, 0x3F3FFFFF, ret);
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}
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}
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/**
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* vcn_v3_0_disable_clock_gating - disable VCN clock gating
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*
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* @adev: amdgpu_device pointer
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* @inst: instance number
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*
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* Disable clock gating for VCN block
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*/
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static void vcn_v3_0_disable_clock_gating(struct amdgpu_device *adev, int inst)
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{
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uint32_t data;
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int ret = 0;
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/* VCN disable CGC */
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data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL);
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if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
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data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
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else
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data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
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data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
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data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
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WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data);
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data = RREG32_SOC15(VCN, inst, mmUVD_CGC_GATE);
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data &= ~(UVD_CGC_GATE__SYS_MASK
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| UVD_CGC_GATE__UDEC_MASK
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| UVD_CGC_GATE__MPEG2_MASK
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| UVD_CGC_GATE__REGS_MASK
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| UVD_CGC_GATE__RBC_MASK
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| UVD_CGC_GATE__LMI_MC_MASK
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| UVD_CGC_GATE__LMI_UMC_MASK
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| UVD_CGC_GATE__IDCT_MASK
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| UVD_CGC_GATE__MPRD_MASK
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| UVD_CGC_GATE__MPC_MASK
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| UVD_CGC_GATE__LBSI_MASK
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| UVD_CGC_GATE__LRBBM_MASK
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| UVD_CGC_GATE__UDEC_RE_MASK
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| UVD_CGC_GATE__UDEC_CM_MASK
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| UVD_CGC_GATE__UDEC_IT_MASK
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| UVD_CGC_GATE__UDEC_DB_MASK
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| UVD_CGC_GATE__UDEC_MP_MASK
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| UVD_CGC_GATE__WCB_MASK
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| UVD_CGC_GATE__VCPU_MASK
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| UVD_CGC_GATE__MMSCH_MASK);
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WREG32_SOC15(VCN, inst, mmUVD_CGC_GATE, data);
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SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_CGC_GATE, 0, 0xFFFFFFFF, ret);
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data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL);
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data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK
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| UVD_CGC_CTRL__UDEC_CM_MODE_MASK
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| UVD_CGC_CTRL__UDEC_IT_MODE_MASK
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| UVD_CGC_CTRL__UDEC_DB_MODE_MASK
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| UVD_CGC_CTRL__UDEC_MP_MODE_MASK
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| UVD_CGC_CTRL__SYS_MODE_MASK
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| UVD_CGC_CTRL__UDEC_MODE_MASK
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| UVD_CGC_CTRL__MPEG2_MODE_MASK
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| UVD_CGC_CTRL__REGS_MODE_MASK
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| UVD_CGC_CTRL__RBC_MODE_MASK
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| UVD_CGC_CTRL__LMI_MC_MODE_MASK
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| UVD_CGC_CTRL__LMI_UMC_MODE_MASK
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| UVD_CGC_CTRL__IDCT_MODE_MASK
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| UVD_CGC_CTRL__MPRD_MODE_MASK
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| UVD_CGC_CTRL__MPC_MODE_MASK
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| UVD_CGC_CTRL__LBSI_MODE_MASK
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| UVD_CGC_CTRL__LRBBM_MODE_MASK
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| UVD_CGC_CTRL__WCB_MODE_MASK
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| UVD_CGC_CTRL__VCPU_MODE_MASK
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| UVD_CGC_CTRL__MMSCH_MODE_MASK);
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WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data);
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data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE);
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data |= (UVD_SUVD_CGC_GATE__SRE_MASK
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| UVD_SUVD_CGC_GATE__SIT_MASK
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| UVD_SUVD_CGC_GATE__SMP_MASK
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| UVD_SUVD_CGC_GATE__SCM_MASK
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| UVD_SUVD_CGC_GATE__SDB_MASK
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| UVD_SUVD_CGC_GATE__SRE_H264_MASK
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| UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
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| UVD_SUVD_CGC_GATE__SIT_H264_MASK
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| UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
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| UVD_SUVD_CGC_GATE__SCM_H264_MASK
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| UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
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| UVD_SUVD_CGC_GATE__SDB_H264_MASK
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| UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
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| UVD_SUVD_CGC_GATE__SCLR_MASK
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| UVD_SUVD_CGC_GATE__ENT_MASK
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| UVD_SUVD_CGC_GATE__IME_MASK
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| UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
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| UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
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| UVD_SUVD_CGC_GATE__SITE_MASK
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| UVD_SUVD_CGC_GATE__SRE_VP9_MASK
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| UVD_SUVD_CGC_GATE__SCM_VP9_MASK
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| UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
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| UVD_SUVD_CGC_GATE__SDB_VP9_MASK
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| UVD_SUVD_CGC_GATE__IME_HEVC_MASK
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| UVD_SUVD_CGC_GATE__EFC_MASK
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| UVD_SUVD_CGC_GATE__SAOE_MASK
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| 0x08000000
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| UVD_SUVD_CGC_GATE__FBC_PCLK_MASK
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| UVD_SUVD_CGC_GATE__FBC_CCLK_MASK
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| 0x40000000
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| UVD_SUVD_CGC_GATE__SMPA_MASK);
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WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE, data);
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data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2);
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data |= (UVD_SUVD_CGC_GATE2__MPBE0_MASK
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| UVD_SUVD_CGC_GATE2__MPBE1_MASK
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| 0x00000004
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| 0x00000008
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| UVD_SUVD_CGC_GATE2__MPC1_MASK);
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WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2, data);
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data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL);
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data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
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| UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
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| UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
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| UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
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| UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
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| UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
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| UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
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| UVD_SUVD_CGC_CTRL__IME_MODE_MASK
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| UVD_SUVD_CGC_CTRL__SITE_MODE_MASK
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| UVD_SUVD_CGC_CTRL__EFC_MODE_MASK
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| UVD_SUVD_CGC_CTRL__SAOE_MODE_MASK
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| UVD_SUVD_CGC_CTRL__SMPA_MODE_MASK
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| UVD_SUVD_CGC_CTRL__MPBE0_MODE_MASK
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| UVD_SUVD_CGC_CTRL__MPBE1_MODE_MASK
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| 0x00008000
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| 0x00010000
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| UVD_SUVD_CGC_CTRL__MPC1_MODE_MASK
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| UVD_SUVD_CGC_CTRL__FBC_PCLK_MASK
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| UVD_SUVD_CGC_CTRL__FBC_CCLK_MASK);
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WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data);
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}
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/**
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* vcn_v3_0_enable_clock_gating - enable VCN clock gating
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*
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* @adev: amdgpu_device pointer
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* @inst: instance number
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*
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* Enable clock gating for VCN block
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*/
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static void vcn_v3_0_enable_clock_gating(struct amdgpu_device *adev, int inst)
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{
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uint32_t data;
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/* enable VCN CGC */
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data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL);
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if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
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data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
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else
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data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
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data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
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data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
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WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data);
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data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL);
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data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK
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| UVD_CGC_CTRL__UDEC_CM_MODE_MASK
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| UVD_CGC_CTRL__UDEC_IT_MODE_MASK
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| UVD_CGC_CTRL__UDEC_DB_MODE_MASK
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| UVD_CGC_CTRL__UDEC_MP_MODE_MASK
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| UVD_CGC_CTRL__SYS_MODE_MASK
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| UVD_CGC_CTRL__UDEC_MODE_MASK
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| UVD_CGC_CTRL__MPEG2_MODE_MASK
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| UVD_CGC_CTRL__REGS_MODE_MASK
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| UVD_CGC_CTRL__RBC_MODE_MASK
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| UVD_CGC_CTRL__LMI_MC_MODE_MASK
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| UVD_CGC_CTRL__LMI_UMC_MODE_MASK
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| UVD_CGC_CTRL__IDCT_MODE_MASK
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| UVD_CGC_CTRL__MPRD_MODE_MASK
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| UVD_CGC_CTRL__MPC_MODE_MASK
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| UVD_CGC_CTRL__LBSI_MODE_MASK
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| UVD_CGC_CTRL__LRBBM_MODE_MASK
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| UVD_CGC_CTRL__WCB_MODE_MASK
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| UVD_CGC_CTRL__VCPU_MODE_MASK
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| UVD_CGC_CTRL__MMSCH_MODE_MASK);
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WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data);
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data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL);
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data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
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| UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
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| UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
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| UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
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| UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
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| UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
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| UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
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| UVD_SUVD_CGC_CTRL__IME_MODE_MASK
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| UVD_SUVD_CGC_CTRL__SITE_MODE_MASK
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| UVD_SUVD_CGC_CTRL__EFC_MODE_MASK
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| UVD_SUVD_CGC_CTRL__SAOE_MODE_MASK
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| UVD_SUVD_CGC_CTRL__SMPA_MODE_MASK
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| UVD_SUVD_CGC_CTRL__MPBE0_MODE_MASK
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| UVD_SUVD_CGC_CTRL__MPBE1_MODE_MASK
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| 0x00008000
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| 0x00010000
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| UVD_SUVD_CGC_CTRL__MPC1_MODE_MASK
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| UVD_SUVD_CGC_CTRL__FBC_PCLK_MASK
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| UVD_SUVD_CGC_CTRL__FBC_CCLK_MASK);
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WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data);
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}
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static int vcn_v3_0_start(struct amdgpu_device *adev)
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{
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struct amdgpu_ring *ring;
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@ -394,10 +697,16 @@ static int vcn_v3_0_start(struct amdgpu_device *adev)
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if (adev->vcn.harvest_config & (1 << i))
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continue;
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/* disable VCN power gating */
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vcn_v3_0_disable_static_power_gating(adev, i);
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/* set VCN status busy */
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tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;
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WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp);
|
||||
|
||||
/*SW clock gating */
|
||||
vcn_v3_0_disable_clock_gating(adev, i);
|
||||
|
||||
/* enable VCPU clock */
|
||||
WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
|
||||
UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
|
||||
|
|
@ -600,6 +909,12 @@ static int vcn_v3_0_stop(struct amdgpu_device *adev)
|
|||
|
||||
/* clear status */
|
||||
WREG32_SOC15(VCN, i, mmUVD_STATUS, 0);
|
||||
|
||||
/* apply HW clock gating */
|
||||
vcn_v3_0_enable_clock_gating(adev, i);
|
||||
|
||||
/* enable VCN power gating */
|
||||
vcn_v3_0_enable_static_power_gating(adev, i);
|
||||
}
|
||||
|
||||
if (adev->pm.dpm_enabled)
|
||||
|
|
@ -853,6 +1168,23 @@ static int vcn_v3_0_wait_for_idle(void *handle)
|
|||
static int vcn_v3_0_set_clockgating_state(void *handle,
|
||||
enum amd_clockgating_state state)
|
||||
{
|
||||
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
||||
bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
|
||||
if (adev->vcn.harvest_config & (1 << i))
|
||||
continue;
|
||||
|
||||
if (enable) {
|
||||
if (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE)
|
||||
return -EBUSY;
|
||||
vcn_v3_0_enable_clock_gating(adev, i);
|
||||
} else {
|
||||
vcn_v3_0_disable_clock_gating(adev, i);
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue