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xtensa: increase ranges in ___invalidate_{i,d}cache_all 

Cache invalidation macros use cache line size to iterate over
invalidated cache lines, assuming that all cache ways are invalidated by
single instruction, but xtensa ISA recommends to not assume that for
future compatibility:
  In some implementations all ways at index Addry-1..z are invalidated
  regardless of the specified way, but for future compatibility this
  behavior should not be assumed.

Iterate over all cache ways in ___invalidate_icache_all and
___invalidate_dcache_all.

Cc: stable@vger.kernel.org
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
This commit is contained in:
Max Filippov 2018-08-10 22:21:22 -07:00
parent be75de2525
commit fec3259c9f
1 changed files with 2 additions and 2 deletions
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4
arch/xtensa/include/asm/cacheasm.h
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@ -123,7 +123,7 @@
.macro ___invalidate_dcache_all ar at .macro ___invalidate_dcache_all ar at
#if XCHAL_DCACHE_SIZE #if XCHAL_DCACHE_SIZE
__loop_cache_all \ar \at dii __stringify(DCACHE_WAY_SIZE) \ __loop_cache_all \ar \at dii XCHAL_DCACHE_SIZE \
XCHAL_DCACHE_LINEWIDTH 1020 XCHAL_DCACHE_LINEWIDTH 1020
#endif #endif
@ -133,7 +133,7 @@
.macro ___invalidate_icache_all ar at .macro ___invalidate_icache_all ar at
#if XCHAL_ICACHE_SIZE #if XCHAL_ICACHE_SIZE
__loop_cache_all \ar \at iii __stringify(ICACHE_WAY_SIZE) \ __loop_cache_all \ar \at iii XCHAL_ICACHE_SIZE \
XCHAL_ICACHE_LINEWIDTH 1020 XCHAL_ICACHE_LINEWIDTH 1020
#endif #endif