msm:disp:dpu1: Fix core clk rate in display driver

Fix max core clk rate during dt parsing in display driver.

Signed-off-by: Shubhashree Dhar <dhar@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>
This commit is contained in:
Shubhashree Dhar 2019-11-27 15:46:07 +05:30 committed by Rob Clark
parent b75ab05a34
commit fea2d7d98e
1 changed files with 1 additions and 0 deletions

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@ -175,6 +175,7 @@ int msm_dss_parse_clock(struct platform_device *pdev,
continue;
mp->clk_config[i].rate = rate;
mp->clk_config[i].type = DSS_CLK_PCLK;
mp->clk_config[i].max_rate = rate;
}
mp->num_clk = num_clk;