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drm/i915: Actually write the correct bits to DPFC_CONTROL on CTG 

We set up all the bits for DPFC_CONTROL but forgot to actually
write them to the register. Oops.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Ville Syrjälä 2014-01-23 16:49:13 +02:00 committed by Daniel Vetter
parent 3fa2e0eec7
commit fe74c1a54f
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/drm/i915/intel_pm.c
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@ -165,7 +165,7 @@ static void g4x_enable_fbc(struct drm_crtc *crtc)
I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
/* enable it... */
I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
}