ARM: tegra: Device tree changes for v4.16-rc1
These changes enable the video decoder engine found on Tegra20 SoCs. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAlo6toITHHRyZWRpbmdA bnZpZGlhLmNvbQAKCRDdI6zXfz6zoYs+D/4sVFi9PmWzGv2OwcOfIN8gC2g0sOBl 3bOFKRiLGUtX444RngWqykHP9Ug8txdRQ6PgGyZMWyTzC2jX61gwNhhIB1ZSpzPq +2PwIawhxeu6gjcZZUdMvuG4Y5RFp2X5ZjxrQWsoUxkgOcKKyAnNd2cNT5h3bHyq XF7YfvmzxzaV/BqEjqpm9Ob+afEwx19CX8lzkMUV7JX59SnFt4CFXkbw3vOyn19R FH9tlRigNBpUkMJZ7lHGsRHVy6jd8QLEcqmq2gfLaIcgpICivzdxjyumRl6HBnaj rL/02Kw2eTWBsySss+L+kZDF6RvO4mYv+2NsOtHfYlkAhY+Cmm2ermGY0rluk+B8 0G7R0Q/O+oqrMYRHX0SG8BjsYMMvODHxYzuRTEPEKfplJEiz25sZHyjQj58BsNa5 j02uwnrDZOTT0uJ0aJm6H5RCOZKK43sog25XRIXVIS3f0k2KqjLYAMlc40nYGveU 8mB3BzQeIGLQbwm5Y+istn9+M3oCJ52qLRjBxeLC7q9IyyHL2/dL/aMGMVT9bstx jFuf6NBMtlbUmiFfNXMjgY6Bs3+ghX7lVb6A3h03XEFSlpTMx69VUxfuIFvIlIeQ RKO7VmZ0iiuE5e79QQ9OQHrFKnxAGEbfQyLnY8+xJ+sd2l4kOmgzxqHoSvDY58ZU 6LEHm1C2RjGlXQ== =bS8w -----END PGP SIGNATURE----- Merge tag 'tegra-for-4.16-arm-dt' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt Pull "ARM: tegra: Device tree changes for v4.16-rc1" from Thierry Reding: These changes enable the video decoder engine found on Tegra20 SoCs. * tag 'tegra-for-4.16-arm-dt' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/tegra/linux: ARM: tegra: Add video decoder on Tegra20 ARM: tegra: Add device tree node to describe IRAM on Tegra20
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@ -10,6 +10,19 @@
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compatible = "nvidia,tegra20";
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interrupt-parent = <&lic>;
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iram@40000000 {
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compatible = "mmio-sram";
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reg = <0x40000000 0x40000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x40000000 0x40000>;
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vde_pool: vde {
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reg = <0x400 0x3fc00>;
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pool;
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};
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};
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host1x@50000000 {
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compatible = "nvidia,tegra20-host1x", "simple-bus";
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reg = <0x50000000 0x00024000>;
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@ -250,6 +263,28 @@
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*/
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};
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vde@6001a000 {
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compatible = "nvidia,tegra20-vde";
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reg = <0x6001a000 0x1000 /* Syntax Engine */
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0x6001b000 0x1000 /* Video Bitstream Engine */
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0x6001c000 0x100 /* Macroblock Engine */
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0x6001c200 0x100 /* Post-processing Engine */
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0x6001c400 0x100 /* Motion Compensation Engine */
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0x6001c600 0x100 /* Transform Engine */
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0x6001c800 0x100 /* Pixel prediction block */
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0x6001ca00 0x100 /* Video DMA */
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0x6001d800 0x300>; /* Video frame controls */
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reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
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"tfe", "ppb", "vdma", "frameid";
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iram = <&vde_pool>; /* IRAM region */
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */
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<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */
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<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */
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interrupt-names = "sync-token", "bsev", "sxe";
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clocks = <&tegra_car TEGRA20_CLK_VDE>;
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resets = <&tegra_car 61>;
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};
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apbmisc@70000800 {
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compatible = "nvidia,tegra20-apbmisc";
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reg = <0x70000800 0x64 /* Chip revision */
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