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drm/amd/display: Adjust static-ness of resource functions 

[Why]
Register definitions are asic-specific, so functions that use registers of
a particular asic should be static, to be exposed in asic-specific function
pointer structures.

[How]
 - make register-definition-using functions static
 - make some functions non-static, for future use
 - remove duplicate function definition

Signed-off-by: Joshua Aberback <joshua.aberback@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Joshua Aberback 2020-07-16 12:39:27 -04:00 committed by Alex Deucher
parent bcca629806
commit fe04afad4e
3 changed files with 18 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
View File

@ -95,7 +95,6 @@ struct display_stream_compressor *dcn20_dsc_create(
struct dc_context *ctx, uint32_t inst); struct dc_context *ctx, uint32_t inst);
void dcn20_dsc_destroy(struct display_stream_compressor **dsc); void dcn20_dsc_destroy(struct display_stream_compressor **dsc);
void dcn20_patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb);
void dcn20_cap_soc_clocks( void dcn20_cap_soc_clocks(
struct _vcs_dpi_soc_bounding_box_st *bb, struct _vcs_dpi_soc_bounding_box_st *bb,
struct pp_smu_nv_clock_table max_clocks); struct pp_smu_nv_clock_table max_clocks);

27
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
View File

@ -871,7 +871,7 @@ void dcn30_dpp_destroy(struct dpp **dpp)
*dpp = NULL; *dpp = NULL;
} }
struct dpp *dcn30_dpp_create( static struct dpp *dcn30_dpp_create(
struct dc_context *ctx, struct dc_context *ctx,
uint32_t inst) uint32_t inst)
{ {
@ -889,7 +889,8 @@ struct dpp *dcn30_dpp_create(
kfree(dpp); kfree(dpp);
return NULL; return NULL;
} }
struct output_pixel_processor *dcn30_opp_create(
static struct output_pixel_processor *dcn30_opp_create(
struct dc_context *ctx, uint32_t inst) struct dc_context *ctx, uint32_t inst)
{ {
struct dcn20_opp *opp = struct dcn20_opp *opp =
@ -905,7 +906,7 @@ struct output_pixel_processor *dcn30_opp_create(
return &opp->base; return &opp->base;
} }
struct dce_aux *dcn30_aux_engine_create( static struct dce_aux *dcn30_aux_engine_create(
struct dc_context *ctx, struct dc_context *ctx,
uint32_t inst) uint32_t inst)
{ {
@ -924,6 +925,7 @@ struct dce_aux *dcn30_aux_engine_create(
return &aux_engine->base; return &aux_engine->base;
} }
#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
static const struct dce_i2c_registers i2c_hw_regs[] = { static const struct dce_i2c_registers i2c_hw_regs[] = {
@ -943,7 +945,7 @@ static const struct dce_i2c_mask i2c_masks = {
I2C_COMMON_MASK_SH_LIST_DCN2(_MASK) I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
}; };
struct dce_i2c_hw *dcn30_i2c_hw_create( static struct dce_i2c_hw *dcn30_i2c_hw_create(
struct dc_context *ctx, struct dc_context *ctx,
uint32_t inst) uint32_t inst)
{ {
@ -958,6 +960,7 @@ struct dce_i2c_hw *dcn30_i2c_hw_create(
return dce_i2c_hw; return dce_i2c_hw;
} }
static struct mpc *dcn30_mpc_create( static struct mpc *dcn30_mpc_create(
struct dc_context *ctx, struct dc_context *ctx,
int num_mpcc, int num_mpcc,
@ -1008,7 +1011,7 @@ struct hubbub *dcn30_hubbub_create(struct dc_context *ctx)
return &hubbub3->base; return &hubbub3->base;
} }
struct timing_generator *dcn30_timing_generator_create( static struct timing_generator *dcn30_timing_generator_create(
struct dc_context *ctx, struct dc_context *ctx,
uint32_t instance) uint32_t instance)
{ {
@ -1042,7 +1045,7 @@ static const struct encoder_feature_support link_enc_feature = {
.flags.bits.IS_TPS4_CAPABLE = true .flags.bits.IS_TPS4_CAPABLE = true
}; };
struct link_encoder *dcn30_link_encoder_create( static struct link_encoder *dcn30_link_encoder_create(
const struct encoder_init_data *enc_init_data) const struct encoder_init_data *enc_init_data)
{ {
struct dcn20_link_encoder *enc20 = struct dcn20_link_encoder *enc20 =
@ -1063,7 +1066,7 @@ struct link_encoder *dcn30_link_encoder_create(
return &enc20->enc10.base; return &enc20->enc10.base;
} }
struct panel_cntl *dcn30_panel_cntl_create(const struct panel_cntl_init_data *init_data) static struct panel_cntl *dcn30_panel_cntl_create(const struct panel_cntl_init_data *init_data)
{ {
struct dce_panel_cntl *panel_cntl = struct dce_panel_cntl *panel_cntl =
kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL); kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
@ -1311,7 +1314,7 @@ static void dcn30_resource_destruct(struct dcn30_resource_pool *pool)
dcn_dccg_destroy(&pool->base.dccg); dcn_dccg_destroy(&pool->base.dccg);
} }
struct hubp *dcn30_hubp_create( static struct hubp *dcn30_hubp_create(
struct dc_context *ctx, struct dc_context *ctx,
uint32_t inst) uint32_t inst)
{ {
@ -1330,7 +1333,7 @@ struct hubp *dcn30_hubp_create(
return NULL; return NULL;
} }
bool dcn30_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) static bool dcn30_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
{ {
int i; int i;
uint32_t pipe_count = pool->res_cap->num_dwb; uint32_t pipe_count = pool->res_cap->num_dwb;
@ -1355,7 +1358,7 @@ bool dcn30_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
return true; return true;
} }
bool dcn30_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) static bool dcn30_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
{ {
int i; int i;
uint32_t pipe_count = pool->res_cap->num_dwb; uint32_t pipe_count = pool->res_cap->num_dwb;
@ -2292,7 +2295,7 @@ static void get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts,
(dcn3_0_soc.return_bus_width_bytes * (dcn3_0_soc.max_avg_sdp_bw_use_normal_percent / 100)); (dcn3_0_soc.return_bus_width_bytes * (dcn3_0_soc.max_avg_sdp_bw_use_normal_percent / 100));
} }
static void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
{ {
unsigned int i, j; unsigned int i, j;
unsigned int num_states = 0; unsigned int num_states = 0;
@ -2683,7 +2686,7 @@ static bool dcn30_resource_construct(
if (!resource_construct(num_virtual_links, dc, &pool->base, if (!resource_construct(num_virtual_links, dc, &pool->base,
(!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
&res_create_funcs : &res_create_maximus_funcs))) &res_create_funcs : &res_create_maximus_funcs)))
goto create_fail; goto create_fail;
/* HW Sequencer and Plane caps */ /* HW Sequencer and Plane caps */
dcn30_hw_sequencer_construct(dc); dcn30_hw_sequencer_construct(dc);

3
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.h
View File

@ -79,4 +79,7 @@ enum dc_status dcn30_add_stream_to_ctx(
struct dc *dc, struct dc *dc,
struct dc_state *new_ctx, struct dc_state *new_ctx,
struct dc_stream_state *dc_stream); struct dc_stream_state *dc_stream);
void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
#endif /* _DCN30_RESOURCE_H_ */ #endif /* _DCN30_RESOURCE_H_ */