ASoC: mediatek: mt8188: support audsys clock
Add mt8188 audio cg clock control. Audio clock gates are registered to CCF for reference count and clock parent management. Signed-off-by: Trevor Wu <trevor.wu@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230116034131.23943-4-trevor.wu@mediatek.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Trevor Wu
Mark Brown
parent
f90f0dd809
commit
fdd4e1a28d
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// SPDX-License-Identifier: GPL-2.0
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/*
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* mt8188-audsys-clk.c -- MediaTek 8188 audsys clock control
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*
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* Copyright (c) 2022 MediaTek Inc.
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* Author: Chun-Chia Chiu <chun-chia.chiu@mediatek.com>
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include "mt8188-afe-common.h"
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#include "mt8188-audsys-clk.h"
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#include "mt8188-audsys-clkid.h"
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#include "mt8188-reg.h"
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struct afe_gate {
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int id;
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const char *name;
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const char *parent_name;
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int reg;
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u8 bit;
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const struct clk_ops *ops;
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unsigned long flags;
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u8 cg_flags;
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};
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#define GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit, _flags, _cgflags) {\
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.reg = _reg, \
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.bit = _bit, \
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.flags = _flags, \
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.cg_flags = _cgflags, \
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}
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#define GATE_AFE(_id, _name, _parent, _reg, _bit) \
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GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit, \
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CLK_SET_RATE_PARENT, CLK_GATE_SET_TO_DISABLE)
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#define GATE_AUD0(_id, _name, _parent, _bit) \
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GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON0, _bit)
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#define GATE_AUD1(_id, _name, _parent, _bit) \
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GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON1, _bit)
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#define GATE_AUD3(_id, _name, _parent, _bit) \
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GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON3, _bit)
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#define GATE_AUD4(_id, _name, _parent, _bit) \
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GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON4, _bit)
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#define GATE_AUD5(_id, _name, _parent, _bit) \
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GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON5, _bit)
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#define GATE_AUD6(_id, _name, _parent, _bit) \
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GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON6, _bit)
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static const struct afe_gate aud_clks[CLK_AUD_NR_CLK] = {
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/* AUD0 */
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GATE_AUD0(CLK_AUD_AFE, "aud_afe", "top_a1sys_hp", 2),
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GATE_AUD0(CLK_AUD_LRCK_CNT, "aud_lrck_cnt", "top_a1sys_hp", 4),
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GATE_AUD0(CLK_AUD_SPDIFIN_TUNER_APLL, "aud_spdifin_tuner_apll", "top_apll4", 10),
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GATE_AUD0(CLK_AUD_SPDIFIN_TUNER_DBG, "aud_spdifin_tuner_dbg", "top_apll4", 11),
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GATE_AUD0(CLK_AUD_UL_TML, "aud_ul_tml", "top_a1sys_hp", 18),
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GATE_AUD0(CLK_AUD_APLL1_TUNER, "aud_apll1_tuner", "top_apll1", 19),
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GATE_AUD0(CLK_AUD_APLL2_TUNER, "aud_apll2_tuner", "top_apll2", 20),
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GATE_AUD0(CLK_AUD_TOP0_SPDF, "aud_top0_spdf", "top_aud_iec_clk", 21),
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GATE_AUD0(CLK_AUD_APLL, "aud_apll", "top_apll1", 23),
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GATE_AUD0(CLK_AUD_APLL2, "aud_apll2", "top_apll2", 24),
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GATE_AUD0(CLK_AUD_DAC, "aud_dac", "top_a1sys_hp", 25),
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GATE_AUD0(CLK_AUD_DAC_PREDIS, "aud_dac_predis", "top_a1sys_hp", 26),
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GATE_AUD0(CLK_AUD_TML, "aud_tml", "top_a1sys_hp", 27),
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GATE_AUD0(CLK_AUD_ADC, "aud_adc", "top_a1sys_hp", 28),
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GATE_AUD0(CLK_AUD_DAC_HIRES, "aud_dac_hires", "top_audio_h", 31),
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/* AUD1 */
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GATE_AUD1(CLK_AUD_A1SYS_HP, "aud_a1sys_hp", "top_a1sys_hp", 2),
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GATE_AUD1(CLK_AUD_AFE_DMIC1, "aud_afe_dmic1", "top_a1sys_hp", 10),
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GATE_AUD1(CLK_AUD_AFE_DMIC2, "aud_afe_dmic2", "top_a1sys_hp", 11),
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GATE_AUD1(CLK_AUD_AFE_DMIC3, "aud_afe_dmic3", "top_a1sys_hp", 12),
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GATE_AUD1(CLK_AUD_AFE_DMIC4, "aud_afe_dmic4", "top_a1sys_hp", 13),
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GATE_AUD1(CLK_AUD_AFE_26M_DMIC_TM, "aud_afe_26m_dmic_tm", "top_a1sys_hp", 14),
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GATE_AUD1(CLK_AUD_UL_TML_HIRES, "aud_ul_tml_hires", "top_audio_h", 16),
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GATE_AUD1(CLK_AUD_ADC_HIRES, "aud_adc_hires", "top_audio_h", 17),
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/* AUD3 */
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GATE_AUD3(CLK_AUD_LINEIN_TUNER, "aud_linein_tuner", "top_apll5", 5),
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GATE_AUD3(CLK_AUD_EARC_TUNER, "aud_earc_tuner", "top_apll3", 7),
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/* AUD4 */
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GATE_AUD4(CLK_AUD_I2SIN, "aud_i2sin", "top_a1sys_hp", 0),
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GATE_AUD4(CLK_AUD_TDM_IN, "aud_tdm_in", "top_a1sys_hp", 1),
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GATE_AUD4(CLK_AUD_I2S_OUT, "aud_i2s_out", "top_a1sys_hp", 6),
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GATE_AUD4(CLK_AUD_TDM_OUT, "aud_tdm_out", "top_a1sys_hp", 7),
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GATE_AUD4(CLK_AUD_HDMI_OUT, "aud_hdmi_out", "top_a1sys_hp", 8),
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GATE_AUD4(CLK_AUD_ASRC11, "aud_asrc11", "top_a1sys_hp", 16),
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GATE_AUD4(CLK_AUD_ASRC12, "aud_asrc12", "top_a1sys_hp", 17),
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GATE_AUD4(CLK_AUD_MULTI_IN, "aud_multi_in", "mphone_slave_b", 19),
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GATE_AUD4(CLK_AUD_INTDIR, "aud_intdir", "top_intdir", 20),
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GATE_AUD4(CLK_AUD_A1SYS, "aud_a1sys", "top_a1sys_hp", 21),
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GATE_AUD4(CLK_AUD_A2SYS, "aud_a2sys", "top_a2sys", 22),
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GATE_AUD4(CLK_AUD_PCMIF, "aud_pcmif", "top_a1sys_hp", 24),
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GATE_AUD4(CLK_AUD_A3SYS, "aud_a3sys", "top_a3sys", 30),
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GATE_AUD4(CLK_AUD_A4SYS, "aud_a4sys", "top_a4sys", 31),
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/* AUD5 */
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GATE_AUD5(CLK_AUD_MEMIF_UL1, "aud_memif_ul1", "top_a1sys_hp", 0),
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GATE_AUD5(CLK_AUD_MEMIF_UL2, "aud_memif_ul2", "top_a1sys_hp", 1),
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GATE_AUD5(CLK_AUD_MEMIF_UL3, "aud_memif_ul3", "top_a1sys_hp", 2),
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GATE_AUD5(CLK_AUD_MEMIF_UL4, "aud_memif_ul4", "top_a1sys_hp", 3),
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GATE_AUD5(CLK_AUD_MEMIF_UL5, "aud_memif_ul5", "top_a1sys_hp", 4),
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GATE_AUD5(CLK_AUD_MEMIF_UL6, "aud_memif_ul6", "top_a1sys_hp", 5),
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GATE_AUD5(CLK_AUD_MEMIF_UL8, "aud_memif_ul8", "top_a1sys_hp", 7),
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GATE_AUD5(CLK_AUD_MEMIF_UL9, "aud_memif_ul9", "top_a1sys_hp", 8),
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GATE_AUD5(CLK_AUD_MEMIF_UL10, "aud_memif_ul10", "top_a1sys_hp", 9),
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GATE_AUD5(CLK_AUD_MEMIF_DL2, "aud_memif_dl2", "top_a1sys_hp", 18),
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GATE_AUD5(CLK_AUD_MEMIF_DL3, "aud_memif_dl3", "top_a1sys_hp", 19),
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GATE_AUD5(CLK_AUD_MEMIF_DL6, "aud_memif_dl6", "top_a1sys_hp", 22),
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GATE_AUD5(CLK_AUD_MEMIF_DL7, "aud_memif_dl7", "top_a1sys_hp", 23),
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GATE_AUD5(CLK_AUD_MEMIF_DL8, "aud_memif_dl8", "top_a1sys_hp", 24),
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GATE_AUD5(CLK_AUD_MEMIF_DL10, "aud_memif_dl10", "top_a1sys_hp", 26),
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GATE_AUD5(CLK_AUD_MEMIF_DL11, "aud_memif_dl11", "top_a1sys_hp", 27),
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/* AUD6 */
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GATE_AUD6(CLK_AUD_GASRC0, "aud_gasrc0", "top_asm_h", 0),
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GATE_AUD6(CLK_AUD_GASRC1, "aud_gasrc1", "top_asm_h", 1),
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GATE_AUD6(CLK_AUD_GASRC2, "aud_gasrc2", "top_asm_h", 2),
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GATE_AUD6(CLK_AUD_GASRC3, "aud_gasrc3", "top_asm_h", 3),
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GATE_AUD6(CLK_AUD_GASRC4, "aud_gasrc4", "top_asm_h", 4),
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GATE_AUD6(CLK_AUD_GASRC5, "aud_gasrc5", "top_asm_h", 5),
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GATE_AUD6(CLK_AUD_GASRC6, "aud_gasrc6", "top_asm_h", 6),
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GATE_AUD6(CLK_AUD_GASRC7, "aud_gasrc7", "top_asm_h", 7),
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GATE_AUD6(CLK_AUD_GASRC8, "aud_gasrc8", "top_asm_h", 8),
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GATE_AUD6(CLK_AUD_GASRC9, "aud_gasrc9", "top_asm_h", 9),
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GATE_AUD6(CLK_AUD_GASRC10, "aud_gasrc10", "top_asm_h", 10),
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GATE_AUD6(CLK_AUD_GASRC11, "aud_gasrc11", "top_asm_h", 11),
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};
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int mt8188_audsys_clk_register(struct mtk_base_afe *afe)
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{
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struct mt8188_afe_private *afe_priv = afe->platform_priv;
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struct clk *clk;
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struct clk_lookup *cl;
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int i;
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afe_priv->lookup = devm_kcalloc(afe->dev, CLK_AUD_NR_CLK,
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sizeof(*afe_priv->lookup),
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GFP_KERNEL);
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if (!afe_priv->lookup)
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return -ENOMEM;
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for (i = 0; i < ARRAY_SIZE(aud_clks); i++) {
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const struct afe_gate *gate = &aud_clks[i];
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clk = clk_register_gate(afe->dev, gate->name, gate->parent_name,
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gate->flags, afe->base_addr + gate->reg,
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gate->bit, gate->cg_flags, NULL);
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if (IS_ERR(clk)) {
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dev_err(afe->dev, "Failed to register clk %s: %ld\n",
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gate->name, PTR_ERR(clk));
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continue;
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}
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/* add clk_lookup for devm_clk_get(SND_SOC_DAPM_CLOCK_SUPPLY) */
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cl = kzalloc(sizeof(*cl), GFP_KERNEL);
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if (!cl)
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return -ENOMEM;
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cl->clk = clk;
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cl->con_id = gate->name;
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cl->dev_id = dev_name(afe->dev);
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cl->clk_hw = NULL;
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clkdev_add(cl);
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afe_priv->lookup[i] = cl;
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}
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return 0;
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}
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void mt8188_audsys_clk_unregister(struct mtk_base_afe *afe)
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{
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struct mt8188_afe_private *afe_priv = afe->platform_priv;
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struct clk *clk;
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struct clk_lookup *cl;
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int i;
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if (!afe_priv)
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return;
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for (i = 0; i < CLK_AUD_NR_CLK; i++) {
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cl = afe_priv->lookup[i];
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if (!cl)
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continue;
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clk = cl->clk;
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clk_unregister_gate(clk);
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clkdev_drop(cl);
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}
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}
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@ -0,0 +1,15 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* mt8188-audsys-clk.h -- MediaTek 8188 audsys clock definition
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*
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* Copyright (c) 2022 MediaTek Inc.
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* Author: Chun-Chia Chiu <chun-chia.chiu@mediatek.com>
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*/
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#ifndef _MT8188_AUDSYS_CLK_H_
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#define _MT8188_AUDSYS_CLK_H_
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int mt8188_audsys_clk_register(struct mtk_base_afe *afe);
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void mt8188_audsys_clk_unregister(struct mtk_base_afe *afe);
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#endif
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@ -0,0 +1,83 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* mt8188-audsys-clkid.h -- MediaTek 8188 audsys clock id definition
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*
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* Copyright (c) 2022 MediaTek Inc.
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* Author: Chun-Chia Chiu <chun-chia.chiu@mediatek.com>
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*/
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#ifndef _MT8188_AUDSYS_CLKID_H_
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#define _MT8188_AUDSYS_CLKID_H_
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enum{
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CLK_AUD_AFE,
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CLK_AUD_LRCK_CNT,
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CLK_AUD_SPDIFIN_TUNER_APLL,
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CLK_AUD_SPDIFIN_TUNER_DBG,
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CLK_AUD_UL_TML,
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CLK_AUD_APLL1_TUNER,
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CLK_AUD_APLL2_TUNER,
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CLK_AUD_TOP0_SPDF,
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CLK_AUD_APLL,
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CLK_AUD_APLL2,
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CLK_AUD_DAC,
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CLK_AUD_DAC_PREDIS,
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CLK_AUD_TML,
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CLK_AUD_ADC,
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CLK_AUD_DAC_HIRES,
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CLK_AUD_A1SYS_HP,
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CLK_AUD_AFE_DMIC1,
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CLK_AUD_AFE_DMIC2,
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CLK_AUD_AFE_DMIC3,
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CLK_AUD_AFE_DMIC4,
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CLK_AUD_AFE_26M_DMIC_TM,
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CLK_AUD_UL_TML_HIRES,
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CLK_AUD_ADC_HIRES,
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CLK_AUD_LINEIN_TUNER,
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CLK_AUD_EARC_TUNER,
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CLK_AUD_I2SIN,
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CLK_AUD_TDM_IN,
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CLK_AUD_I2S_OUT,
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CLK_AUD_TDM_OUT,
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CLK_AUD_HDMI_OUT,
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CLK_AUD_ASRC11,
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CLK_AUD_ASRC12,
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CLK_AUD_MULTI_IN,
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CLK_AUD_INTDIR,
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CLK_AUD_A1SYS,
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CLK_AUD_A2SYS,
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CLK_AUD_PCMIF,
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CLK_AUD_A3SYS,
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CLK_AUD_A4SYS,
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CLK_AUD_MEMIF_UL1,
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CLK_AUD_MEMIF_UL2,
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CLK_AUD_MEMIF_UL3,
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CLK_AUD_MEMIF_UL4,
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CLK_AUD_MEMIF_UL5,
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CLK_AUD_MEMIF_UL6,
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CLK_AUD_MEMIF_UL8,
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CLK_AUD_MEMIF_UL9,
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CLK_AUD_MEMIF_UL10,
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CLK_AUD_MEMIF_DL2,
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CLK_AUD_MEMIF_DL3,
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CLK_AUD_MEMIF_DL6,
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CLK_AUD_MEMIF_DL7,
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CLK_AUD_MEMIF_DL8,
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CLK_AUD_MEMIF_DL10,
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CLK_AUD_MEMIF_DL11,
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CLK_AUD_GASRC0,
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CLK_AUD_GASRC1,
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CLK_AUD_GASRC2,
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CLK_AUD_GASRC3,
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CLK_AUD_GASRC4,
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CLK_AUD_GASRC5,
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CLK_AUD_GASRC6,
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CLK_AUD_GASRC7,
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CLK_AUD_GASRC8,
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CLK_AUD_GASRC9,
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CLK_AUD_GASRC10,
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CLK_AUD_GASRC11,
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CLK_AUD_NR_CLK,
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};
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#endif
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