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OpenCloudOS-Kernel
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Merge branch 'next-merged' of git://aeryn.fluff.org.uk/bjdooks/linux into devel

This commit is contained in:
Russell King 2008-12-18 22:15:30 +00:00 committed by Russell King
parent fc0b7a2036 7bb56d01f1
commit fdb0a1a67e
177 changed files with 10761 additions and 1189 deletions
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13
arch/arm/Kconfig
View File

@ -518,6 +518,13 @@ config ARCH_S3C2410
BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
the Samsung SMDK2410 development board (and derivatives).
config ARCH_S3C64XX
bool "Samsung S3C64XX"
select GENERIC_GPIO
select HAVE_CLK
help
Samsung S3C64XX series based systems
config ARCH_SHARK
bool "Shark"
select CPU_SA110
@ -621,6 +628,7 @@ source "arch/arm/mach-orion5x/Kconfig"
source "arch/arm/mach-kirkwood/Kconfig"
source "arch/arm/plat-s3c24xx/Kconfig"
source "arch/arm/plat-s3c64xx/Kconfig"
source "arch/arm/plat-s3c/Kconfig"
if ARCH_S3C2410
@ -632,6 +640,11 @@ source "arch/arm/mach-s3c2442/Kconfig"
source "arch/arm/mach-s3c2443/Kconfig"
endif
if ARCH_S3C64XX
source "arch/arm/mach-s3c6400/Kconfig"
source "arch/arm/mach-s3c6410/Kconfig"
endif
source "arch/arm/mach-lh7a40x/Kconfig"
source "arch/arm/mach-imx/Kconfig"

3
arch/arm/Makefile
View File

@ -121,7 +121,10 @@ endif
machine-$(CONFIG_ARCH_OMAP3) := omap2
plat-$(CONFIG_ARCH_OMAP) := omap
machine-$(CONFIG_ARCH_S3C2410) := s3c2410 s3c2400 s3c2412 s3c2440 s3c2442 s3c2443
machine-$(CONFIG_ARCH_S3C24A0) := s3c24a0
plat-$(CONFIG_PLAT_S3C24XX) := s3c24xx s3c
machine-$(CONFIG_ARCH_S3C64XX) := s3c6400 s3c6410
plat-$(CONFIG_PLAT_S3C64XX) := s3c64xx s3c
machine-$(CONFIG_ARCH_LH7A40X) := lh7a40x
machine-$(CONFIG_ARCH_VERSATILE) := versatile
machine-$(CONFIG_ARCH_IMX) := imx

8
arch/arm/common/vic.c
View File

@ -69,12 +69,12 @@ void __init vic_init(void __iomem *base, unsigned int irq_start,
/*
* Make sure we clear all existing interrupts
*/
writel(0, base + VIC_VECT_ADDR);
writel(0, base + VIC_PL190_VECT_ADDR);
for (i = 0; i < 19; i++) {
unsigned int value;
value = readl(base + VIC_VECT_ADDR);
writel(value, base + VIC_VECT_ADDR);
value = readl(base + VIC_PL190_VECT_ADDR);
writel(value, base + VIC_PL190_VECT_ADDR);
}
for (i = 0; i < 16; i++) {
@ -82,7 +82,7 @@ void __init vic_init(void __iomem *base, unsigned int irq_start,
writel(VIC_VECT_CNTL_ENABLE | i, reg);
}
writel(32, base + VIC_DEF_VECT_ADDR);
writel(32, base + VIC_PL190_DEF_VECT_ADDR);
for (i = 0; i < 32; i++) {
unsigned int irq = irq_start + i;

845
arch/arm/configs/s3c6400_defconfig Normal file
View File

@ -0,0 +1,845 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.28-rc3
# Mon Nov 3 10:10:30 2008
#
CONFIG_ARM=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
CONFIG_GENERIC_GPIO=y
# CONFIG_GENERIC_TIME is not set
# CONFIG_GENERIC_CLOCKEVENTS is not set
CONFIG_MMU=y
CONFIG_NO_IOPORT=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_HAVE_LATENCYTOP_SUPPORT=y
CONFIG_LOCKDEP_SUPPORT=y
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
# CONFIG_ARCH_HAS_ILOG2_U32 is not set
# CONFIG_ARCH_HAS_ILOG2_U64 is not set
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
CONFIG_VECTORS_BASE=0xffff0000
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
#
# General setup
#
CONFIG_EXPERIMENTAL=y
CONFIG_BROKEN_ON_SMP=y
CONFIG_INIT_ENV_ARG_LIMIT=32
CONFIG_LOCALVERSION=""
CONFIG_LOCALVERSION_AUTO=y
CONFIG_SWAP=y
# CONFIG_SYSVIPC is not set
# CONFIG_BSD_PROCESS_ACCT is not set
# CONFIG_IKCONFIG is not set
CONFIG_LOG_BUF_SHIFT=17
# CONFIG_CGROUPS is not set
# CONFIG_GROUP_SCHED is not set
CONFIG_SYSFS_DEPRECATED=y
CONFIG_SYSFS_DEPRECATED_V2=y
# CONFIG_RELAY is not set
CONFIG_NAMESPACES=y
# CONFIG_UTS_NS is not set
# CONFIG_USER_NS is not set
# CONFIG_PID_NS is not set
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_SYSCTL=y
# CONFIG_EMBEDDED is not set
CONFIG_UID16=y
CONFIG_SYSCTL_SYSCALL=y
CONFIG_KALLSYMS=y
CONFIG_KALLSYMS_ALL=y
# CONFIG_KALLSYMS_EXTRA_PASS is not set
CONFIG_HOTPLUG=y
CONFIG_PRINTK=y
CONFIG_BUG=y
CONFIG_ELF_CORE=y
CONFIG_COMPAT_BRK=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_ANON_INODES=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_AIO=y
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_SLUB_DEBUG=y
# CONFIG_SLAB is not set
CONFIG_SLUB=y
# CONFIG_SLOB is not set
# CONFIG_PROFILING is not set
# CONFIG_MARKERS is not set
CONFIG_HAVE_OPROFILE=y
# CONFIG_KPROBES is not set
CONFIG_HAVE_KPROBES=y
CONFIG_HAVE_KRETPROBES=y
CONFIG_HAVE_CLK=y
CONFIG_HAVE_GENERIC_DMA_COHERENT=y
CONFIG_SLABINFO=y
CONFIG_RT_MUTEXES=y
# CONFIG_TINY_SHMEM is not set
CONFIG_BASE_SMALL=0
CONFIG_MODULES=y
# CONFIG_MODULE_FORCE_LOAD is not set
CONFIG_MODULE_UNLOAD=y
# CONFIG_MODULE_FORCE_UNLOAD is not set
# CONFIG_MODVERSIONS is not set
# CONFIG_MODULE_SRCVERSION_ALL is not set
CONFIG_KMOD=y
CONFIG_BLOCK=y
CONFIG_LBD=y
# CONFIG_BLK_DEV_IO_TRACE is not set
CONFIG_LSF=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_BLK_DEV_INTEGRITY is not set
#
# IO Schedulers
#
CONFIG_IOSCHED_NOOP=y
CONFIG_IOSCHED_AS=y
CONFIG_IOSCHED_DEADLINE=y
CONFIG_IOSCHED_CFQ=y
# CONFIG_DEFAULT_AS is not set
# CONFIG_DEFAULT_DEADLINE is not set
CONFIG_DEFAULT_CFQ=y
# CONFIG_DEFAULT_NOOP is not set
CONFIG_DEFAULT_IOSCHED="cfq"
CONFIG_CLASSIC_RCU=y
# CONFIG_FREEZER is not set
#
# System Type
#
# CONFIG_ARCH_AAEC2000 is not set
# CONFIG_ARCH_INTEGRATOR is not set
# CONFIG_ARCH_REALVIEW is not set
# CONFIG_ARCH_VERSATILE is not set
# CONFIG_ARCH_AT91 is not set
# CONFIG_ARCH_CLPS7500 is not set
# CONFIG_ARCH_CLPS711X is not set
# CONFIG_ARCH_EBSA110 is not set
# CONFIG_ARCH_EP93XX is not set
# CONFIG_ARCH_FOOTBRIDGE is not set
# CONFIG_ARCH_NETX is not set
# CONFIG_ARCH_H720X is not set
# CONFIG_ARCH_IMX is not set
# CONFIG_ARCH_IOP13XX is not set
# CONFIG_ARCH_IOP32X is not set
# CONFIG_ARCH_IOP33X is not set
# CONFIG_ARCH_IXP23XX is not set
# CONFIG_ARCH_IXP2000 is not set
# CONFIG_ARCH_IXP4XX is not set
# CONFIG_ARCH_L7200 is not set
# CONFIG_ARCH_KIRKWOOD is not set
# CONFIG_ARCH_KS8695 is not set
# CONFIG_ARCH_NS9XXX is not set
# CONFIG_ARCH_LOKI is not set
# CONFIG_ARCH_MV78XX0 is not set
# CONFIG_ARCH_MXC is not set
# CONFIG_ARCH_ORION5X is not set
# CONFIG_ARCH_PNX4008 is not set
# CONFIG_ARCH_PXA is not set
# CONFIG_ARCH_RPC is not set
# CONFIG_ARCH_SA1100 is not set
# CONFIG_ARCH_S3C2410 is not set
CONFIG_ARCH_S3C64XX=y
# CONFIG_ARCH_SHARK is not set
# CONFIG_ARCH_LH7A40X is not set
# CONFIG_ARCH_DAVINCI is not set
# CONFIG_ARCH_OMAP is not set
# CONFIG_ARCH_MSM is not set
CONFIG_PLAT_S3C64XX=y
CONFIG_CPU_S3C6400_INIT=y
CONFIG_CPU_S3C6400_CLOCK=y
CONFIG_S3C64XX_SETUP_I2C0=y
CONFIG_S3C64XX_SETUP_I2C1=y
CONFIG_PLAT_S3C=y
#
# Boot options
#
CONFIG_S3C_BOOT_ERROR_RESET=y
#
# Power management
#
CONFIG_S3C_LOWLEVEL_UART_PORT=0
CONFIG_S3C_GPIO_SPACE=0
CONFIG_S3C_GPIO_TRACK=y
CONFIG_S3C_GPIO_PULL_UPDOWN=y
CONFIG_S3C_GPIO_CFG_S3C24XX=y
CONFIG_S3C_GPIO_CFG_S3C64XX=y
CONFIG_S3C_DEV_HSMMC=y
CONFIG_S3C_DEV_HSMMC1=y
CONFIG_S3C_DEV_I2C1=y
CONFIG_CPU_S3C6410=y
CONFIG_S3C6410_SETUP_SDHCI=y
CONFIG_MACH_SMDK6410=y
CONFIG_SMDK6410_SD_CH0=y
# CONFIG_SMDK6410_SD_CH1 is not set
#
# Processor Type
#
CONFIG_CPU_32=y
CONFIG_CPU_V6=y
CONFIG_CPU_32v6K=y
CONFIG_CPU_32v6=y
CONFIG_CPU_ABRT_EV6=y
CONFIG_CPU_PABRT_NOIFAR=y
CONFIG_CPU_CACHE_V6=y
CONFIG_CPU_CACHE_VIPT=y
CONFIG_CPU_COPY_V6=y
CONFIG_CPU_TLB_V6=y
CONFIG_CPU_HAS_ASID=y
CONFIG_CPU_CP15=y
CONFIG_CPU_CP15_MMU=y
#
# Processor Features
#
CONFIG_ARM_THUMB=y
# CONFIG_CPU_ICACHE_DISABLE is not set
# CONFIG_CPU_DCACHE_DISABLE is not set
# CONFIG_CPU_BPREDICT_DISABLE is not set
# CONFIG_OUTER_CACHE is not set
CONFIG_ARM_VIC=y
#
# Bus support
#
# CONFIG_PCI_SYSCALL is not set
# CONFIG_ARCH_SUPPORTS_MSI is not set
# CONFIG_PCCARD is not set
#
# Kernel Features
#
CONFIG_VMSPLIT_3G=y
# CONFIG_VMSPLIT_2G is not set
# CONFIG_VMSPLIT_1G is not set
CONFIG_PAGE_OFFSET=0xC0000000
# CONFIG_PREEMPT is not set
CONFIG_HZ=100
CONFIG_AEABI=y
CONFIG_OABI_COMPAT=y
CONFIG_ARCH_FLATMEM_HAS_HOLES=y
# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
CONFIG_SELECT_MEMORY_MODEL=y
CONFIG_FLATMEM_MANUAL=y
# CONFIG_DISCONTIGMEM_MANUAL is not set
# CONFIG_SPARSEMEM_MANUAL is not set
CONFIG_FLATMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y
CONFIG_PAGEFLAGS_EXTENDED=y
CONFIG_SPLIT_PTLOCK_CPUS=4
# CONFIG_RESOURCES_64BIT is not set
# CONFIG_PHYS_ADDR_T_64BIT is not set
CONFIG_ZONE_DMA_FLAG=0
CONFIG_VIRT_TO_BUS=y
CONFIG_UNEVICTABLE_LRU=y
CONFIG_ALIGNMENT_TRAP=y
#
# Boot options
#
CONFIG_ZBOOT_ROM_TEXT=0
CONFIG_ZBOOT_ROM_BSS=0
CONFIG_CMDLINE="console=ttySAC0,115200 root=/dev/ram init=/bin/bash initrd=0x51000000,4M"
# CONFIG_XIP_KERNEL is not set
# CONFIG_KEXEC is not set
#
# CPU Power Management
#
# CONFIG_CPU_IDLE is not set
#
# Floating point emulation
#
#
# At least one emulation must be selected
#
# CONFIG_FPE_NWFPE is not set
# CONFIG_FPE_FASTFPE is not set
CONFIG_VFP=y
#
# Userspace binary formats
#
CONFIG_BINFMT_ELF=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
CONFIG_HAVE_AOUT=y
# CONFIG_BINFMT_AOUT is not set
# CONFIG_BINFMT_MISC is not set
#
# Power management options
#
# CONFIG_PM is not set
CONFIG_ARCH_SUSPEND_POSSIBLE=y
# CONFIG_NET is not set
#
# Device Drivers
#
#
# Generic Driver Options
#
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
CONFIG_FW_LOADER=y
CONFIG_FIRMWARE_IN_KERNEL=y
CONFIG_EXTRA_FIRMWARE=""
# CONFIG_DEBUG_DRIVER is not set
# CONFIG_DEBUG_DEVRES is not set
# CONFIG_SYS_HYPERVISOR is not set
# CONFIG_MTD is not set
# CONFIG_PARPORT is not set
CONFIG_BLK_DEV=y
# CONFIG_BLK_DEV_COW_COMMON is not set
CONFIG_BLK_DEV_LOOP=y
# CONFIG_BLK_DEV_CRYPTOLOOP is not set
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=16
CONFIG_BLK_DEV_RAM_SIZE=4096
# CONFIG_BLK_DEV_XIP is not set
# CONFIG_CDROM_PKTCDVD is not set
CONFIG_MISC_DEVICES=y
# CONFIG_EEPROM_93CX6 is not set
# CONFIG_ENCLOSURE_SERVICES is not set
CONFIG_HAVE_IDE=y
# CONFIG_IDE is not set
#
# SCSI device support
#
# CONFIG_RAID_ATTRS is not set
# CONFIG_SCSI is not set
# CONFIG_SCSI_DMA is not set
# CONFIG_SCSI_NETLINK is not set
# CONFIG_ATA is not set
# CONFIG_MD is not set
#
# Input device support
#
CONFIG_INPUT=y
# CONFIG_INPUT_FF_MEMLESS is not set
# CONFIG_INPUT_POLLDEV is not set
#
# Userland interfaces
#
CONFIG_INPUT_MOUSEDEV=y
CONFIG_INPUT_MOUSEDEV_PSAUX=y
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
# CONFIG_INPUT_JOYDEV is not set
# CONFIG_INPUT_EVDEV is not set
# CONFIG_INPUT_EVBUG is not set
#
# Input Device Drivers
#
CONFIG_INPUT_KEYBOARD=y
CONFIG_KEYBOARD_ATKBD=y
# CONFIG_KEYBOARD_SUNKBD is not set
# CONFIG_KEYBOARD_LKKBD is not set
# CONFIG_KEYBOARD_XTKBD is not set
# CONFIG_KEYBOARD_NEWTON is not set
# CONFIG_KEYBOARD_STOWAWAY is not set
# CONFIG_KEYBOARD_GPIO is not set
CONFIG_INPUT_MOUSE=y
CONFIG_MOUSE_PS2=y
CONFIG_MOUSE_PS2_ALPS=y
CONFIG_MOUSE_PS2_LOGIPS2PP=y
CONFIG_MOUSE_PS2_SYNAPTICS=y
CONFIG_MOUSE_PS2_LIFEBOOK=y
CONFIG_MOUSE_PS2_TRACKPOINT=y
# CONFIG_MOUSE_PS2_ELANTECH is not set
# CONFIG_MOUSE_PS2_TOUCHKIT is not set
# CONFIG_MOUSE_SERIAL is not set
# CONFIG_MOUSE_APPLETOUCH is not set
# CONFIG_MOUSE_BCM5974 is not set
# CONFIG_MOUSE_VSXXXAA is not set
# CONFIG_MOUSE_GPIO is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TABLET is not set
# CONFIG_INPUT_TOUCHSCREEN is not set
# CONFIG_INPUT_MISC is not set
#
# Hardware I/O ports
#
CONFIG_SERIO=y
CONFIG_SERIO_SERPORT=y
CONFIG_SERIO_LIBPS2=y
# CONFIG_SERIO_RAW is not set
# CONFIG_GAMEPORT is not set
#
# Character devices
#
CONFIG_VT=y
CONFIG_CONSOLE_TRANSLATIONS=y
CONFIG_VT_CONSOLE=y
CONFIG_HW_CONSOLE=y
# CONFIG_VT_HW_CONSOLE_BINDING is not set
CONFIG_DEVKMEM=y
# CONFIG_SERIAL_NONSTANDARD is not set
#
# Serial drivers
#
CONFIG_SERIAL_8250=y
# CONFIG_SERIAL_8250_CONSOLE is not set
CONFIG_SERIAL_8250_NR_UARTS=4
CONFIG_SERIAL_8250_RUNTIME_UARTS=4
# CONFIG_SERIAL_8250_EXTENDED is not set
#
# Non-8250 serial port support
#
CONFIG_SERIAL_SAMSUNG=y
CONFIG_SERIAL_SAMSUNG_UARTS=4
# CONFIG_SERIAL_SAMSUNG_DEBUG is not set
CONFIG_SERIAL_SAMSUNG_CONSOLE=y
CONFIG_SERIAL_S3C6400=y
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
CONFIG_UNIX98_PTYS=y
CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=256
# CONFIG_IPMI_HANDLER is not set
CONFIG_HW_RANDOM=y
# CONFIG_NVRAM is not set
# CONFIG_R3964 is not set
# CONFIG_RAW_DRIVER is not set
# CONFIG_TCG_TPM is not set
CONFIG_I2C=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_HELPER_AUTO=y
#
# I2C Hardware Bus support
#
#
# I2C system bus drivers (mostly embedded / system-on-chip)
#
# CONFIG_I2C_GPIO is not set
# CONFIG_I2C_OCORES is not set
CONFIG_I2C_S3C2410=y
# CONFIG_I2C_SIMTEC is not set
#
# External I2C/SMBus adapter drivers
#
# CONFIG_I2C_PARPORT_LIGHT is not set
# CONFIG_I2C_TAOS_EVM is not set
#
# Other I2C/SMBus bus drivers
#
# CONFIG_I2C_PCA_PLATFORM is not set
# CONFIG_I2C_STUB is not set
#
# Miscellaneous I2C Chip support
#
# CONFIG_DS1682 is not set
CONFIG_AT24=y
# CONFIG_SENSORS_EEPROM is not set
# CONFIG_SENSORS_PCF8574 is not set
# CONFIG_PCF8575 is not set
# CONFIG_SENSORS_PCA9539 is not set
# CONFIG_SENSORS_PCF8591 is not set
# CONFIG_TPS65010 is not set
# CONFIG_SENSORS_MAX6875 is not set
# CONFIG_SENSORS_TSL2550 is not set
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
# CONFIG_I2C_DEBUG_BUS is not set
# CONFIG_I2C_DEBUG_CHIP is not set
# CONFIG_SPI is not set
CONFIG_ARCH_REQUIRE_GPIOLIB=y
CONFIG_GPIOLIB=y
# CONFIG_DEBUG_GPIO is not set
# CONFIG_GPIO_SYSFS is not set
#
# I2C GPIO expanders:
#
# CONFIG_GPIO_MAX732X is not set
# CONFIG_GPIO_PCA953X is not set
# CONFIG_GPIO_PCF857X is not set
#
# PCI GPIO expanders:
#
#
# SPI GPIO expanders:
#
# CONFIG_W1 is not set
# CONFIG_POWER_SUPPLY is not set
CONFIG_HWMON=y
# CONFIG_HWMON_VID is not set
# CONFIG_SENSORS_AD7414 is not set
# CONFIG_SENSORS_AD7418 is not set
# CONFIG_SENSORS_ADM1021 is not set
# CONFIG_SENSORS_ADM1025 is not set
# CONFIG_SENSORS_ADM1026 is not set
# CONFIG_SENSORS_ADM1029 is not set
# CONFIG_SENSORS_ADM1031 is not set
# CONFIG_SENSORS_ADM9240 is not set
# CONFIG_SENSORS_ADT7470 is not set
# CONFIG_SENSORS_ADT7473 is not set
# CONFIG_SENSORS_ATXP1 is not set
# CONFIG_SENSORS_DS1621 is not set
# CONFIG_SENSORS_F71805F is not set
# CONFIG_SENSORS_F71882FG is not set
# CONFIG_SENSORS_F75375S is not set
# CONFIG_SENSORS_GL518SM is not set
# CONFIG_SENSORS_GL520SM is not set
# CONFIG_SENSORS_IT87 is not set
# CONFIG_SENSORS_LM63 is not set
# CONFIG_SENSORS_LM75 is not set
# CONFIG_SENSORS_LM77 is not set
# CONFIG_SENSORS_LM78 is not set
# CONFIG_SENSORS_LM80 is not set
# CONFIG_SENSORS_LM83 is not set
# CONFIG_SENSORS_LM85 is not set
# CONFIG_SENSORS_LM87 is not set
# CONFIG_SENSORS_LM90 is not set
# CONFIG_SENSORS_LM92 is not set
# CONFIG_SENSORS_LM93 is not set
# CONFIG_SENSORS_MAX1619 is not set
# CONFIG_SENSORS_MAX6650 is not set
# CONFIG_SENSORS_PC87360 is not set
# CONFIG_SENSORS_PC87427 is not set
# CONFIG_SENSORS_DME1737 is not set
# CONFIG_SENSORS_SMSC47M1 is not set
# CONFIG_SENSORS_SMSC47M192 is not set
# CONFIG_SENSORS_SMSC47B397 is not set
# CONFIG_SENSORS_ADS7828 is not set
# CONFIG_SENSORS_THMC50 is not set
# CONFIG_SENSORS_VT1211 is not set
# CONFIG_SENSORS_W83781D is not set
# CONFIG_SENSORS_W83791D is not set
# CONFIG_SENSORS_W83792D is not set
# CONFIG_SENSORS_W83793 is not set
# CONFIG_SENSORS_W83L785TS is not set
# CONFIG_SENSORS_W83L786NG is not set
# CONFIG_SENSORS_W83627HF is not set
# CONFIG_SENSORS_W83627EHF is not set
# CONFIG_HWMON_DEBUG_CHIP is not set
# CONFIG_THERMAL is not set
# CONFIG_THERMAL_HWMON is not set
# CONFIG_WATCHDOG is not set
#
# Sonics Silicon Backplane
#
CONFIG_SSB_POSSIBLE=y
# CONFIG_SSB is not set
#
# Multifunction device drivers
#
# CONFIG_MFD_CORE is not set
# CONFIG_MFD_SM501 is not set
# CONFIG_MFD_ASIC3 is not set
# CONFIG_HTC_EGPIO is not set
# CONFIG_HTC_PASIC3 is not set
# CONFIG_MFD_TMIO is not set
# CONFIG_MFD_T7L66XB is not set
# CONFIG_MFD_TC6387XB is not set
# CONFIG_MFD_TC6393XB is not set
# CONFIG_PMIC_DA903X is not set
# CONFIG_MFD_WM8400 is not set
# CONFIG_MFD_WM8350_I2C is not set
#
# Multimedia devices
#
#
# Multimedia core support
#
# CONFIG_VIDEO_DEV is not set
# CONFIG_VIDEO_MEDIA is not set
#
# Multimedia drivers
#
# CONFIG_DAB is not set
#
# Graphics support
#
# CONFIG_VGASTATE is not set
# CONFIG_VIDEO_OUTPUT_CONTROL is not set
# CONFIG_FB is not set
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
#
# Display device support
#
# CONFIG_DISPLAY_SUPPORT is not set
#
# Console display driver support
#
# CONFIG_VGA_CONSOLE is not set
CONFIG_DUMMY_CONSOLE=y
# CONFIG_SOUND is not set
CONFIG_HID_SUPPORT=y
CONFIG_HID=y
CONFIG_HID_DEBUG=y
# CONFIG_HIDRAW is not set
# CONFIG_HID_PID is not set
#
# Special HID drivers
#
# CONFIG_HID_COMPAT is not set
CONFIG_USB_SUPPORT=y
CONFIG_USB_ARCH_HAS_HCD=y
# CONFIG_USB_ARCH_HAS_OHCI is not set
# CONFIG_USB_ARCH_HAS_EHCI is not set
# CONFIG_USB is not set
#
# Enable Host or Gadget support to see Inventra options
#
#
# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
#
# CONFIG_USB_GADGET is not set
CONFIG_MMC=y
CONFIG_MMC_DEBUG=y
CONFIG_MMC_UNSAFE_RESUME=y
#
# MMC/SD/SDIO Card Drivers
#
CONFIG_MMC_BLOCK=y
CONFIG_MMC_BLOCK_BOUNCE=y
CONFIG_SDIO_UART=y
# CONFIG_MMC_TEST is not set
#
# MMC/SD/SDIO Host Controller Drivers
#
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_S3C=y
# CONFIG_MEMSTICK is not set
# CONFIG_ACCESSIBILITY is not set
# CONFIG_NEW_LEDS is not set
CONFIG_RTC_LIB=y
# CONFIG_RTC_CLASS is not set
# CONFIG_DMADEVICES is not set
#
# Voltage and Current regulators
#
# CONFIG_REGULATOR is not set
# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
# CONFIG_REGULATOR_BQ24022 is not set
# CONFIG_UIO is not set
#
# File systems
#
CONFIG_EXT2_FS=y
# CONFIG_EXT2_FS_XATTR is not set
# CONFIG_EXT2_FS_XIP is not set
CONFIG_EXT3_FS=y
CONFIG_EXT3_FS_XATTR=y
CONFIG_EXT3_FS_POSIX_ACL=y
CONFIG_EXT3_FS_SECURITY=y
# CONFIG_EXT4_FS is not set
CONFIG_JBD=y
CONFIG_FS_MBCACHE=y
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
CONFIG_FS_POSIX_ACL=y
CONFIG_FILE_LOCKING=y
# CONFIG_XFS_FS is not set
# CONFIG_GFS2_FS is not set
CONFIG_DNOTIFY=y
CONFIG_INOTIFY=y
CONFIG_INOTIFY_USER=y
# CONFIG_QUOTA is not set
# CONFIG_AUTOFS_FS is not set
# CONFIG_AUTOFS4_FS is not set
# CONFIG_FUSE_FS is not set
CONFIG_GENERIC_ACL=y
#
# CD-ROM/DVD Filesystems
#
# CONFIG_ISO9660_FS is not set
# CONFIG_UDF_FS is not set
#
# DOS/FAT/NT Filesystems
#
# CONFIG_MSDOS_FS is not set
# CONFIG_VFAT_FS is not set
# CONFIG_NTFS_FS is not set
#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
CONFIG_PROC_SYSCTL=y
CONFIG_PROC_PAGE_MONITOR=y
CONFIG_SYSFS=y
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
# CONFIG_HUGETLB_PAGE is not set
# CONFIG_CONFIGFS_FS is not set
#
# Miscellaneous filesystems
#
# CONFIG_ADFS_FS is not set
# CONFIG_AFFS_FS is not set
# CONFIG_HFS_FS is not set
# CONFIG_HFSPLUS_FS is not set
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
CONFIG_CRAMFS=y
# CONFIG_VXFS_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_OMFS_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
CONFIG_ROMFS_FS=y
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
#
# Partition Types
#
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_MSDOS_PARTITION=y
# CONFIG_NLS is not set
#
# Kernel hacking
#
# CONFIG_PRINTK_TIME is not set
CONFIG_ENABLE_WARN_DEPRECATED=y
CONFIG_ENABLE_MUST_CHECK=y
CONFIG_FRAME_WARN=1024
CONFIG_MAGIC_SYSRQ=y
# CONFIG_UNUSED_SYMBOLS is not set
# CONFIG_DEBUG_FS is not set
# CONFIG_HEADERS_CHECK is not set
CONFIG_DEBUG_KERNEL=y
# CONFIG_DEBUG_SHIRQ is not set
CONFIG_DETECT_SOFTLOCKUP=y
# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
CONFIG_SCHED_DEBUG=y
# CONFIG_SCHEDSTATS is not set
# CONFIG_TIMER_STATS is not set
# CONFIG_DEBUG_OBJECTS is not set
# CONFIG_SLUB_DEBUG_ON is not set
# CONFIG_SLUB_STATS is not set
CONFIG_DEBUG_RT_MUTEXES=y
CONFIG_DEBUG_PI_LIST=y
# CONFIG_RT_MUTEX_TESTER is not set
CONFIG_DEBUG_SPINLOCK=y
CONFIG_DEBUG_MUTEXES=y
# CONFIG_DEBUG_LOCK_ALLOC is not set
# CONFIG_PROVE_LOCKING is not set
# CONFIG_LOCK_STAT is not set
CONFIG_DEBUG_SPINLOCK_SLEEP=y
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
# CONFIG_DEBUG_KOBJECT is not set
CONFIG_DEBUG_BUGVERBOSE=y
CONFIG_DEBUG_INFO=y
# CONFIG_DEBUG_VM is not set
# CONFIG_DEBUG_WRITECOUNT is not set
CONFIG_DEBUG_MEMORY_INIT=y
# CONFIG_DEBUG_LIST is not set
# CONFIG_DEBUG_SG is not set
CONFIG_FRAME_POINTER=y
# CONFIG_BOOT_PRINTK_DELAY is not set
# CONFIG_RCU_TORTURE_TEST is not set
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
# CONFIG_BACKTRACE_SELF_TEST is not set
# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
# CONFIG_FAULT_INJECTION is not set
# CONFIG_LATENCYTOP is not set
CONFIG_SYSCTL_SYSCALL_CHECK=y
CONFIG_HAVE_FUNCTION_TRACER=y
#
# Tracers
#
# CONFIG_FUNCTION_TRACER is not set
# CONFIG_SCHED_TRACER is not set
# CONFIG_CONTEXT_SWITCH_TRACER is not set
# CONFIG_BOOT_TRACER is not set
# CONFIG_STACK_TRACER is not set
# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
# CONFIG_SAMPLES is not set
CONFIG_HAVE_ARCH_KGDB=y
# CONFIG_KGDB is not set
CONFIG_DEBUG_USER=y
CONFIG_DEBUG_ERRORS=y
# CONFIG_DEBUG_STACK_USAGE is not set
CONFIG_DEBUG_LL=y
# CONFIG_DEBUG_ICEDCC is not set
CONFIG_DEBUG_S3C_PORT=y
CONFIG_DEBUG_S3C_UART=0
#
# Security options
#
# CONFIG_KEYS is not set
# CONFIG_SECURITY is not set
# CONFIG_SECURITYFS is not set
# CONFIG_SECURITY_FILE_CAPABILITIES is not set
# CONFIG_CRYPTO is not set
#
# Library routines
#
CONFIG_BITREVERSE=y
# CONFIG_CRC_CCITT is not set
# CONFIG_CRC16 is not set
# CONFIG_CRC_T10DIF is not set
# CONFIG_CRC_ITU_T is not set
CONFIG_CRC32=y
# CONFIG_CRC7 is not set
# CONFIG_LIBCRC32C is not set
CONFIG_ZLIB_INFLATE=y
CONFIG_PLIST=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_DMA=y

10
arch/arm/include/asm/hardware/vic.h
View File

@ -29,15 +29,17 @@
#define VIC_INT_SOFT 0x18
#define VIC_INT_SOFT_CLEAR 0x1c
#define VIC_PROTECT 0x20
#define VIC_VECT_ADDR 0x30
#define VIC_DEF_VECT_ADDR 0x34
#define VIC_PL190_VECT_ADDR 0x30 /* PL190 only */
#define VIC_PL190_DEF_VECT_ADDR 0x34 /* PL190 only */
#define VIC_VECT_ADDR0 0x100 /* 0 to 15 */
#define VIC_VECT_CNTL0 0x200 /* 0 to 15 */
#define VIC_VECT_ADDR0 0x100 /* 0 to 15 (0..31 PL192) */
#define VIC_VECT_CNTL0 0x200 /* 0 to 15 (0..31 PL192) */
#define VIC_ITCR 0x300 /* VIC test control register */
#define VIC_VECT_CNTL_ENABLE (1 << 5)
#define VIC_PL192_VECT_ADDR 0xF00
#ifndef __ASSEMBLY__
void vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources);
#endif

7
arch/arm/mach-s3c2410/Kconfig
View File

@ -33,11 +33,6 @@ config S3C2410_GPIO
help
GPIO code for S3C2410 and similar processors
config S3C2410_CLOCK
bool
help
Clock code for the S3C2410, and similar processors
config SIMTEC_NOR
bool
help
@ -85,6 +80,7 @@ config ARCH_BAST
select PM_SIMTEC if PM
select SIMTEC_NOR
select MACH_BAST_IDE
select S3C24XX_DCLK
select ISA
help
Say Y here if you are using the Simtec Electronics EB2410ITX
@ -122,6 +118,7 @@ config MACH_TCT_HAMMER
config MACH_VR1000
bool "Thorcom VR1000"
select PM_SIMTEC if PM
select S3C24XX_DCLK
select SIMTEC_NOR
select MACH_BAST_IDE
select CPU_S3C2410

1
arch/arm/mach-s3c2410/Makefile
View File

@ -15,7 +15,6 @@ obj-$(CONFIG_CPU_S3C2410_DMA) += dma.o
obj-$(CONFIG_CPU_S3C2410_DMA) += dma.o
obj-$(CONFIG_S3C2410_PM) += pm.o sleep.o
obj-$(CONFIG_S3C2410_GPIO) += gpio.o
obj-$(CONFIG_S3C2410_CLOCK) += clock.o
# Machine support

34
arch/arm/mach-s3c2410/include/mach/gpio-core.h Normal file
View File

@ -0,0 +1,34 @@
/* arch/arm/mach-s3c24100/include/mach/gpio-core.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C2410 - GPIO core support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_GPIO_CORE_H
#define __ASM_ARCH_GPIO_CORE_H __FILE__
#include <plat/gpio-core.h>
#include <mach/regs-gpio.h>
extern struct s3c_gpio_chip s3c24xx_gpios[];
static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int pin)
{
struct s3c_gpio_chip *chip;
if (pin > S3C2410_GPG10)
return NULL;
chip = &s3c24xx_gpios[pin/32];
return (S3C2410_GPIO_OFFSET(pin) > chip->chip.ngpio) ? chip : NULL;
}
#endif /* __ASM_ARCH_GPIO_CORE_H */

6
arch/arm/mach-s3c2410/include/mach/gpio.h
View File

@ -15,4 +15,10 @@
#define gpio_set_value __gpio_set_value
#define gpio_cansleep __gpio_cansleep
/* some boards require extra gpio capacity to support external
* devices that need GPIO.
*/
#define ARCH_NR_GPIOS (256 + CONFIG_S3C24XX_GPIO_EXTRA)
#include <asm-generic/gpio.h>

8
arch/arm/mach-s3c2410/include/mach/irqs.h
View File

@ -134,6 +134,8 @@
#define IRQ_S3C2443_HSMMC S3C2410_IRQ(20) /* IRQ_SDI */
#define IRQ_S3C2443_NAND S3C2410_IRQ(24) /* reserved */
#define IRQ_HSMMC0 IRQ_S3C2443_HSMMC
#define IRQ_S3C2443_LCD1 S3C2410_IRQSUB(14)
#define IRQ_S3C2443_LCD2 S3C2410_IRQSUB(15)
#define IRQ_S3C2443_LCD3 S3C2410_IRQSUB(16)
@ -160,6 +162,12 @@
#define NR_IRQS (IRQ_S3C2440_AC97+1)
#endif
/* compatibility define. */
#define IRQ_UART3 IRQ_S3C2443_UART3
#define IRQ_S3CUART_RX3 IRQ_S3C2443_RX3
#define IRQ_S3CUART_TX3 IRQ_S3C2443_TX3
#define IRQ_S3CUART_ERR3 IRQ_S3C2443_ERR3
/* Our FIQs are routable from IRQ_EINT0 to IRQ_ADCPARENT */
#define FIQ_START IRQ_EINT0

83
arch/arm/mach-s3c2410/include/mach/map.h
View File

@ -13,34 +13,20 @@
#ifndef __ASM_ARCH_MAP_H
#define __ASM_ARCH_MAP_H
#include <plat/map-base.h>
#include <plat/map.h>
#define S3C2410_ADDR(x) S3C_ADDR(x)
/* interrupt controller is the first thing we put in, to make
* the assembly code for the irq detection easier
*/
#define S3C24XX_VA_IRQ S3C_VA_IRQ
#define S3C2410_PA_IRQ (0x4A000000)
#define S3C24XX_SZ_IRQ SZ_1M
/* memory controller registers */
#define S3C24XX_VA_MEMCTRL S3C_VA_MEM
#define S3C2410_PA_MEMCTRL (0x48000000)
#define S3C24XX_SZ_MEMCTRL SZ_1M
/* USB host controller */
#define S3C2410_PA_USBHOST (0x49000000)
#define S3C24XX_SZ_USBHOST SZ_1M
/* DMA controller */
#define S3C2410_PA_DMA (0x4B000000)
#define S3C24XX_SZ_DMA SZ_1M
/* Clock and Power management */
#define S3C24XX_VA_CLKPWR S3C_VA_SYS
#define S3C2410_PA_CLKPWR (0x4C000000)
#define S3C24XX_SZ_CLKPWR SZ_1M
/* LCD controller */
#define S3C2410_PA_LCD (0x4D000000)
@ -48,48 +34,12 @@
/* NAND flash controller */
#define S3C2410_PA_NAND (0x4E000000)
#define S3C24XX_SZ_NAND SZ_1M
/* UARTs */
#define S3C24XX_VA_UART S3C_VA_UART
#define S3C2410_PA_UART (0x50000000)
#define S3C24XX_SZ_UART SZ_1M
/* Timers */
#define S3C24XX_VA_TIMER S3C_VA_TIMER
#define S3C2410_PA_TIMER (0x51000000)
#define S3C24XX_SZ_TIMER SZ_1M
/* USB Device port */
#define S3C2410_PA_USBDEV (0x52000000)
#define S3C24XX_SZ_USBDEV SZ_1M
/* Watchdog */
#define S3C24XX_VA_WATCHDOG S3C_VA_WATCHDOG
#define S3C2410_PA_WATCHDOG (0x53000000)
#define S3C24XX_SZ_WATCHDOG SZ_1M
/* IIC hardware controller */
#define S3C2410_PA_IIC (0x54000000)
#define S3C24XX_SZ_IIC SZ_1M
/* IIS controller */
#define S3C2410_PA_IIS (0x55000000)
#define S3C24XX_SZ_IIS SZ_1M
/* GPIO ports */
/* the calculation for the VA of this must ensure that
* it is the same distance apart from the UART in the
* phsyical address space, as the initial mapping for the IO
* is done as a 1:1 maping. This puts it (currently) at
* 0xFA800000, which is not in the way of any current mapping
* by the base system.
*/
#define S3C2410_PA_GPIO (0x56000000)
#define S3C24XX_VA_GPIO ((S3C2410_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART)
#define S3C24XX_SZ_GPIO SZ_1M
/* RTC */
#define S3C2410_PA_RTC (0x57000000)
@ -97,15 +47,12 @@
/* ADC */
#define S3C2410_PA_ADC (0x58000000)
#define S3C24XX_SZ_ADC SZ_1M
/* SPI */
#define S3C2410_PA_SPI (0x59000000)
#define S3C24XX_SZ_SPI SZ_1M
/* SDI */
#define S3C2410_PA_SDI (0x5A000000)
#define S3C24XX_SZ_SDI SZ_1M
/* CAMIF */
#define S3C2440_PA_CAMIF (0x4F000000)
@ -120,13 +67,6 @@
#define S3C2443_PA_HSMMC (0x4A800000)
#define S3C2443_SZ_HSMMC (256)
/* ISA style IO, for each machine to sort out mappings for, if it
* implements it. We reserve two 16M regions for ISA.
*/
#define S3C24XX_VA_ISA_WORD S3C2410_ADDR(0x02000000)
#define S3C24XX_VA_ISA_BYTE S3C2410_ADDR(0x03000000)
/* physical addresses of all the chip-select areas */
#define S3C2410_CS0 (0x00000000)
@ -152,27 +92,16 @@
#define S3C24XX_PA_TIMER S3C2410_PA_TIMER
#define S3C24XX_PA_USBDEV S3C2410_PA_USBDEV
#define S3C24XX_PA_WATCHDOG S3C2410_PA_WATCHDOG
#define S3C24XX_PA_IIC S3C2410_PA_IIC
#define S3C24XX_PA_IIS S3C2410_PA_IIS
#define S3C24XX_PA_GPIO S3C2410_PA_GPIO
#define S3C24XX_PA_RTC S3C2410_PA_RTC
#define S3C24XX_PA_ADC S3C2410_PA_ADC
#define S3C24XX_PA_SPI S3C2410_PA_SPI
#define S3C24XX_PA_SDI S3C2410_PA_SDI
#define S3C24XX_PA_NAND S3C2410_PA_NAND
/* deal with the registers that move under the 2412/2413 */
#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
#ifndef __ASSEMBLY__
extern void __iomem *s3c24xx_va_gpio2;
#endif
#ifdef CONFIG_CPU_S3C2412_ONLY
#define S3C24XX_VA_GPIO2 (S3C24XX_VA_GPIO + 0x10)
#else
#define S3C24XX_VA_GPIO2 s3c24xx_va_gpio2
#endif
#else
#define s3c24xx_va_gpio2 S3C24XX_VA_GPIO
#define S3C24XX_VA_GPIO2 S3C24XX_VA_GPIO
#endif
#define S3C_PA_IIC S3C2410_PA_IIC
#define S3C_PA_UART S3C24XX_PA_UART
#define S3C_PA_HSMMC0 S3C2443_PA_HSMMC
#endif /* __ASM_ARCH_MAP_H */

33
arch/arm/mach-s3c2410/include/mach/regs-clock.h
View File

@ -42,13 +42,6 @@
#define S3C2410_CLKCON_IIS (1<<17)
#define S3C2410_CLKCON_SPI (1<<18)
#define S3C2410_PLLCON_MDIVSHIFT 12
#define S3C2410_PLLCON_PDIVSHIFT 4
#define S3C2410_PLLCON_SDIVSHIFT 0
#define S3C2410_PLLCON_MDIVMASK ((1<<(1+(19-12)))-1)
#define S3C2410_PLLCON_PDIVMASK ((1<<5)-1)
#define S3C2410_PLLCON_SDIVMASK 3
/* DCLKCON register addresses in gpio.h */
#define S3C2410_DCLKCON_DCLK0EN (1<<0)
@ -76,32 +69,6 @@
#define S3C2410_CLKSLOW_SLOWVAL(x) (x)
#define S3C2410_CLKSLOW_GET_SLOWVAL(x) ((x) & 7)
#ifndef __ASSEMBLY__
#include <asm/div64.h>
static inline unsigned int
s3c2410_get_pll(unsigned int pllval, unsigned int baseclk)
{
unsigned int mdiv, pdiv, sdiv;
uint64_t fvco;
mdiv = pllval >> S3C2410_PLLCON_MDIVSHIFT;
pdiv = pllval >> S3C2410_PLLCON_PDIVSHIFT;
sdiv = pllval >> S3C2410_PLLCON_SDIVSHIFT;
mdiv &= S3C2410_PLLCON_MDIVMASK;
pdiv &= S3C2410_PLLCON_PDIVMASK;
sdiv &= S3C2410_PLLCON_SDIVMASK;
fvco = (uint64_t)baseclk * (mdiv + 8);
do_div(fvco, (pdiv + 2) << sdiv);
return (unsigned int)fvco;
}
#endif /* __ASSEMBLY__ */
#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
/* extra registers */

7
arch/arm/mach-s3c2410/include/mach/regs-gpio.h
View File

@ -1053,13 +1053,6 @@
#define S3C24XX_EXTINT1 S3C24XX_GPIOREG2(0x8C)
#define S3C24XX_EXTINT2 S3C24XX_GPIOREG2(0x90)
/* values for S3C2410_EXTINT0/1/2 */
#define S3C2410_EXTINT_LOWLEV (0x00)
#define S3C2410_EXTINT_HILEV (0x01)
#define S3C2410_EXTINT_FALLEDGE (0x02)
#define S3C2410_EXTINT_RISEEDGE (0x04)
#define S3C2410_EXTINT_BOTHEDGE (0x06)
/* interrupt filtering conrrol for EINT16..EINT23 */
#define S3C2410_EINFLT0 S3C2410_GPIOREG(0x94)
#define S3C2410_EINFLT1 S3C2410_GPIOREG(0x98)

7
arch/arm/mach-s3c2410/include/mach/spi.h
View File

@ -22,5 +22,12 @@ struct s3c2410_spi_info {
void (*set_cs)(struct s3c2410_spi_info *spi, int cs, int pol);
};
/* Standard setup / suspend routines for SPI GPIO pins. */
extern void s3c24xx_spi_gpiocfg_bus0_gpe11_12_13(struct s3c2410_spi_info *spi,
int enable);
extern void s3c24xx_spi_gpiocfg_bus1_gpg5_6_7(struct s3c2410_spi_info *spi,
int enable);
#endif /* __ASM_ARCH_SPI_H */

15
arch/arm/mach-s3c2410/include/mach/tick.h Normal file
View File

@ -0,0 +1,15 @@
/* linux/arch/arm/mach-s3c2410/include/mach/tick.h
*
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C2410 - timer tick support
*/
#define SRCPND_TIMER4 (1<<(IRQ_TIMER4 - IRQ_EINT0))
static inline int s3c24xx_ostimer_pending(void)
{
return __raw_readl(S3C2410_SRCPND) & SRCPND_TIMER4;
}

1
arch/arm/mach-s3c2410/include/mach/uncompress.h
View File

@ -1,3 +1,4 @@
/* arch/arm/mach-s3c2410/include/mach/uncompress.h
*
* Copyright (c) 2003, 2007 Simtec Electronics

4
arch/arm/mach-s3c2410/mach-amlm5900.c
View File

@ -52,6 +52,7 @@
#include <mach/regs-lcd.h>
#include <mach/regs-gpio.h>
#include <plat/iic.h>
#include <plat/devs.h>
#include <plat/cpu.h>
@ -150,7 +151,7 @@ static struct platform_device *amlm5900_devices[] __initdata = {
#endif
&s3c_device_adc,
&s3c_device_wdt,
&s3c_device_i2c,
&s3c_device_i2c0,
&s3c_device_usb,
&s3c_device_rtc,
&s3c_device_usbgadget,
@ -233,6 +234,7 @@ static void __init amlm5900_init(void)
#ifdef CONFIG_FB_S3C2410
s3c24xx_fb_set_platdata(&amlm5900_fb_info);
#endif
s3c_i2c0_set_platdata(NULL);
platform_add_devices(amlm5900_devices, ARRAY_SIZE(amlm5900_devices));
}

7
arch/arm/mach-s3c2410/mach-bast.c
View File

@ -406,7 +406,7 @@ static struct platform_device bast_sio = {
* standard 100KHz i2c bus frequency
*/
static struct s3c2410_platform_i2c bast_i2c_info = {
static struct s3c2410_platform_i2c __initdata bast_i2c_info = {
.flags = 0,
.slave_addr = 0x10,
.bus_freq = 100*1000,
@ -553,7 +553,7 @@ static struct platform_device *bast_devices[] __initdata = {
&s3c_device_usb,
&s3c_device_lcd,
&s3c_device_wdt,
&s3c_device_i2c,
&s3c_device_i2c0,
&s3c_device_rtc,
&s3c_device_nand,
&bast_device_dm9k,
@ -588,7 +588,8 @@ static void __init bast_map_io(void)
s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks));
s3c_device_nand.dev.platform_data = &bast_nand_info;
s3c_device_i2c.dev.platform_data = &bast_i2c_info;
s3c_i2c0_set_platdata(&bast_i2c_info);
s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
s3c24xx_init_clocks(0);

12
arch/arm/mach-s3c2410/mach-h1940.c
View File

@ -39,10 +39,12 @@
#include <mach/h1940-latch.h>
#include <mach/fb.h>
#include <plat/udc.h>
#include <plat/iic.h>
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#include <plat/pll.h>
#include <plat/pm.h>
static struct map_desc h1940_iodesc[] __initdata = {
@ -183,7 +185,7 @@ static struct platform_device *h1940_devices[] __initdata = {
&s3c_device_usb,
&s3c_device_lcd,
&s3c_device_wdt,
&s3c_device_i2c,
&s3c_device_i2c0,
&s3c_device_iis,
&s3c_device_usbgadget,
&s3c_device_leds,
@ -215,6 +217,7 @@ static void __init h1940_init(void)
s3c24xx_fb_set_platdata(&h1940_fb_info);
s3c24xx_udc_set_platdata(&h1940_udc_cfg);
s3c_i2c0_set_platdata(NULL);
/* Turn off suspend on both USB ports, and switch the
* selectable USB port to USB device mode. */
@ -223,10 +226,9 @@ static void __init h1940_init(void)
S3C2410_MISCCR_USBSUSPND0 |
S3C2410_MISCCR_USBSUSPND1, 0x0);
tmp = (
0x78 << S3C2410_PLLCON_MDIVSHIFT)
| (0x02 << S3C2410_PLLCON_PDIVSHIFT)
| (0x03 << S3C2410_PLLCON_SDIVSHIFT);
tmp = (0x78 << S3C24XX_PLLCON_MDIVSHIFT)
| (0x02 << S3C24XX_PLLCON_PDIVSHIFT)
| (0x03 << S3C24XX_PLLCON_SDIVSHIFT);
writel(tmp, S3C2410_UPLLCON);
platform_add_devices(h1940_devices, ARRAY_SIZE(h1940_devices));

7
arch/arm/mach-s3c2410/mach-n30.c
View File

@ -17,7 +17,6 @@
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/delay.h>
#include <linux/gpio_keys.h>
#include <linux/init.h>
#include <linux/input.h>
@ -320,7 +319,7 @@ static struct s3c2410fb_mach_info n30_fb_info __initdata = {
static struct platform_device *n30_devices[] __initdata = {
&s3c_device_lcd,
&s3c_device_wdt,
&s3c_device_i2c,
&s3c_device_i2c0,
&s3c_device_iis,
&s3c_device_usb,
&s3c_device_usbgadget,
@ -332,7 +331,7 @@ static struct platform_device *n30_devices[] __initdata = {
static struct platform_device *n35_devices[] __initdata = {
&s3c_device_lcd,
&s3c_device_wdt,
&s3c_device_i2c,
&s3c_device_i2c0,
&s3c_device_iis,
&s3c_device_usbgadget,
&n35_button_device,
@ -501,7 +500,7 @@ static void __init n30_init_irq(void)
static void __init n30_init(void)
{
s3c24xx_fb_set_platdata(&n30_fb_info);
s3c_device_i2c.dev.platform_data = &n30_i2ccfg;
s3c_device_i2c0.dev.platform_data = &n30_i2ccfg;
s3c24xx_udc_set_platdata(&n30_udc_cfg);
/* Turn off suspend on both USB ports, and switch the

4
arch/arm/mach-s3c2410/mach-otom.c
View File

@ -35,6 +35,7 @@
#include <plat/s3c2410.h>
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/iic.h>
#include <plat/cpu.h>
static struct map_desc otom11_iodesc[] __initdata = {
@ -94,7 +95,7 @@ static struct platform_device *otom11_devices[] __initdata = {
&s3c_device_usb,
&s3c_device_lcd,
&s3c_device_wdt,
&s3c_device_i2c,
&s3c_device_i2c0,
&s3c_device_iis,
&s3c_device_rtc,
&otom_device_nor,
@ -109,6 +110,7 @@ static void __init otom11_map_io(void)
static void __init otom11_init(void)
{
s3c_i2c0_set_platdata(NULL);
platform_add_devices(otom11_devices, ARRAY_SIZE(otom11_devices));
}

4
arch/arm/mach-s3c2410/mach-qt2410.c
View File

@ -54,6 +54,7 @@
#include <plat/udc.h>
#include <mach/spi.h>
#include <mach/spi-gpio.h>
#include <plat/iic.h>
#include <plat/common-smdk.h>
#include <plat/devs.h>
@ -247,7 +248,7 @@ static struct platform_device *qt2410_devices[] __initdata = {
&s3c_device_usb,
&s3c_device_lcd,
&s3c_device_wdt,
&s3c_device_i2c,
&s3c_device_i2c0,
&s3c_device_iis,
&s3c_device_sdi,
&s3c_device_usbgadget,
@ -349,6 +350,7 @@ static void __init qt2410_machine_init(void)
s3c2410_gpio_setpin(S3C2410_GPB0, 1);
s3c24xx_udc_set_platdata(&qt2410_udc_cfg);
s3c_i2c0_set_platdata(NULL);
s3c2410_gpio_cfgpin(S3C2410_GPB5, S3C2410_GPIO_OUTPUT);

4
arch/arm/mach-s3c2410/mach-smdk2410.c
View File

@ -47,6 +47,7 @@
#include <asm/mach-types.h>
#include <plat/regs-serial.h>
#include <plat/iic.h>
#include <plat/devs.h>
#include <plat/cpu.h>
@ -89,7 +90,7 @@ static struct platform_device *smdk2410_devices[] __initdata = {
&s3c_device_usb,
&s3c_device_lcd,
&s3c_device_wdt,
&s3c_device_i2c,
&s3c_device_i2c0,
&s3c_device_iis,
};
@ -102,6 +103,7 @@ static void __init smdk2410_map_io(void)
static void __init smdk2410_init(void)
{
s3c_i2c0_set_platdata(NULL);
platform_add_devices(smdk2410_devices, ARRAY_SIZE(smdk2410_devices));
smdk_machine_init();
}

4
arch/arm/mach-s3c2410/mach-tct_hammer.c
View File

@ -45,6 +45,7 @@
#include <asm/mach-types.h>
#include <plat/regs-serial.h>
#include <plat/iic.h>
#include <plat/devs.h>
#include <plat/cpu.h>
@ -127,7 +128,7 @@ static struct s3c2410_uartcfg tct_hammer_uartcfgs[] = {
static struct platform_device *tct_hammer_devices[] __initdata = {
&s3c_device_adc,
&s3c_device_wdt,
&s3c_device_i2c,
&s3c_device_i2c0,
&s3c_device_usb,
&s3c_device_rtc,
&s3c_device_usbgadget,
@ -146,6 +147,7 @@ static void __init tct_hammer_map_io(void)
static void __init tct_hammer_init(void)
{
s3c_i2c0_set_platdata(NULL);
platform_add_devices(tct_hammer_devices, ARRAY_SIZE(tct_hammer_devices));
}

4
arch/arm/mach-s3c2410/mach-vr1000.c
View File

@ -47,6 +47,7 @@
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#include <plat/iic.h>
#include "usb-simtec.h"
#include "nor-simtec.h"
@ -334,7 +335,7 @@ static struct platform_device *vr1000_devices[] __initdata = {
&s3c_device_usb,
&s3c_device_lcd,
&s3c_device_wdt,
&s3c_device_i2c,
&s3c_device_i2c0,
&s3c_device_adc,
&serial_device,
&vr1000_dm9k0,
@ -384,6 +385,7 @@ static void __init vr1000_map_io(void)
static void __init vr1000_init(void)
{
s3c_i2c0_set_platdata(NULL);
platform_add_devices(vr1000_devices, ARRAY_SIZE(vr1000_devices));
i2c_register_board_info(0, vr1000_i2c_devs,

27
arch/arm/mach-s3c2410/s3c2410.c
View File

@ -16,6 +16,7 @@
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/sysdev.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
@ -28,6 +29,8 @@
#include <mach/hardware.h>
#include <asm/irq.h>
#include <plat/cpu-freq.h>
#include <mach/regs-clock.h>
#include <plat/regs-serial.h>
@ -35,6 +38,7 @@
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/clock.h>
#include <plat/pll.h>
/* Initial IO mappings */
@ -59,25 +63,28 @@ void __init s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no)
* machine specific initialisation.
*/
void __init s3c2410_map_io(struct map_desc *mach_desc, int mach_size)
void __init s3c2410_map_io(void)
{
/* register our io-tables */
iotable_init(s3c2410_iodesc, ARRAY_SIZE(s3c2410_iodesc));
iotable_init(mach_desc, mach_size);
}
void __init s3c2410_init_clocks(int xtal)
void __init_or_cpufreq s3c2410_setup_clocks(void)
{
struct clk *xtal_clk;
unsigned long tmp;
unsigned long xtal;
unsigned long fclk;
unsigned long hclk;
unsigned long pclk;
xtal_clk = clk_get(NULL, "xtal");
xtal = clk_get_rate(xtal_clk);
clk_put(xtal_clk);
/* now we've got our machine bits initialised, work out what
* clocks we've got */
fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal);
fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal);
tmp = __raw_readl(S3C2410_CLKDIVN);
@ -95,7 +102,13 @@ void __init s3c2410_init_clocks(int xtal)
* console to use them
*/
s3c24xx_setup_clocks(xtal, fclk, hclk, pclk);
s3c24xx_setup_clocks(fclk, hclk, pclk);
}
void __init s3c2410_init_clocks(int xtal)
{
s3c24xx_register_baseclocks(xtal);
s3c2410_setup_clocks();
s3c2410_baseclk_add();
}

7
arch/arm/mach-s3c2412/clock.c
View File

@ -93,12 +93,6 @@ static int s3c2412_upll_enable(struct clk *clk, int enable)
/* clock selections */
/* CPU EXTCLK input */
static struct clk clk_ext = {
.name = "extclk",
.id = -1,
};
static struct clk clk_erefclk = {
.name = "erefclk",
.id = -1,
@ -773,5 +767,6 @@ int __init s3c2412_baseclk_add(void)
s3c2412_clkcon_enable(clkp, 0);
}
s3c_pwmclk_init();
return 0;
}

16
arch/arm/mach-s3c2412/mach-jive.c
View File

@ -17,7 +17,6 @@
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/sysdev.h>
#include <linux/delay.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
#include <linux/i2c.h>
@ -53,6 +52,7 @@
#include <plat/cpu.h>
#include <plat/pm.h>
#include <plat/udc.h>
#include <plat/iic.h>
static struct map_desc jive_iodesc[] __initdata = {
};
@ -398,11 +398,12 @@ static struct s3c2410_spigpio_info jive_lcd_spi = {
.bus_num = 1,
.pin_clk = S3C2410_GPG8,
.pin_mosi = S3C2410_GPB8,
.num_chipselect = 1,
.chip_select = jive_lcd_spi_chipselect,
};
static struct platform_device jive_device_lcdspi = {
.name = "s3c24xx-spi-gpio",
.name = "spi_s3c24xx_gpio",
.id = 1,
.num_resources = 0,
.dev.platform_data = &jive_lcd_spi,
@ -419,11 +420,12 @@ static struct s3c2410_spigpio_info jive_wm8750_spi = {
.bus_num = 2,
.pin_clk = S3C2410_GPB4,
.pin_mosi = S3C2410_GPB9,
.num_chipselect = 1,
.chip_select = jive_wm8750_chipselect,
};
static struct platform_device jive_device_wm8750 = {
.name = "s3c24xx-spi-gpio",
.name = "spi_s3c24xx_gpio",
.id = 2,
.num_resources = 0,
.dev.platform_data = &jive_wm8750_spi,
@ -450,14 +452,14 @@ static struct spi_board_info __initdata jive_spi_devs[] = {
/* I2C bus and device configuration. */
static struct s3c2410_platform_i2c jive_i2c_cfg = {
static struct s3c2410_platform_i2c jive_i2c_cfg __initdata = {
.max_freq = 80 * 1000,
.bus_freq = 50 * 1000,
.flags = S3C_IICFLG_FILTER,
.sda_delay = 2,
};
static struct i2c_board_info jive_i2c_devs[] = {
static struct i2c_board_info jive_i2c_devs[] __initdata = {
[0] = {
I2C_BOARD_INFO("lis302dl", 0x1c),
.irq = IRQ_EINT14,
@ -470,7 +472,7 @@ static struct platform_device *jive_devices[] __initdata = {
&s3c_device_usb,
&s3c_device_rtc,
&s3c_device_wdt,
&s3c_device_i2c,
&s3c_device_i2c0,
&s3c_device_lcd,
&jive_device_lcdspi,
&jive_device_wm8750,
@ -663,7 +665,7 @@ static void __init jive_machine_init(void)
spi_register_board_info(jive_spi_devs, ARRAY_SIZE(jive_spi_devs));
s3c_device_i2c.dev.platform_data = &jive_i2c_cfg;
s3c_i2c0_set_platdata(&jive_i2c_cfg);
i2c_register_board_info(0, jive_i2c_devs, ARRAY_SIZE(jive_i2c_devs));
pm_power_off = jive_power_off;

4
arch/arm/mach-s3c2412/mach-smdk2413.c
View File

@ -38,6 +38,7 @@
#include <mach/idle.h>
#include <plat/udc.h>
#include <plat/iic.h>
#include <mach/fb.h>
#include <plat/s3c2410.h>
@ -105,7 +106,7 @@ static struct platform_device *smdk2413_devices[] __initdata = {
&s3c_device_usb,
//&s3c_device_lcd,
&s3c_device_wdt,
&s3c_device_i2c,
&s3c_device_i2c0,
&s3c_device_iis,
&s3c_device_usbgadget,
};
@ -142,6 +143,7 @@ static void __init smdk2413_machine_init(void)
s3c24xx_udc_set_platdata(&smdk2413_udc_cfg);
s3c_i2c0_set_platdata(NULL);
platform_add_devices(smdk2413_devices, ARRAY_SIZE(smdk2413_devices));
smdk_machine_init();

4
arch/arm/mach-s3c2412/mach-vstms.c
View File

@ -39,6 +39,7 @@
#include <mach/idle.h>
#include <mach/fb.h>
#include <plat/iic.h>
#include <plat/nand.h>
#include <plat/s3c2410.h>
@ -122,7 +123,7 @@ static struct s3c2410_platform_nand vstms_nand_info = {
static struct platform_device *vstms_devices[] __initdata = {
&s3c_device_usb,
&s3c_device_wdt,
&s3c_device_i2c,
&s3c_device_i2c0,
&s3c_device_iis,
&s3c_device_rtc,
&s3c_device_nand,
@ -151,6 +152,7 @@ static void __init vstms_map_io(void)
static void __init vstms_init(void)
{
s3c_i2c0_set_platdata(NULL);
platform_add_devices(vstms_devices, ARRAY_SIZE(vstms_devices));
}

25
arch/arm/mach-s3c2412/s3c2412.c
View File

@ -16,6 +16,7 @@
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/sysdev.h>
#include <linux/serial_core.h>
@ -33,6 +34,8 @@
#include <mach/reset.h>
#include <mach/idle.h>
#include <plat/cpu-freq.h>
#include <mach/regs-clock.h>
#include <plat/regs-serial.h>
#include <mach/regs-power.h>
@ -47,6 +50,7 @@
#include <plat/devs.h>
#include <plat/clock.h>
#include <plat/pm.h>
#include <plat/pll.h>
#ifndef CONFIG_CPU_S3C2412_ONLY
void __iomem *s3c24xx_va_gpio2 = S3C24XX_VA_GPIO;
@ -136,7 +140,7 @@ static void s3c2412_hard_reset(void)
* machine specific initialisation.
*/
void __init s3c2412_map_io(struct map_desc *mach_desc, int mach_size)
void __init s3c2412_map_io(void)
{
/* move base of IO */
@ -153,20 +157,25 @@ void __init s3c2412_map_io(struct map_desc *mach_desc, int mach_size)
/* register our io-tables */
iotable_init(s3c2412_iodesc, ARRAY_SIZE(s3c2412_iodesc));
iotable_init(mach_desc, mach_size);
}
void __init s3c2412_init_clocks(int xtal)
void __init_or_cpufreq s3c2412_setup_clocks(void)
{
struct clk *xtal_clk;
unsigned long tmp;
unsigned long xtal;
unsigned long fclk;
unsigned long hclk;
unsigned long pclk;
xtal_clk = clk_get(NULL, "xtal");
xtal = clk_get_rate(xtal_clk);
clk_put(xtal_clk);
/* now we've got our machine bits initialised, work out what
* clocks we've got */
fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal*2);
fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal * 2);
clk_mpll.rate = fclk;
@ -183,11 +192,17 @@ void __init s3c2412_init_clocks(int xtal)
printk("S3C2412: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));
s3c24xx_setup_clocks(fclk, hclk, pclk);
}
void __init s3c2412_init_clocks(int xtal)
{
/* initialise the clocks here, to allow other things like the
* console to use them
*/
s3c24xx_setup_clocks(xtal, fclk, hclk, pclk);
s3c24xx_register_baseclocks(xtal);
s3c2412_setup_clocks();
s3c2412_baseclk_add();
}

4
arch/arm/mach-s3c2440/Kconfig
View File

@ -29,8 +29,10 @@ menu "S3C2440 Machines"
config MACH_ANUBIS
bool "Simtec Electronics ANUBIS"
select CPU_S3C2440
select S3C24XX_DCLK
select PM_SIMTEC if PM
select HAVE_PATA_PLATFORM
select S3C24XX_GPIO_EXTRA64
help
Say Y here if you are using the Simtec Electronics ANUBIS
development system
@ -38,7 +40,9 @@ config MACH_ANUBIS
config MACH_OSIRIS
bool "Simtec IM2440D20 (OSIRIS) module"
select CPU_S3C2440
select S3C24XX_DCLK
select PM_SIMTEC if PM
select S3C24XX_GPIO_EXTRA128
help
Say Y here if you are using the Simtec IM2440D20 module, also
known as the Osiris.

9
arch/arm/mach-s3c2440/mach-anubis.c
View File

@ -40,6 +40,7 @@
#include <mach/regs-mem.h>
#include <mach/regs-lcd.h>
#include <plat/nand.h>
#include <plat/iic.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
@ -366,6 +367,8 @@ static struct sm501_initdata anubis_sm501_initdata = {
.mask = 0,
},
.devices = SM501_USE_GPIO,
/* set the SDRAM and bus clocks */
.mclk = 72 * MHZ,
.m1xclk = 144 * MHZ,
@ -373,10 +376,12 @@ static struct sm501_initdata anubis_sm501_initdata = {
static struct sm501_platdata_gpio_i2c anubis_sm501_gpio_i2c[] = {
[0] = {
.bus_num = 1,
.pin_scl = 44,
.pin_sda = 45,
},
[1] = {
.bus_num = 2,
.pin_scl = 40,
.pin_sda = 41,
},
@ -384,6 +389,7 @@ static struct sm501_platdata_gpio_i2c anubis_sm501_gpio_i2c[] = {
static struct sm501_platdata anubis_sm501_platdata = {
.init = &anubis_sm501_initdata,
.gpio_base = -1,
.gpio_i2c = anubis_sm501_gpio_i2c,
.gpio_i2c_nr = ARRAY_SIZE(anubis_sm501_gpio_i2c),
};
@ -404,7 +410,7 @@ static struct platform_device *anubis_devices[] __initdata = {
&s3c_device_usb,
&s3c_device_wdt,
&s3c_device_adc,
&s3c_device_i2c,
&s3c_device_i2c0,
&s3c_device_rtc,
&s3c_device_nand,
&anubis_device_ide0,
@ -468,6 +474,7 @@ static void __init anubis_map_io(void)
static void __init anubis_init(void)
{
s3c_i2c0_set_platdata(NULL);
platform_add_devices(anubis_devices, ARRAY_SIZE(anubis_devices));
i2c_register_board_info(0, anubis_i2c_devs,

49
arch/arm/mach-s3c2440/mach-at2440evb.c
View File

@ -28,6 +28,7 @@
#include <asm/mach/irq.h>
#include <mach/hardware.h>
#include <mach/fb.h>
#include <asm/irq.h>
#include <asm/mach-types.h>
@ -36,6 +37,7 @@
#include <mach/regs-mem.h>
#include <mach/regs-lcd.h>
#include <plat/nand.h>
#include <plat/iic.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
@ -45,6 +47,7 @@
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#include <asm/plat-s3c24xx/mci.h>
static struct map_desc at2440evb_iodesc[] __initdata = {
/* Nothing here */
@ -162,19 +165,60 @@ static struct platform_device at2440evb_device_eth = {
},
};
static struct s3c24xx_mci_pdata at2440evb_mci_pdata = {
.gpio_detect = S3C2410_GPG10,
};
/* 7" LCD panel */
static struct s3c2410fb_display at2440evb_lcd_cfg __initdata = {
.lcdcon5 = S3C2410_LCDCON5_FRM565 |
S3C2410_LCDCON5_INVVLINE |
S3C2410_LCDCON5_INVVFRAME |
S3C2410_LCDCON5_PWREN |
S3C2410_LCDCON5_HWSWP,
.type = S3C2410_LCDCON1_TFT,
.width = 800,
.height = 480,
.pixclock = 33333, /* HCLK 60 MHz, divisor 2 */
.xres = 800,
.yres = 480,
.bpp = 16,
.left_margin = 88,
.right_margin = 40,
.hsync_len = 128,
.upper_margin = 32,
.lower_margin = 11,
.vsync_len = 2,
};
static struct s3c2410fb_mach_info at2440evb_fb_info __initdata = {
.displays = &at2440evb_lcd_cfg,
.num_displays = 1,
.default_display = 0,
};
static struct platform_device *at2440evb_devices[] __initdata = {
&s3c_device_usb,
&s3c_device_wdt,
&s3c_device_adc,
&s3c_device_i2c,
&s3c_device_i2c0,
&s3c_device_rtc,
&s3c_device_nand,
&s3c_device_sdi,
&s3c_device_lcd,
&at2440evb_device_eth,
};
static void __init at2440evb_map_io(void)
{
s3c_device_nand.dev.platform_data = &at2440evb_nand_info;
s3c_device_sdi.name = "s3c2440-sdi";
s3c_device_sdi.dev.platform_data = &at2440evb_mci_pdata;
s3c24xx_init_io(at2440evb_iodesc, ARRAY_SIZE(at2440evb_iodesc));
s3c24xx_init_clocks(16934400);
@ -183,6 +227,9 @@ static void __init at2440evb_map_io(void)
static void __init at2440evb_init(void)
{
s3c24xx_fb_set_platdata(&at2440evb_fb_info);
s3c_i2c0_set_platdata(NULL);
platform_add_devices(at2440evb_devices, ARRAY_SIZE(at2440evb_devices));
}

4
arch/arm/mach-s3c2440/mach-nexcoder.c
View File

@ -37,6 +37,7 @@
//#include <asm/debug-ll.h>
#include <mach/regs-gpio.h>
#include <plat/regs-serial.h>
#include <plat/iic.h>
#include <plat/s3c2410.h>
#include <plat/s3c2440.h>
@ -107,7 +108,7 @@ static struct platform_device *nexcoder_devices[] __initdata = {
&s3c_device_usb,
&s3c_device_lcd,
&s3c_device_wdt,
&s3c_device_i2c,
&s3c_device_i2c0,
&s3c_device_iis,
&s3c_device_rtc,
&s3c_device_camif,
@ -142,6 +143,7 @@ static void __init nexcoder_map_io(void)
static void __init nexcoder_init(void)
{
s3c_i2c0_set_platdata(NULL);
platform_add_devices(nexcoder_devices, ARRAY_SIZE(nexcoder_devices));
};

5
arch/arm/mach-s3c2440/mach-osiris.c
View File

@ -38,6 +38,7 @@
#include <mach/regs-mem.h>
#include <mach/regs-lcd.h>
#include <plat/nand.h>
#include <plat/iic.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
@ -335,7 +336,7 @@ static struct i2c_board_info osiris_i2c_devs[] __initdata = {
/* Standard Osiris devices */
static struct platform_device *osiris_devices[] __initdata = {
&s3c_device_i2c,
&s3c_device_i2c0,
&s3c_device_wdt,
&s3c_device_nand,
&osiris_pcmcia,
@ -398,6 +399,8 @@ static void __init osiris_init(void)
sysdev_class_register(&osiris_pm_sysclass);
sysdev_register(&osiris_pm_sysdev);
s3c_i2c0_set_platdata(NULL);
i2c_register_board_info(0, osiris_i2c_devs,
ARRAY_SIZE(osiris_i2c_devs));

2
arch/arm/mach-s3c2440/mach-rx3715.c
View File

@ -179,7 +179,7 @@ static struct platform_device *rx3715_devices[] __initdata = {
&s3c_device_usb,
&s3c_device_lcd,
&s3c_device_wdt,
&s3c_device_i2c,
&s3c_device_i2c0,
&s3c_device_iis,
&s3c_device_nand,
};

4
arch/arm/mach-s3c2440/mach-smdk2440.c
View File

@ -37,6 +37,7 @@
#include <mach/idle.h>
#include <mach/fb.h>
#include <plat/iic.h>
#include <plat/s3c2410.h>
#include <plat/s3c2440.h>
@ -152,7 +153,7 @@ static struct platform_device *smdk2440_devices[] __initdata = {
&s3c_device_usb,
&s3c_device_lcd,
&s3c_device_wdt,
&s3c_device_i2c,
&s3c_device_i2c0,
&s3c_device_iis,
};
@ -166,6 +167,7 @@ static void __init smdk2440_map_io(void)
static void __init smdk2440_machine_init(void)
{
s3c24xx_fb_set_platdata(&smdk2440_fb_info);
s3c_i2c0_set_platdata(NULL);
platform_add_devices(smdk2440_devices, ARRAY_SIZE(smdk2440_devices));
smdk_machine_init();

1
arch/arm/mach-s3c2443/Kconfig
View File

@ -24,6 +24,7 @@ config MACH_SMDK2443
bool "SMDK2443"
select CPU_S3C2443
select MACH_SMDK
select S3C_DEV_HSMMC
help
Say Y here if you are using an SMDK2443

53
arch/arm/mach-s3c2443/clock.c
View File

@ -29,7 +29,6 @@
#include <linux/sysdev.h>
#include <linux/clk.h>
#include <linux/mutex.h>
#include <linux/delay.h>
#include <linux/serial_core.h>
#include <linux/io.h>
@ -39,6 +38,8 @@
#include <mach/regs-s3c2443-clock.h>
#include <plat/cpu-freq.h>
#include <plat/s3c2443.h>
#include <plat/clock.h>
#include <plat/cpu.h>
@ -145,12 +146,6 @@ static unsigned long s3c2443_roundrate_clksrc256(struct clk *clk,
/* clock selections */
/* CPU EXTCLK input */
static struct clk clk_ext = {
.name = "ext",
.id = -1,
};
static struct clk clk_mpllref = {
.name = "mpllref",
.parent = &clk_xtal,
@ -165,14 +160,6 @@ static struct clk clk_mpll = {
};
#endif
static struct clk clk_epllref;
static struct clk clk_epll = {
.name = "epll",
.parent = &clk_epllref,
.id = -1,
};
static struct clk clk_i2s_ext = {
.name = "i2s-ext",
.id = -1,
@ -1011,22 +998,20 @@ static struct clk *clks[] __initdata = {
&clk_prediv,
};
void __init s3c2443_init_clocks(int xtal)
void __init_or_cpufreq s3c2443_setup_clocks(void)
{
unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
unsigned long mpllcon = __raw_readl(S3C2443_MPLLCON);
unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
struct clk *xtal_clk;
unsigned long xtal;
unsigned long pll;
unsigned long fclk;
unsigned long hclk;
unsigned long pclk;
struct clk *clkp;
int ret;
int ptr;
/* s3c2443 parents h and p clocks from prediv */
clk_h.parent = &clk_prediv;
clk_p.parent = &clk_prediv;
xtal_clk = clk_get(NULL, "xtal");
xtal = clk_get_rate(xtal_clk);
clk_put(xtal_clk);
pll = s3c2443_get_mpll(mpllcon, xtal);
clk_msysclk.rate = pll;
@ -1036,13 +1021,29 @@ void __init s3c2443_init_clocks(int xtal)
hclk /= s3c2443_get_hdiv(clkdiv0);
pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1);
s3c24xx_setup_clocks(xtal, fclk, hclk, pclk);
s3c24xx_setup_clocks(fclk, hclk, pclk);
printk("S3C2443: mpll %s %ld.%03ld MHz, cpu %ld.%03ld MHz, mem %ld.%03ld MHz, pclk %ld.%03ld MHz\n",
(mpllcon & S3C2443_PLLCON_OFF) ? "off":"on",
print_mhz(pll), print_mhz(fclk),
print_mhz(hclk), print_mhz(pclk));
s3c24xx_setup_clocks(fclk, hclk, pclk);
}
void __init s3c2443_init_clocks(int xtal)
{
struct clk *clkp;
unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
int ret;
int ptr;
/* s3c2443 parents h and p clocks from prediv */
clk_h.parent = &clk_prediv;
clk_p.parent = &clk_prediv;
s3c24xx_register_baseclocks(xtal);
s3c2443_setup_clocks();
s3c2443_clk_initparents();
for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) {
@ -1056,7 +1057,7 @@ void __init s3c2443_init_clocks(int xtal)
}
clk_epll.rate = s3c2443_get_epll(epllcon, xtal);
clk_epll.parent = &clk_epllref;
clk_usb_bus.parent = &clk_usb_bus_host;
/* ensure usb bus clock is within correct rate of 48MHz */
@ -1105,4 +1106,6 @@ void __init s3c2443_init_clocks(int xtal)
(clkp->enable)(clkp, 0);
}
s3c_pwmclk_init();
}

6
arch/arm/mach-s3c2443/mach-smdk2443.c
View File

@ -37,6 +37,7 @@
#include <mach/idle.h>
#include <mach/fb.h>
#include <plat/iic.h>
#include <plat/s3c2410.h>
#include <plat/s3c2440.h>
@ -103,8 +104,8 @@ static struct s3c2410_uartcfg smdk2443_uartcfgs[] __initdata = {
static struct platform_device *smdk2443_devices[] __initdata = {
&s3c_device_wdt,
&s3c_device_i2c,
&s3c_device_hsmmc,
&s3c_device_i2c0,
&s3c_device_hsmmc0,
};
static void __init smdk2443_map_io(void)
@ -116,6 +117,7 @@ static void __init smdk2443_map_io(void)
static void __init smdk2443_machine_init(void)
{
s3c_i2c0_set_platdata(NULL);
platform_add_devices(smdk2443_devices, ARRAY_SIZE(smdk2443_devices));
smdk_machine_init();
}

3
arch/arm/mach-s3c2443/s3c2443.c
View File

@ -81,10 +81,9 @@ void __init s3c2443_init_uarts(struct s3c2410_uartcfg *cfg, int no)
* machine specific initialisation.
*/
void __init s3c2443_map_io(struct map_desc *mach_desc, int mach_size)
void __init s3c2443_map_io(void)
{
iotable_init(s3c2443_iodesc, ARRAY_SIZE(s3c2443_iodesc));
iotable_init(mach_desc, mach_size);
}
/* need to register class before we actually register the device, and

28
arch/arm/mach-s3c24a0/include/mach/debug-macro.S Normal file
View File

@ -0,0 +1,28 @@
/* arch/arm/mach-s3c2410/include/mach/debug-macro.S
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/* pull in the relevant register and map files. */
#include <mach/map.h>
#include <plat/regs-serial.h>
.macro addruart, rx
mrc p15, 0, \rx, c1, c0
tst \rx, #1
ldreq \rx, = S3C24XX_PA_UART
ldrne \rx, = S3C24XX_VA_UART
#if CONFIG_DEBUG_S3C_UART != 0
add \rx, \rx, #(S3C2410_UART1_OFF * CONFIG_DEBUG_S3C_UART)
#endif
.endm
/* include the reset of the code which will do the work, we're only
* compiling for a single cpu processor type so the default of s3c2440
* will be fine with us.
*/
#include <plat/debug-macro.S>

115
arch/arm/mach-s3c24a0/include/mach/irqs.h Normal file
View File

@ -0,0 +1,115 @@
/* linux/arch/arm/mach-s3c24a0/include/mach/irqs.h
*
* Copyright (c) 2003-2005 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_24A0_IRQS_H
#define __ASM_ARCH_24A0_IRQS_H __FILE__
#define IRQ_EINT0t2 S3C2410_IRQ(0) /* 16 */
/* for generic entry-macro.S */
#define IRQ_EINT0 IRQ_EINT0t2
#define IRQ_EINT3t6 S3C2410_IRQ(1)
#define IRQ_EINT7t10 S3C2410_IRQ(2)
#define IRQ_EINT11t14 S3C2410_IRQ(3)
#define IRQ_EINT15t18 S3C2410_IRQ(4) /* 20 */
#define IRQ_TICK S3C2410_IRQ(5)
#define IRQ_DCTQ S3C2410_IRQ(6)
#define IRQ_MC S3C2410_IRQ(7)
#define IRQ_ME S3C2410_IRQ(8) /* 24 */
#define IRQ_KEYPAD S3C2410_IRQ(9)
#define IRQ_TIMER0 S3C2410_IRQ(10)
#define IRQ_TIMER1 S3C2410_IRQ(11)
#define IRQ_TIMER2 S3C2410_IRQ(12)
#define IRQ_TIMER3_4 S3C2410_IRQ(13)
#define IRQ_OS_TIMER IRQ_TIMER3_4
#define IRQ_LCD S3C2410_IRQ(14)
#define IRQ_CAM_C S3C2410_IRQ(15)
#define IRQ_WDT_BATFLT S3C2410_IRQ(16) /* 32 */
#define IRQ_UART0 S3C2410_IRQ(17)
#define IRQ_CAM_P S3C2410_IRQ(18)
#define IRQ_MODEM S3C2410_IRQ(19)
#define IRQ_DMA S3C2410_IRQ(20)
#define IRQ_SDI S3C2410_IRQ(21)
#define IRQ_SPI0 S3C2410_IRQ(22)
#define IRQ_UART1 S3C2410_IRQ(23)
#define IRQ_AC97_NFLASH S3C2410_IRQ(24) /* 40 */
#define IRQ_USBD S3C2410_IRQ(25)
#define IRQ_USBH S3C2410_IRQ(26)
#define IRQ_IIC S3C2410_IRQ(27)
#define IRQ_IRDA_MSTICK S3C2410_IRQ(28) /* 44 */
#define IRQ_VLX_SPI1 S3C2410_IRQ(29)
#define IRQ_RTC S3C2410_IRQ(30) /* 46 */
#define IRQ_ADC_PEN S3C2410_IRQ(31)
/* interrupts generated from the external interrupts sources */
#define IRQ_EINT00 S3C2410_IRQ(32) /* 48 */
#define IRQ_EINT1 S3C2410_IRQ(33)
#define IRQ_EINT2 S3C2410_IRQ(34)
#define IRQ_EINT3 S3C2410_IRQ(35)
#define IRQ_EINT4 S3C2410_IRQ(36)
#define IRQ_EINT5 S3C2410_IRQ(37)
#define IRQ_EINT6 S3C2410_IRQ(38)
#define IRQ_EINT7 S3C2410_IRQ(39)
#define IRQ_EINT8 S3C2410_IRQ(40)
#define IRQ_EINT9 S3C2410_IRQ(41)
#define IRQ_EINT10 S3C2410_IRQ(42)
#define IRQ_EINT11 S3C2410_IRQ(43)
#define IRQ_EINT12 S3C2410_IRQ(44)
#define IRQ_EINT13 S3C2410_IRQ(45)
#define IRQ_EINT14 S3C2410_IRQ(46)
#define IRQ_EINT15 S3C2410_IRQ(47)
#define IRQ_EINT16 S3C2410_IRQ(48)
#define IRQ_EINT17 S3C2410_IRQ(49)
#define IRQ_EINT18 S3C2410_IRQ(50)
/* SUB IRQS */
#define IRQ_S3CUART_RX0 S3C2410_IRQ(51) /* 67 */
#define IRQ_S3CUART_TX0 S3C2410_IRQ(52)
#define IRQ_S3CUART_ERR0 S3C2410_IRQ(53)
#define IRQ_S3CUART_RX1 S3C2410_IRQ(54)
#define IRQ_S3CUART_TX1 S3C2410_IRQ(55)
#define IRQ_S3CUART_ERR1 S3C2410_IRQ(56)
#define IRQ_S3CUART_RX2 (0x0)
#define IRQ_S3CUART_TX2 (0x0)
#define IRQ_S3CUART_ERR2 (0x0)
#define IRQ_IRDA S3C2410_IRQ(57)
#define IRQ_MSTICK S3C2410_IRQ(58)
#define IRQ_RESERVED0 S3C2410_IRQ(59)
#define IRQ_RESERVED1 S3C2410_IRQ(60)
#define IRQ_RESERVED2 S3C2410_IRQ(61)
#define IRQ_TIMER3 S3C2410_IRQ(62)
#define IRQ_TIMER4 S3C2410_IRQ(63)
#define IRQ_WDT S3C2410_IRQ(64)
#define IRQ_BATFLT S3C2410_IRQ(65)
#define IRQ_POST S3C2410_IRQ(66)
#define IRQ_DISP_FIFO S3C2410_IRQ(67)
#define IRQ_PENUP S3C2410_IRQ(68)
#define IRQ_PENDN S3C2410_IRQ(69)
#define IRQ_ADC S3C2410_IRQ(70)
#define IRQ_DISP_FRAME S3C2410_IRQ(71)
#define IRQ_NFLASH S3C2410_IRQ(72)
#define IRQ_AC97 S3C2410_IRQ(73)
#define IRQ_SPI1 S3C2410_IRQ(74)
#define IRQ_VLX S3C2410_IRQ(75)
#define IRQ_DMA0 S3C2410_IRQ(76)
#define IRQ_DMA1 S3C2410_IRQ(77)
#define IRQ_DMA2 S3C2410_IRQ(78)
#define IRQ_DMA3 S3C2410_IRQ(79)
#define IRQ_TC (0x0)
#define NR_IRQS (IRQ_DMA3+1)
#endif /* __ASM_ARCH_24A0_IRQS_H */

85
arch/arm/mach-s3c24a0/include/mach/map.h Normal file
View File

@ -0,0 +1,85 @@
/* linux/arch/arm/mach-s3c24a0/include/mach/map.h
*
* Copyright 2003,2007 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S3C24A0 - Memory map definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_24A0_MAP_H
#define __ASM_ARCH_24A0_MAP_H __FILE__
#include <plat/map-base.h>
#include <plat/map.h>
#define S3C24A0_PA_IO_BASE (0x40000000)
#define S3C24A0_PA_CLKPWR (0x40000000)
#define S3C24A0_PA_IRQ (0x40200000)
#define S3C24A0_PA_DMA (0x40400000)
#define S3C24A0_PA_MEMCTRL (0x40C00000)
#define S3C24A0_PA_NAND (0x40C00000)
#define S3C24A0_PA_SROM (0x40C20000)
#define S3C24A0_PA_SDRAM (0x40C40000)
#define S3C24A0_PA_BUSM (0x40CE0000)
#define S3C24A0_PA_USBHOST (0x41000000)
#define S3C24A0_PA_MODEMIF (0x41180000)
#define S3C24A0_PA_IRDA (0x41800000)
#define S3C24A0_PA_TIMER (0x44000000)
#define S3C24A0_PA_WATCHDOG (0x44100000)
#define S3C24A0_PA_RTC (0x44200000)
#define S3C24A0_PA_UART (0x44400000)
#define S3C24A0_PA_UART0 (S3C24A0_PA_UART)
#define S3C24A0_PA_UART1 (S3C24A0_PA_UART + 0x4000)
#define S3C24A0_PA_SPI (0x44500000)
#define S3C24A0_PA_IIC (0x44600000)
#define S3C24A0_PA_IIS (0x44700000)
#define S3C24A0_PA_GPIO (0x44800000)
#define S3C24A0_PA_KEYIF (0x44900000)
#define S3C24A0_PA_USBDEV (0x44A00000)
#define S3C24A0_PA_AC97 (0x45000000)
#define S3C24A0_PA_ADC (0x45800000)
#define S3C24A0_PA_SDI (0x46000000)
#define S3C24A0_PA_MS (0x46100000)
#define S3C24A0_PA_LCD (0x4A000000)
#define S3C24A0_PA_VPOST (0x4A100000)
/* physical addresses of all the chip-select areas */
#define S3C24A0_CS0 (0x00000000)
#define S3C24A0_CS1 (0x04000000)
#define S3C24A0_CS2 (0x08000000)
#define S3C24A0_CS3 (0x0C000000)
#define S3C24A0_CS4 (0x10000000)
#define S3C24A0_CS5 (0x40000000)
#define S3C24A0_SDRAM_PA (S3C24A0_CS4)
/* Use a single interface for common resources between S3C24XX cpus */
#define S3C24XX_PA_IRQ S3C24A0_PA_IRQ
#define S3C24XX_PA_MEMCTRL S3C24A0_PA_MEMCTRL
#define S3C24XX_PA_USBHOST S3C24A0_PA_USBHOST
#define S3C24XX_PA_DMA S3C24A0_PA_DMA
#define S3C24XX_PA_CLKPWR S3C24A0_PA_CLKPWR
#define S3C24XX_PA_LCD S3C24A0_PA_LCD
#define S3C24XX_PA_UART S3C24A0_PA_UART
#define S3C24XX_PA_TIMER S3C24A0_PA_TIMER
#define S3C24XX_PA_USBDEV S3C24A0_PA_USBDEV
#define S3C24XX_PA_WATCHDOG S3C24A0_PA_WATCHDOG
#define S3C24XX_PA_IIS S3C24A0_PA_IIS
#define S3C24XX_PA_GPIO S3C24A0_PA_GPIO
#define S3C24XX_PA_RTC S3C24A0_PA_RTC
#define S3C24XX_PA_ADC S3C24A0_PA_ADC
#define S3C24XX_PA_SPI S3C24A0_PA_SPI
#define S3C24XX_PA_SDI S3C24A0_PA_SDI
#define S3C24XX_PA_NAND S3C24A0_PA_NAND
#define S3C_PA_UART S3C24A0_PA_UART
#define S3C_PA_IIC S3C24A0_PA_IIC
#endif /* __ASM_ARCH_24A0_MAP_H */

19
arch/arm/mach-s3c24a0/include/mach/memory.h Normal file
View File

@ -0,0 +1,19 @@
/* linux/arch/arm/mach-s3c24a0/include/mach/memory.h
* from linux/include/asm-arm/arch-rpc/memory.h
*
* Copyright (C) 1996,1997,1998 Russell King.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_24A0_MEMORY_H
#define __ASM_ARCH_24A0_MEMORY_H __FILE__
#define PHYS_OFFSET UL(0x10000000)
#define __virt_to_bus(x) __virt_to_phys(x)
#define __bus_to_virt(x) __phys_to_virt(x)
#endif

88
arch/arm/mach-s3c24a0/include/mach/regs-clock.h Normal file
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@ -0,0 +1,88 @@
/* linux/arch/arm/mach-s3c24a0/include/mach/regs-clock.h
*
* Copyright (c) 2003,2004,2005,2006 Simtec Electronics <linux@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* S3C24A0 clock register definitions
*/
#ifndef __ASM_ARCH_24A0_REGS_CLOCK_H
#define __ASM_ARCH_24A0_REGS_CLOCK_H __FILE__
#define S3C24A0_MPLLCON S3C2410_CLKREG(0x10)
#define S3C24A0_UPLLCON S3C2410_CLKREG(0x14)
#define S3C24A0_CLKCON S3C2410_CLKREG(0x20)
#define S3C24A0_CLKSRC S3C2410_CLKREG(0x24)
#define S3C24A0_CLKDIVN S3C2410_CLKREG(0x28)
/* CLKCON register bits */
#define S3C24A0_CLKCON_VLX (1<<29)
#define S3C24A0_CLKCON_VPOST (1<<28)
#define S3C24A0_CLKCON_WDT (1<<27) /* reserved */
#define S3C24A0_CLKCON_MPEGDCTQ (1<<26)
#define S3C24A0_CLKCON_VPOSTIF (1<<25)
#define S3C24A0_CLKCON_MPEG4IF (1<<24)
#define S3C24A0_CLKCON_CAM_UPLL (1<<23)
#define S3C24A0_CLKCON_LCDC (1<<22)
#define S3C24A0_CLKCON_CAM_HCLK (1<<21)
#define S3C24A0_CLKCON_MPEG4 (1<<20)
#define S3C24A0_CLKCON_KEYPAD (1<<19)
#define S3C24A0_CLKCON_ADC (1<<18)
#define S3C24A0_CLKCON_SDI (1<<17)
#define S3C24A0_CLKCON_MS (1<<16) /* memory stick */
#define S3C24A0_CLKCON_USBD (1<<15)
#define S3C24A0_CLKCON_GPIO (1<<14)
#define S3C24A0_CLKCON_IIS (1<<13)
#define S3C24A0_CLKCON_IIC (1<<12)
#define S3C24A0_CLKCON_SPI (1<<11)
#define S3C24A0_CLKCON_UART1 (1<<10)
#define S3C24A0_CLKCON_UART0 (1<<9)
#define S3C24A0_CLKCON_PWMT (1<<8)
#define S3C24A0_CLKCON_USBH (1<<7)
#define S3C24A0_CLKCON_AC97 (1<<6)
#define S3C24A0_CLKCON_IrDA (1<<4)
#define S3C24A0_CLKCON_IDLE (1<<2)
#define S3C24A0_CLKCON_MON (1<<1)
#define S3C24A0_CLKCON_STOP (1<<0)
/* CLKSRC register bits */
#define S3C24A0_CLKSRC_OSC (1<<8) /* CLKSRC */
#define S3C24A0_CLKSRC_UPLL (1<<7)
#define S3C24A0_CLKSRC_MPLL (1<<5)
#define S3C24A0_CLKSRC_EXT (1<<4)
/* Use a single interface with the common code, for s3c24xx */
#define S3C2410_MPLLCON S3C24A0_MPLLCON
#define S3C2410_UPLLCON S3C24A0_UPLLCON
#define S3C2410_CLKCON S3C24A0_CLKCON
#define S3C2410_CLKSLOW S3C24A0_CLKSRC
#define S3C2410_CLKDIVN S3C24A0_CLKDIVN
#define S3C2410_CLKCON_IDLE S3C24A0_CLKCON_IDLE
#define S3C2410_CLKCON_POWER S3C24A0_CLKCON_STOP
#define S3C2410_CLKCON_LCDC S3C24A0_CLKCON_LCDC
#define S3C2410_CLKCON_USBH S3C24A0_CLKCON_USBH
#define S3C2410_CLKCON_USBD S3C24A0_CLKCON_USBD
#define S3C2410_CLKCON_PWMT S3C24A0_CLKCON_PWMT
#define S3C2410_CLKCON_SDI S3C24A0_CLKCON_SDI
#define S3C2410_CLKCON_UART0 S3C24A0_CLKCON_UART0
#define S3C2410_CLKCON_UART1 S3C24A0_CLKCON_UART1
#define S3C2410_CLKCON_GPIO S3C24A0_CLKCON_GPIO
#define S3C2410_CLKCON_ADC S3C24A0_CLKCON_ADC
#define S3C2410_CLKCON_IIC S3C24A0_CLKCON_IIC
#define S3C2410_CLKCON_IIS S3C24A0_CLKCON_IIS
#define S3C2410_CLKCON_SPI S3C24A0_CLKCON_SPI
#define S3C2410_CLKSLOW_UCLK_OFF S3C24A0_CLKSRC_UPLL
#define S3C2410_CLKSLOW_MPLL_OFF S3C24A0_CLKSRC_MPLL
#define S3C2410_CLKSLOW_SLOW (0xFF)
#define S3C2410_CLKSLOW_GET_SLOWVAL(x) (0x1)
#endif /* __ASM_ARCH_24A0_REGS_CLOCK_H */

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/* linux/arch/arm/mach-s3c24a0/include/mach/regs-irq.h
*
* Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
* http://www.simtec.co.uk/products/SWLINUX/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef ___ASM_ARCH_24A0_REGS_IRQ_H
#define ___ASM_ARCH_24A0_REGS_IRQ_H __FILE__
#define S3C2410_EINTMASK S3C2410_EINTREG(0x034)
#define S3C2410_EINTPEND S3C2410_EINTREG(0X038)
#define S3C24XX_EINTMASK S3C24XX_EINTREG(0x034)
#define S3C24XX_EINTPEND S3C24XX_EINTREG(0X038)
#endif /* __ASM_ARCH_24A0_REGS_IRQ_H */

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/* linux/arch/arm/mach-s3c24a0/include/mach/system.h
*
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* S3C24A0 - System function defines and includes
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <mach/hardware.h>
#include <asm/io.h>
#include <mach/map.h>
static void arch_idle(void)
{
/* currently no specific idle support. */
}
void (*s3c24xx_reset_hook)(void);
#include <asm/plat-s3c24xx/system-reset.h>

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/* linux/arch/arm/mach-s3c24a0/include/mach/tick.h
*
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C24A0 - timer tick support
*/
#define SUBSRC_TIMER4 (1 << (IRQ_TIMER4 - IRQ_S3CUART_RX0))
static inline int s3c24xx_ostimer_pending(void)
{
return __raw_readl(S3C2410_SUBSRCPND) & SUBSRC_TIMER4;
}

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arch/arm/mach-s3c24a0/include/mach/timex.h Normal file
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/* linux/arch/arm/mach-s3c24a0/include/mach/timex.h
*
* Copyright (c) 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* S3C2410 - time parameters
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_TIMEX_H
#define __ASM_ARCH_TIMEX_H
#define CLOCK_TICK_RATE 12000000
#endif /* __ASM_ARCH_TIMEX_H */

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arch/arm/mach-s3c24a0/include/mach/vmalloc.h Normal file
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/* linux/include/asm-arm/arch-s3c24ao/vmalloc.h
*
* Copyright 2008 Simtec Electronics <linux@simtec.co.uk>
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* S3C24A0 vmalloc definition
*/
#ifndef __ASM_ARCH_VMALLOC_H
#define __ASM_ARCH_VMALLOC_H
#define VMALLOC_END (0xE0000000)
#endif /* __ASM_ARCH_VMALLOC_H */

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# arch/arm/mach-s3c6400/Kconfig
#
# Copyright 2008 Openmoko, Inc.
# Simtec Electronics, Ben Dooks <ben@simtec.co.uk>
#
# Licensed under GPLv2
# Currently nothing here, this will be added later

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arch/arm/mach-s3c6400/Makefile Normal file
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# arch/arm/mach-s3c6400/Makefile
#
# Copyright 2008 Openmoko, Inc.
# Copyright 2008 Simtec Electronics
#
# Licensed under GPLv2
obj-y :=
obj-m :=
obj-n :=
obj- :=
# Core support for S3C6400 system
obj-n += blank.o

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zreladdr-y := 0x50008000
params_phys-y := 0x50000100

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arch/arm/mach-s3c6400/include/mach/debug-macro.S Normal file
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/* arch/arm/mach-s3c6400/include/mach/debug-macro.S
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/* pull in the relevant register and map files. */
#include <mach/map.h>
#include <plat/regs-serial.h>
/* note, for the boot process to work we have to keep the UART
* virtual address aligned to an 1MiB boundary for the L1
* mapping the head code makes. We keep the UART virtual address
* aligned and add in the offset when we load the value here.
*/
.macro addruart, rx
mrc p15, 0, \rx, c1, c0
tst \rx, #1
ldreq \rx, = S3C_PA_UART
ldrne \rx, = (S3C_VA_UART + S3C_PA_UART & 0xfffff)
#if CONFIG_DEBUG_S3C_UART != 0
add \rx, \rx, #(0x400 * CONFIG_DEBUG_S3C_UART)
#endif
.endm
/* include the reset of the code which will do the work, we're only
* compiling for a single cpu processor type so the default of s3c2440
* will be fine with us.
*/
#include <plat/debug-macro.S>

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arch/arm/mach-s3c6400/include/mach/dma.h Normal file
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/* linux/arch/arm/mach-s3c6400/include/mach/dma.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C6400 - DMA support
*/
#ifndef __ASM_ARCH_DMA_H
#define __ASM_ARCH_DMA_H __FILE__
/* currently nothing here, placeholder */
#endif /* __ASM_ARCH_IRQ_H */

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arch/arm/mach-s3c6400/include/mach/entry-macro.S Normal file
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/* arch/arm/mach-s3c6400/include/mach/entry-macro.S
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* Low-level IRQ helper macros for the Samsung S3C64XX series
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <asm/hardware/vic.h>
#include <mach/map.h>
#include <plat/irqs.h>
.macro disable_fiq
.endm
.macro get_irqnr_preamble, base, tmp
ldr \base, =S3C_VA_VIC0
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
@ check the vic0
mov \irqnr, # S3C_IRQ_OFFSET + 31
ldr \irqstat, [ \base, # VIC_IRQ_STATUS ]
teq \irqstat, #0
@ otherwise try vic1
addeq \tmp, \base, #(S3C_VA_VIC1 - S3C_VA_VIC0)
addeq \irqnr, \irqnr, #32
ldreq \irqstat, [ \tmp, # VIC_IRQ_STATUS ]
teqeq \irqstat, #0
clzne \irqstat, \irqstat
subne \irqnr, \irqnr, \irqstat
.endm

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arch/arm/mach-s3c6400/include/mach/gpio-core.h Normal file
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/* arch/arm/mach-s3c6400/include/mach/gpio-core.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C64XX - GPIO core support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_GPIO_CORE_H
#define __ASM_ARCH_GPIO_CORE_H __FILE__
/* currently we just include the platform support */
#include <plat/gpio-core.h>
#endif /* __ASM_ARCH_GPIO_CORE_H */

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arch/arm/mach-s3c6400/include/mach/gpio.h Normal file
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/* arch/arm/mach-s3c6400/include/mach/gpio.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S3C6400 - GPIO lib support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define gpio_get_value __gpio_get_value
#define gpio_set_value __gpio_set_value
#define gpio_cansleep __gpio_cansleep
#define gpio_to_irq __gpio_to_irq
/* GPIO bank sizes */
#define S3C64XX_GPIO_A_NR (8)
#define S3C64XX_GPIO_B_NR (7)
#define S3C64XX_GPIO_C_NR (8)
#define S3C64XX_GPIO_D_NR (5)
#define S3C64XX_GPIO_E_NR (5)
#define S3C64XX_GPIO_F_NR (16)
#define S3C64XX_GPIO_G_NR (7)
#define S3C64XX_GPIO_H_NR (10)
#define S3C64XX_GPIO_I_NR (16)
#define S3C64XX_GPIO_J_NR (12)
#define S3C64XX_GPIO_K_NR (16)
#define S3C64XX_GPIO_L_NR (15)
#define S3C64XX_GPIO_M_NR (6)
#define S3C64XX_GPIO_N_NR (16)
#define S3C64XX_GPIO_O_NR (16)
#define S3C64XX_GPIO_P_NR (15)
#define S3C64XX_GPIO_Q_NR (9)
/* GPIO bank numbes */
/* CONFIG_S3C_GPIO_SPACE allows the user to select extra
* space for debugging purposes so that any accidental
* change from one gpio bank to another can be caught.
*/
#define S3C64XX_GPIO_NEXT(__gpio) \
((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
enum s3c_gpio_number {
S3C64XX_GPIO_A_START = 0,
S3C64XX_GPIO_B_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_A),
S3C64XX_GPIO_C_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_B),
S3C64XX_GPIO_D_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_C),
S3C64XX_GPIO_E_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_D),
S3C64XX_GPIO_F_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_E),
S3C64XX_GPIO_G_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_F),
S3C64XX_GPIO_H_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_G),
S3C64XX_GPIO_I_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_H),
S3C64XX_GPIO_J_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_I),
S3C64XX_GPIO_K_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_J),
S3C64XX_GPIO_L_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_K),
S3C64XX_GPIO_M_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_L),
S3C64XX_GPIO_N_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_M),
S3C64XX_GPIO_O_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_N),
S3C64XX_GPIO_P_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_O),
S3C64XX_GPIO_Q_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_P),
};
/* S3C64XX GPIO number definitions. */
#define S3C64XX_GPA(_nr) (S3C64XX_GPIO_A_START + (_nr))
#define S3C64XX_GPB(_nr) (S3C64XX_GPIO_B_START + (_nr))
#define S3C64XX_GPC(_nr) (S3C64XX_GPIO_C_START + (_nr))
#define S3C64XX_GPD(_nr) (S3C64XX_GPIO_D_START + (_nr))
#define S3C64XX_GPE(_nr) (S3C64XX_GPIO_E_START + (_nr))
#define S3C64XX_GPF(_nr) (S3C64XX_GPIO_F_START + (_nr))
#define S3C64XX_GPG(_nr) (S3C64XX_GPIO_G_START + (_nr))
#define S3C64XX_GPH(_nr) (S3C64XX_GPIO_H_START + (_nr))
#define S3C64XX_GPI(_nr) (S3C64XX_GPIO_I_START + (_nr))
#define S3C64XX_GPJ(_nr) (S3C64XX_GPIO_J_START + (_nr))
#define S3C64XX_GPK(_nr) (S3C64XX_GPIO_K_START + (_nr))
#define S3C64XX_GPL(_nr) (S3C64XX_GPIO_L_START + (_nr))
#define S3C64XX_GPM(_nr) (S3C64XX_GPIO_M_START + (_nr))
#define S3C64XX_GPN(_nr) (S3C64XX_GPIO_N_START + (_nr))
#define S3C64XX_GPO(_nr) (S3C64XX_GPIO_O_START + (_nr))
#define S3C64XX_GPP(_nr) (S3C64XX_GPIO_P_START + (_nr))
#define S3C64XX_GPQ(_nr) (S3C64XX_GPIO_Q_START + (_nr))
/* the end of the S3C64XX specific gpios */
#define S3C64XX_GPIO_END (S3C64XX_GPQ(S3C64XX_GPIO_Q_NR) + 1)
#define S3C_GPIO_END S3C64XX_GPIO_END
/* define the number of gpios we need to the one after the GPQ() range */
#define ARCH_NR_GPIOS (S3C64XX_GPQ(S3C64XX_GPIO_Q_NR) + 1)
#include <asm-generic/gpio.h>

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/* linux/arch/arm/mach-s3c6400/include/mach/hardware.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C6400 - Hardware support
*/
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H __FILE__
/* currently nothing here, placeholder */
#endif /* __ASM_ARCH_IRQ_H */

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/* linux/arch/arm/mach-s3c6400/include/mach/irqs.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C6400 - IRQ definitions
*/
#ifndef __ASM_ARCH_IRQS_H
#define __ASM_ARCH_IRQS_H __FILE__
#ifndef __ASM_ARM_IRQ_H
#error "Do not include this directly, instead #include <asm/irq.h>"
#endif
#include <plat/irqs.h>
#endif /* __ASM_ARCH_IRQ_H */

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/* linux/arch/arm/mach-s3c6400/include/mach/map.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S3C64XX - Memory map definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_MAP_H
#define __ASM_ARCH_MAP_H __FILE__
#include <plat/map-base.h>
/* HSMMC units */
#define S3C64XX_PA_HSMMC(x) (0x7C200000 + ((x) * 0x100000))
#define S3C64XX_PA_HSMMC0 S3C64XX_PA_HSMMC(0)
#define S3C64XX_PA_HSMMC1 S3C64XX_PA_HSMMC(1)
#define S3C64XX_PA_HSMMC2 S3C64XX_PA_HSMMC(2)
#define S3C_PA_UART (0x7F005000)
#define S3C_PA_UART0 (S3C_PA_UART + 0x00)
#define S3C_PA_UART1 (S3C_PA_UART + 0x400)
#define S3C_PA_UART2 (S3C_PA_UART + 0x800)
#define S3C_PA_UART3 (S3C_PA_UART + 0xC00)
#define S3C_UART_OFFSET (0x400)
/* See notes on UART VA mapping in debug-macro.S */
#define S3C_VA_UARTx(x) (S3C_VA_UART + (S3C_PA_UART & 0xfffff) + ((x) * S3C_UART_OFFSET))
#define S3C_VA_UART0 S3C_VA_UARTx(0)
#define S3C_VA_UART1 S3C_VA_UARTx(1)
#define S3C_VA_UART2 S3C_VA_UARTx(2)
#define S3C_VA_UART3 S3C_VA_UARTx(3)
#define S3C64XX_PA_FB (0x77100000)
#define S3C64XX_PA_SYSCON (0x7E00F000)
#define S3C64XX_PA_TIMER (0x7F006000)
#define S3C64XX_PA_IIC0 (0x7F004000)
#define S3C64XX_PA_IIC1 (0x7F00F000)
#define S3C64XX_PA_GPIO (0x7F008000)
#define S3C64XX_VA_GPIO S3C_ADDR(0x00500000)
#define S3C64XX_SZ_GPIO SZ_4K
#define S3C64XX_PA_SDRAM (0x50000000)
#define S3C64XX_PA_VIC0 (0x71200000)
#define S3C64XX_PA_VIC1 (0x71300000)
/* place VICs close together */
#define S3C_VA_VIC0 (S3C_VA_IRQ + 0x00)
#define S3C_VA_VIC1 (S3C_VA_IRQ + 0x10000)
/* compatibiltiy defines. */
#define S3C_PA_TIMER S3C64XX_PA_TIMER
#define S3C_PA_HSMMC0 S3C64XX_PA_HSMMC0
#define S3C_PA_HSMMC1 S3C64XX_PA_HSMMC1
#define S3C_PA_HSMMC2 S3C64XX_PA_HSMMC2
#define S3C_PA_IIC S3C64XX_PA_IIC0
#define S3C_PA_IIC1 S3C64XX_PA_IIC1
#define S3C_PA_FB S3C64XX_PA_FB
#endif /* __ASM_ARCH_6400_MAP_H */

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/* arch/arm/mach-s3c6400/include/mach/memory.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_MEMORY_H
#define __ASM_ARCH_MEMORY_H
#define PHYS_OFFSET UL(0x50000000)
#endif

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/* linux/arch/arm/mach-s3c6400/include/mach/pwm-clock.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C64xx - pwm clock and timer support
*/
/**
* pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
* @tcfg: The timer TCFG1 register bits shifted down to 0.
*
* Return true if the given configuration from TCFG1 is a TCLK instead
* any of the TDIV clocks.
*/
static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
{
return tcfg >= S3C64XX_TCFG1_MUX_TCLK;
}
/**
* tcfg_to_divisor() - convert tcfg1 setting to a divisor
* @tcfg1: The tcfg1 setting, shifted down.
*
* Get the divisor value for the given tcfg1 setting. We assume the
* caller has already checked to see if this is not a TCLK source.
*/
static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
{
return 1 << tcfg1;
}
/**
* pwm_tdiv_has_div1() - does the tdiv setting have a /1
*
* Return true if we have a /1 in the tdiv setting.
*/
static inline unsigned int pwm_tdiv_has_div1(void)
{
return 1;
}
/**
* pwm_tdiv_div_bits() - calculate TCFG1 divisor value.
* @div: The divisor to calculate the bit information for.
*
* Turn a divisor into the necessary bit field for TCFG1.
*/
static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
{
return ilog2(div);
}
#define S3C_TCFG1_MUX_TCLK S3C64XX_TCFG1_MUX_TCLK

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/* arch/arm/mach-s3c6400/include/mach/regs-fb.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S3C64XX - new-style framebuffer register definitions
*
* This is the register set for the new style framebuffer interface
* found from the S3C2443 onwards and specifically the S3C64XX series
* S3C6400 and S3C6410.
*
* The file contains the cpu specific items which change between whichever
* architecture is selected. See <plat/regs-fb.h> for the core definitions
* that are the same.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/* include the core definitions here, in case we really do need to
* override them at a later date.
*/
#include <plat/regs-fb.h>
#define S3C_FB_MAX_WIN (5) /* number of hardware windows available. */
#define VIDCON1_FSTATUS_EVEN (1 << 15)
/* Video timing controls */
#define VIDTCON0 (0x10)
#define VIDTCON1 (0x14)
#define VIDTCON2 (0x18)
/* Window position controls */
#define WINCON(_win) (0x20 + ((_win) * 4))
/* OSD1 and OSD4 do not have register D */
#define VIDOSD_A(_win) (0x40 + ((_win) * 16))
#define VIDOSD_B(_win) (0x44 + ((_win) * 16))
#define VIDOSD_C(_win) (0x48 + ((_win) * 16))
#define VIDOSD_D(_win) (0x4C + ((_win) * 16))
/* Video buffer addresses */
#define VIDW_BUF_START(_buff) (0xA0 + ((_buff) * 8))
#define VIDW_BUF_START1(_buff) (0xA4 + ((_buff) * 8))
#define VIDW_BUF_END(_buff) (0xD0 + ((_buff) * 8))
#define VIDW_BUF_END1(_buff) (0xD4 + ((_buff) * 8))
#define VIDW_BUF_SIZE(_buff) (0x100 + ((_buff) * 4))
#define VIDINTCON0 (0x130)
#define WxKEYCONy(_win, _con) ((0x140 + ((_win) * 8)) + ((_con) * 4))
/* WINCONx */
#define WINCONx_CSCWIDTH_MASK (0x3 << 26)
#define WINCONx_CSCWIDTH_SHIFT (26)
#define WINCONx_CSCWIDTH_WIDE (0x0 << 26)
#define WINCONx_CSCWIDTH_NARROW (0x3 << 26)
#define WINCONx_ENLOCAL (1 << 22)
#define WINCONx_BUFSTATUS (1 << 21)
#define WINCONx_BUFSEL (1 << 20)
#define WINCONx_BUFAUTOEN (1 << 19)
#define WINCONx_YCbCr (1 << 13)
#define WINCON1_LOCALSEL_CAMIF (1 << 23)
#define WINCON2_LOCALSEL_CAMIF (1 << 23)
#define WINCON2_BLD_PIX (1 << 6)
#define WINCON2_ALPHA_SEL (1 << 1)
#define WINCON2_BPPMODE_MASK (0xf << 2)
#define WINCON2_BPPMODE_SHIFT (2)
#define WINCON2_BPPMODE_1BPP (0x0 << 2)
#define WINCON2_BPPMODE_2BPP (0x1 << 2)
#define WINCON2_BPPMODE_4BPP (0x2 << 2)
#define WINCON2_BPPMODE_8BPP_1232 (0x4 << 2)
#define WINCON2_BPPMODE_16BPP_565 (0x5 << 2)
#define WINCON2_BPPMODE_16BPP_A1555 (0x6 << 2)
#define WINCON2_BPPMODE_16BPP_I1555 (0x7 << 2)
#define WINCON2_BPPMODE_18BPP_666 (0x8 << 2)
#define WINCON2_BPPMODE_18BPP_A1665 (0x9 << 2)
#define WINCON2_BPPMODE_19BPP_A1666 (0xa << 2)
#define WINCON2_BPPMODE_24BPP_888 (0xb << 2)
#define WINCON2_BPPMODE_24BPP_A1887 (0xc << 2)
#define WINCON2_BPPMODE_25BPP_A1888 (0xd << 2)
#define WINCON2_BPPMODE_28BPP_A4888 (0xd << 2)
#define WINCON3_BLD_PIX (1 << 6)
#define WINCON3_ALPHA_SEL (1 << 1)
#define WINCON3_BPPMODE_MASK (0xf << 2)
#define WINCON3_BPPMODE_SHIFT (2)
#define WINCON3_BPPMODE_1BPP (0x0 << 2)
#define WINCON3_BPPMODE_2BPP (0x1 << 2)
#define WINCON3_BPPMODE_4BPP (0x2 << 2)
#define WINCON3_BPPMODE_16BPP_565 (0x5 << 2)
#define WINCON3_BPPMODE_16BPP_A1555 (0x6 << 2)
#define WINCON3_BPPMODE_16BPP_I1555 (0x7 << 2)
#define WINCON3_BPPMODE_18BPP_666 (0x8 << 2)
#define WINCON3_BPPMODE_18BPP_A1665 (0x9 << 2)
#define WINCON3_BPPMODE_19BPP_A1666 (0xa << 2)
#define WINCON3_BPPMODE_24BPP_888 (0xb << 2)
#define WINCON3_BPPMODE_24BPP_A1887 (0xc << 2)
#define WINCON3_BPPMODE_25BPP_A1888 (0xd << 2)
#define WINCON3_BPPMODE_28BPP_A4888 (0xd << 2)
#define VIDINTCON0_FIFIOSEL_WINDOW2 (0x10 << 5)
#define VIDINTCON0_FIFIOSEL_WINDOW3 (0x20 << 5)
#define VIDINTCON0_FIFIOSEL_WINDOW4 (0x40 << 5)
#define DITHMODE (0x170)
#define WINxMAP(_win) (0x180 + ((_win) * 4))
#define DITHMODE_R_POS_MASK (0x3 << 5)
#define DITHMODE_R_POS_SHIFT (5)
#define DITHMODE_R_POS_8BIT (0x0 << 5)
#define DITHMODE_R_POS_6BIT (0x1 << 5)
#define DITHMODE_R_POS_5BIT (0x2 << 5)
#define DITHMODE_G_POS_MASK (0x3 << 3)
#define DITHMODE_G_POS_SHIFT (3)
#define DITHMODE_G_POS_8BIT (0x0 << 3)
#define DITHMODE_G_POS_6BIT (0x1 << 3)
#define DITHMODE_G_POS_5BIT (0x2 << 3)
#define DITHMODE_B_POS_MASK (0x3 << 1)
#define DITHMODE_B_POS_SHIFT (1)
#define DITHMODE_B_POS_8BIT (0x0 << 1)
#define DITHMODE_B_POS_6BIT (0x1 << 1)
#define DITHMODE_B_POS_5BIT (0x2 << 1)
#define DITHMODE_DITH_EN (1 << 0)
#define WPALCON (0x1A0)
#define WPALCON_W4PAL_16BPP_A555 (1 << 8)
#define WPALCON_W3PAL_16BPP_A555 (1 << 7)
#define WPALCON_W2PAL_16BPP_A555 (1 << 6)
/* Palette registers */
#define WIN2_PAL(_entry) (0x300 + ((_entry) * 2))
#define WIN3_PAL(_entry) (0x320 + ((_entry) * 2))
#define WIN4_PAL(_entry) (0x340 + ((_entry) * 2))
#define WIN0_PAL(_entry) (0x400 + ((_entry) * 4))
#define WIN1_PAL(_entry) (0x800 + ((_entry) * 4))
/* system specific implementation code for palette sizes, and other
* information that changes depending on which architecture is being
* compiled.
*/
/* return true if window _win has OSD register D */
#define s3c_fb_has_osd_d(_win) ((_win) != 4 && (_win) != 0)
static inline unsigned int s3c_fb_win_pal_size(unsigned int win)
{
if (win < 2)
return 256;
if (win < 4)
return 16;
if (win == 4)
return 4;
BUG(); /* shouldn't get here */
}
static inline int s3c_fb_validate_win_bpp(unsigned int win, unsigned int bpp)
{
/* all windows can do 1/2 bpp */
if ((bpp == 25 || bpp == 19) && win == 0)
return 0; /* win 0 does not have 19 or 25bpp modes */
if (bpp == 4 && win == 4)
return 0;
if (bpp == 8 && (win >= 3))
return 0; /* win 3/4 cannot do 8bpp in any mode */
return 1;
}
static inline unsigned int s3c_fb_pal_reg(unsigned int window, int reg)
{
switch (window) {
case 0: return WIN0_PAL(reg);
case 1: return WIN1_PAL(reg);
case 2: return WIN2_PAL(reg);
case 3: return WIN3_PAL(reg);
case 4: return WIN4_PAL(reg);
}
BUG();
}
static inline int s3c_fb_pal_is16(unsigned int window)
{
return window > 1;
}
struct s3c_fb_palette {
struct fb_bitfield r;
struct fb_bitfield g;
struct fb_bitfield b;
struct fb_bitfield a;
};
static inline void s3c_fb_init_palette(unsigned int window,
struct s3c_fb_palette *palette)
{
if (window < 2) {
/* Windows 0/1 are 8/8/8 or A/8/8/8 */
palette->r.offset = 16;
palette->r.length = 8;
palette->g.offset = 8;
palette->g.length = 8;
palette->b.offset = 0;
palette->b.length = 8;
} else {
/* currently we assume RGB 5/6/5 */
palette->r.offset = 11;
palette->r.length = 5;
palette->g.offset = 5;
palette->g.length = 6;
palette->b.offset = 0;
palette->b.length = 5;
}
}
/* Notes on per-window bpp settings
*
* Value Win0 Win1 Win2 Win3 Win 4
* 0000 1(P) 1(P) 1(P) 1(P) 1(P)
* 0001 2(P) 2(P) 2(P) 2(P) 2(P)
* 0010 4(P) 4(P) 4(P) 4(P) -none-
* 0011 8(P) 8(P) -none- -none- -none-
* 0100 -none- 8(A232) 8(A232) -none- -none-
* 0101 16(565) 16(565) 16(565) 16(565) 16(565)
* 0110 -none- 16(A555) 16(A555) 16(A555) 16(A555)
* 0111 16(I555) 16(I565) 16(I555) 16(I555) 16(I555)
* 1000 18(666) 18(666) 18(666) 18(666) 18(666)
* 1001 -none- 18(A665) 18(A665) 18(A665) 16(A665)
* 1010 -none- 19(A666) 19(A666) 19(A666) 19(A666)
* 1011 24(888) 24(888) 24(888) 24(888) 24(888)
* 1100 -none- 24(A887) 24(A887) 24(A887) 24(A887)
* 1101 -none- 25(A888) 25(A888) 25(A888) 25(A888)
* 1110 -none- -none- -none- -none- -none-
* 1111 -none- -none- -none- -none- -none-
*/

20
arch/arm/mach-s3c6400/include/mach/regs-irq.h Normal file
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/* linux/arch/arm/mach-s3c6400/include/mach/regs-irq.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S3C64XX - IRQ register definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_REGS_IRQ_H
#define __ASM_ARCH_REGS_IRQ_H __FILE__
#include <asm/hardware/vic.h>
#endif /* __ASM_ARCH_6400_REGS_IRQ_H */

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arch/arm/mach-s3c6400/include/mach/system.h Normal file
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/* linux/arch/arm/mach-s3c6400/include/mach/system.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C6400 - system implementation
*/
#ifndef __ASM_ARCH_SYSTEM_H
#define __ASM_ARCH_SYSTEM_H __FILE__
static void arch_idle(void)
{
/* nothing here yet */
}
static void arch_reset(char mode)
{
/* nothing here yet */
}
#endif /* __ASM_ARCH_IRQ_H */

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arch/arm/mach-s3c6400/include/mach/tick.h Normal file
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/* linux/arch/arm/mach-s3c6400/include/mach/tick.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S3C64XX - Timer tick support definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_TICK_H
#define __ASM_ARCH_TICK_H __FILE__
/* note, the timer interrutps turn up in 2 places, the vic and then
* the timer block. We take the VIC as the base at the moment.
*/
static inline u32 s3c24xx_ostimer_pending(void)
{
u32 pend = __raw_readl(S3C_VA_VIC0 + VIC_RAW_STATUS);
return pend & 1 << (IRQ_TIMER4_VIC - S3C64XX_IRQ_VIC0(0));
}
#define TICK_MAX (0xffffffff)
#endif /* __ASM_ARCH_6400_TICK_H */

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arch/arm/mach-s3c6400/include/mach/uncompress.h Normal file
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/* arch/arm/mach-s3c6400/include/mach/uncompress.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S3C6400 - uncompress code
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_UNCOMPRESS_H
#define __ASM_ARCH_UNCOMPRESS_H
#include <mach/map.h>
#include <plat/uncompress.h>
static void arch_detect_cpu(void)
{
/* we do not need to do any cpu detection here at the moment. */
fifo_mask = S3C2440_UFSTAT_TXMASK;
fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT;
}
#endif /* __ASM_ARCH_UNCOMPRESS_H */

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arch/arm/mach-s3c6410/Kconfig Normal file
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# arch/arm/mach-s3c6410/Kconfig
#
# Copyright 2008 Openmoko, Inc.
# Copyright 2008 Simtec Electronics
#
# Licensed under GPLv2
# Configuration options for the S3C6410 CPU
config CPU_S3C6410
bool
select CPU_S3C6400_INIT
select CPU_S3C6400_CLOCK
help
Enable S3C6410 CPU support
config S3C6410_SETUP_SDHCI
bool
help
Internal helper functions for S3C6410 based SDHCI systems
config MACH_SMDK6410
bool "SMDK6410"
select CPU_S3C6410
select S3C_DEV_HSMMC
select S3C_DEV_HSMMC1
select S3C_DEV_I2C1
select S3C_DEV_FB
select S3C6410_SETUP_SDHCI
select S3C64XX_SETUP_I2C1
select S3C64XX_SETUP_FB_24BPP
help
Machine support for the Samsung SMDK6410
# At least some of the SMDK6410s were shipped with the card detect
# for the MMC/SD slots connected to the same input. This means that
# either the boards need to be altered to have channel0 to an alternate
# configuration or that only one slot can be used.
choice
prompt "SMDK6410 MMC/SD slot setup"
depends on MACH_SMDK6410
config SMDK6410_SD_CH0
bool "Use channel 0 only"
depends on MACH_SMDK6410
help
Select CON7 (channel 0) as the MMC/SD slot, as
at least some SMDK6410 boards come with the
resistors fitted so that the card detects for
channels 0 and 1 are the same.
config SMDK6410_SD_CH1
bool "Use channel 1 only"
depends on MACH_SMDK6410
help
Select CON6 (channel 1) as the MMC/SD slot, as
at least some SMDK6410 boards come with the
resistors fitted so that the card detects for
channels 0 and 1 are the same.
endchoice

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arch/arm/mach-s3c6410/Makefile Normal file
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# arch/arm/plat-s3c6410/Makefile
#
# Copyright 2008 Openmoko, Inc.
# Copyright 2008 Simtec Electronics
#
# Licensed under GPLv2
obj-y :=
obj-m :=
obj-n :=
obj- :=
# Core support for S3C6410 system
obj-$(CONFIG_CPU_S3C6410) += cpu.o
# Helper and device support
obj-$(CONFIG_S3C6410_SETUP_SDHCI) += setup-sdhci.o
# machine support
obj-$(CONFIG_MACH_SMDK6410) += mach-smdk6410.o

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arch/arm/mach-s3c6410/cpu.c Normal file
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/* linux/arch/arm/mach-s3c6410/cpu.c
*
* Copyright 2008 Simtec Electronics
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/sysdev.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <plat/cpu-freq.h>
#include <plat/regs-serial.h>
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/clock.h>
#include <plat/sdhci.h>
#include <plat/iic-core.h>
#include <plat/s3c6400.h>
#include <plat/s3c6410.h>
/* Initial IO mappings */
static struct map_desc s3c6410_iodesc[] __initdata = {
};
/* s3c6410_map_io
*
* register the standard cpu IO areas
*/
void __init s3c6410_map_io(void)
{
iotable_init(s3c6410_iodesc, ARRAY_SIZE(s3c6410_iodesc));
/* initialise device information early */
s3c6410_default_sdhci0();
s3c6410_default_sdhci1();
/* the i2c devices are directly compatible with s3c2440 */
s3c_i2c0_setname("s3c2440-i2c");
s3c_i2c1_setname("s3c2440-i2c");
}
void __init s3c6410_init_clocks(int xtal)
{
printk(KERN_DEBUG "%s: initialising clocks\n", __func__);
s3c24xx_register_baseclocks(xtal);
s3c64xx_register_clocks();
s3c6400_register_clocks();
s3c6400_setup_clocks();
}
void __init s3c6410_init_irq(void)
{
/* VIC0 is missing IRQ7, VIC1 is fully populated. */
s3c64xx_init_irq(~0 & ~(1 << 7), ~0);
}
struct sysdev_class s3c6410_sysclass = {
.name = "s3c6410-core",
};
static struct sys_device s3c6410_sysdev = {
.cls = &s3c6410_sysclass,
};
static int __init s3c6410_core_init(void)
{
return sysdev_class_register(&s3c6410_sysclass);
}
core_initcall(s3c6410_core_init);
int __init s3c6410_init(void)
{
printk("S3C6410: Initialising architecture\n");
return sysdev_register(&s3c6410_sysdev);
}

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/* linux/arch/arm/mach-s3c6410/mach-smdk6410.c
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/i2c.h>
#include <linux/fb.h>
#include <linux/gpio.h>
#include <linux/delay.h>
#include <video/platform_lcd.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <mach/hardware.h>
#include <mach/regs-fb.h>
#include <mach/map.h>
#include <asm/irq.h>
#include <asm/mach-types.h>
#include <plat/regs-serial.h>
#include <plat/iic.h>
#include <plat/fb.h>
#include <plat/s3c6410.h>
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
static struct s3c2410_uartcfg smdk6410_uartcfgs[] __initdata = {
[0] = {
.hwport = 0,
.flags = 0,
.ucon = 0x3c5,
.ulcon = 0x03,
.ufcon = 0x51,
},
[1] = {
.hwport = 1,
.flags = 0,
.ucon = 0x3c5,
.ulcon = 0x03,
.ufcon = 0x51,
},
};
/* framebuffer and LCD setup. */
/* GPF15 = LCD backlight control
* GPF13 => Panel power
* GPN5 = LCD nRESET signal
* PWM_TOUT1 => backlight brightness
*/
static void smdk6410_lcd_power_set(struct plat_lcd_data *pd,
unsigned int power)
{
if (power) {
gpio_direction_output(S3C64XX_GPF(13), 1);
gpio_direction_output(S3C64XX_GPF(15), 1);
/* fire nRESET on power up */
gpio_direction_output(S3C64XX_GPN(5), 0);
msleep(10);
gpio_direction_output(S3C64XX_GPN(5), 1);
msleep(1);
} else {
gpio_direction_output(S3C64XX_GPF(15), 0);
gpio_direction_output(S3C64XX_GPF(13), 0);
}
}
static struct plat_lcd_data smdk6410_lcd_power_data = {
.set_power = smdk6410_lcd_power_set,
};
static struct platform_device smdk6410_lcd_powerdev = {
.name = "platform-lcd",
.dev.parent = &s3c_device_fb.dev,
.dev.platform_data = &smdk6410_lcd_power_data,
};
static struct s3c_fb_pd_win smdk6410_fb_win0 = {
/* this is to ensure we use win0 */
.win_mode = {
.pixclock = 41094,
.left_margin = 8,
.right_margin = 13,
.upper_margin = 7,
.lower_margin = 5,
.hsync_len = 3,
.vsync_len = 1,
.xres = 800,
.yres = 480,
},
.max_bpp = 32,
.default_bpp = 16,
};
/* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
static struct s3c_fb_platdata smdk6410_lcd_pdata __initdata = {
.setup_gpio = s3c64xx_fb_gpio_setup_24bpp,
.win[0] = &smdk6410_fb_win0,
.vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
.vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
};
struct map_desc smdk6410_iodesc[] = {};
static struct platform_device *smdk6410_devices[] __initdata = {
#ifdef CONFIG_SMDK6410_SD_CH0
&s3c_device_hsmmc0,
#endif
#ifdef CONFIG_SMDK6410_SD_CH1
&s3c_device_hsmmc1,
#endif
&s3c_device_i2c0,
&s3c_device_i2c1,
&s3c_device_fb,
&smdk6410_lcd_powerdev,
};
static struct i2c_board_info i2c_devs0[] __initdata = {
{ I2C_BOARD_INFO("24c08", 0x50), },
{ I2C_BOARD_INFO("WM8580", 0X1b), },
};
static struct i2c_board_info i2c_devs1[] __initdata = {
{ I2C_BOARD_INFO("24c128", 0x57), }, /* Samsung S524AD0XD1 */
};
static void __init smdk6410_map_io(void)
{
s3c64xx_init_io(smdk6410_iodesc, ARRAY_SIZE(smdk6410_iodesc));
s3c24xx_init_clocks(12000000);
s3c24xx_init_uarts(smdk6410_uartcfgs, ARRAY_SIZE(smdk6410_uartcfgs));
}
static void __init smdk6410_machine_init(void)
{
s3c_i2c0_set_platdata(NULL);
s3c_i2c1_set_platdata(NULL);
s3c_fb_set_platdata(&smdk6410_lcd_pdata);
i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
platform_add_devices(smdk6410_devices, ARRAY_SIZE(smdk6410_devices));
}
MACHINE_START(SMDK6410, "SMDK6410")
/* Maintainer: Ben Dooks <ben@fluff.org> */
.phys_io = S3C_PA_UART & 0xfff00000,
.io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
.boot_params = S3C64XX_PA_SDRAM + 0x100,
.init_irq = s3c6410_init_irq,
.map_io = smdk6410_map_io,
.init_machine = smdk6410_machine_init,
.timer = &s3c24xx_timer,
MACHINE_END

102
arch/arm/mach-s3c6410/setup-sdhci.c Normal file
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@ -0,0 +1,102 @@
/* linux/arch/arm/mach-s3c6410/setup-sdhci.c
*
* Copyright 2008 Simtec Electronics
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C6410 - Helper functions for settign up SDHCI device(s) (HSMMC)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/mmc/card.h>
#include <linux/mmc/host.h>
#include <mach/gpio.h>
#include <plat/gpio-cfg.h>
#include <plat/regs-sdhci.h>
#include <plat/sdhci.h>
/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
char *s3c6410_hsmmc_clksrcs[4] = {
[0] = "hsmmc",
[1] = "hsmmc",
[2] = "mmc_bus",
/* [3] = "48m", - note not succesfully used yet */
};
void s3c6410_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
{
unsigned int gpio;
unsigned int end;
end = S3C64XX_GPG(2 + width);
/* Set all the necessary GPG pins to special-function 0 */
for (gpio = S3C64XX_GPG(0); gpio < end; gpio++) {
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
}
s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP);
s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(2));
}
void s3c6410_setup_sdhci0_cfg_card(struct platform_device *dev,
void __iomem *r,
struct mmc_ios *ios,
struct mmc_card *card)
{
u32 ctrl2, ctrl3;
/* don't need to alter anything acording to card-type */
writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA, r + S3C64XX_SDHCI_CONTROL4);
ctrl2 = readl(r + S3C_SDHCI_CONTROL2);
ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
S3C_SDHCI_CTRL2_ENFBCLKRX |
S3C_SDHCI_CTRL2_DFCNT_NONE |
S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
if (ios->clock < 25 * 1000000)
ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 |
S3C_SDHCI_CTRL3_FCSEL2 |
S3C_SDHCI_CTRL3_FCSEL1 |
S3C_SDHCI_CTRL3_FCSEL0);
else
ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
printk(KERN_INFO "%s: CTRL 2=%08x, 3=%08x\n", __func__, ctrl2, ctrl3);
writel(ctrl2, r + S3C_SDHCI_CONTROL2);
writel(ctrl3, r + S3C_SDHCI_CONTROL3);
}
void s3c6410_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
{
unsigned int gpio;
unsigned int end;
end = S3C64XX_GPH(2 + width);
/* Set all the necessary GPG pins to special-function 0 */
for (gpio = S3C64XX_GPH(0); gpio < end; gpio++) {
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
}
s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP);
s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(3));
}

90
arch/arm/plat-s3c/Kconfig
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@ -6,8 +6,8 @@
config PLAT_S3C
bool
depends on ARCH_S3C2410
default y if ARCH_S3C2410
depends on ARCH_S3C2410 || ARCH_S3C24A0 || ARCH_S3C64XX
default y
select NO_IOPORT
help
Base platform code for any Samsung S3C device
@ -16,24 +16,24 @@ config PLAT_S3C
config CPU_LLSERIAL_S3C2410_ONLY
bool
depends on ARCH_S3C2410
depends on PLAT_S3C
default y if CPU_LLSERIAL_S3C2410 && !CPU_LLSERIAL_S3C2440
config CPU_LLSERIAL_S3C2440_ONLY
bool
depends on ARCH_S3C2410
depends on PLAT_S3C
default y if CPU_LLSERIAL_S3C2440 && !CPU_LLSERIAL_S3C2410
config CPU_LLSERIAL_S3C2410
bool
depends on ARCH_S3C2410
depends on PLAT_S3C
help
Selected if there is an S3C2410 (or register compatible) serial
low-level implementation needed
config CPU_LLSERIAL_S3C2440
bool
depends on ARCH_S3C2410
depends on PLAT_S3C
help
Selected if there is an S3C2440 (or register compatible) serial
low-level implementation needed
@ -57,6 +57,14 @@ config S3C_BOOT_ERROR_RESET
Say y here to use the watchdog to reset the system if the
kernel decompressor detects an error during decompression.
config S3C_BOOT_UART_FORCE_FIFO
bool "Force UART FIFO on during boot process"
depends on PLAT_S3C
default y
help
Say Y here to force the UART FIFOs on during the kernel
uncompressor
comment "Power management"
config S3C2410_PM_DEBUG
@ -102,3 +110,73 @@ config S3C_LOWLEVEL_UART_PORT
such as the `Uncompressing...` at start time. The value of
this configuration should be between zero and two. The port
must have been initialised by the boot-loader before use.
# options for gpiolib support
config S3C_GPIO_SPACE
int "Space between gpio banks"
default 0
help
Add a number of spare GPIO entries between each bank for debugging
purposes. This allows any problems where an counter overflows from
one bank to another to be caught, at the expense of using a little
more memory.
config S3C_GPIO_TRACK
bool
help
Internal configuration option to enable the s3c specific gpio
chip tracking if the platform requires it.
config S3C_GPIO_PULL_UPDOWN
bool
help
Internal configuration to enable the correct GPIO pull helper
config S3C_GPIO_PULL_DOWN
bool
help
Internal configuration to enable the correct GPIO pull helper
config S3C_GPIO_PULL_UP
bool
help
Internal configuration to enable the correct GPIO pull helper
config S3C_GPIO_CFG_S3C24XX
bool
help
Internal configuration to enable S3C24XX style GPIO configuration
functions.
config S3C_GPIO_CFG_S3C64XX
bool
help
Internal configuration to enable S3C64XX style GPIO configuration
functions.
# device definitions to compile in
config S3C_DEV_HSMMC
bool
depends on PLAT_S3C
help
Compile in platform device definitions for HSMMC code
config S3C_DEV_HSMMC1
bool
depends on PLAT_S3C
help
Compile in platform device definitions for HSMMC channel 1
config S3C_DEV_I2C1
bool
depends on PLAT_S3C
help
Compile in platform device definitions for I2C channel 1
config S3C_DEV_FB
bool
depends on PLAT_S3C
help
Compile in platform device definition for framebuffer

28
arch/arm/plat-s3c/Makefile
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@ -1,3 +1,27 @@
# dummy makefile, currently just including asm/arm/plat-s3c/include/plat
# arch/arm/plat-s3c/Makefile
#
# Copyright 2008 Simtec Electronics
#
# Licensed under GPLv2
obj-n := dummy.o
obj-y :=
obj-m :=
obj-n :=
obj- :=
# Core support for all Samsung SoCs
obj-y += init.o
obj-y += time.o
obj-y += clock.o
obj-y += pwm-clock.o
obj-y += gpio.o
obj-y += gpio-config.o
# devices
obj-$(CONFIG_S3C_DEV_HSMMC) += dev-hsmmc.o
obj-$(CONFIG_S3C_DEV_HSMMC1) += dev-hsmmc1.o
obj-y += dev-i2c0.o
obj-$(CONFIG_S3C_DEV_I2C1) += dev-i2c1.o
obj-$(CONFIG_S3C_DEV_FB) += dev-fb.o

368
arch/arm/plat-s3c/clock.c Normal file
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@ -0,0 +1,368 @@
/* linux/arch/arm/plat-s3c24xx/clock.c
*
* Copyright (c) 2004-2005 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* S3C24XX Core clock control support
*
* Based on, and code from linux/arch/arm/mach-versatile/clock.c
**
** Copyright (C) 2004 ARM Limited.
** Written by Deep Blue Solutions Limited.
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/sysdev.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/clk.h>
#include <linux/spinlock.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <plat/cpu-freq.h>
#include <plat/clock.h>
#include <plat/cpu.h>
/* clock information */
static LIST_HEAD(clocks);
/* We originally used an mutex here, but some contexts (see resume)
* are calling functions such as clk_set_parent() with IRQs disabled
* causing an BUG to be triggered.
*/
DEFINE_SPINLOCK(clocks_lock);
/* enable and disable calls for use with the clk struct */
static int clk_null_enable(struct clk *clk, int enable)
{
return 0;
}
/* Clock API calls */
struct clk *clk_get(struct device *dev, const char *id)
{
struct clk *p;
struct clk *clk = ERR_PTR(-ENOENT);
int idno;
if (dev == NULL || dev->bus != &platform_bus_type)
idno = -1;
else
idno = to_platform_device(dev)->id;
spin_lock(&clocks_lock);
list_for_each_entry(p, &clocks, list) {
if (p->id == idno &&
strcmp(id, p->name) == 0 &&
try_module_get(p->owner)) {
clk = p;
break;
}
}
/* check for the case where a device was supplied, but the
* clock that was being searched for is not device specific */
if (IS_ERR(clk)) {
list_for_each_entry(p, &clocks, list) {
if (p->id == -1 && strcmp(id, p->name) == 0 &&
try_module_get(p->owner)) {
clk = p;
break;
}
}
}
spin_unlock(&clocks_lock);
return clk;
}
void clk_put(struct clk *clk)
{
module_put(clk->owner);
}
int clk_enable(struct clk *clk)
{
if (IS_ERR(clk) || clk == NULL)
return -EINVAL;
clk_enable(clk->parent);
spin_lock(&clocks_lock);
if ((clk->usage++) == 0)
(clk->enable)(clk, 1);
spin_unlock(&clocks_lock);
return 0;
}
void clk_disable(struct clk *clk)
{
if (IS_ERR(clk) || clk == NULL)
return;
spin_lock(&clocks_lock);
if ((--clk->usage) == 0)
(clk->enable)(clk, 0);
spin_unlock(&clocks_lock);
clk_disable(clk->parent);
}
unsigned long clk_get_rate(struct clk *clk)
{
if (IS_ERR(clk))
return 0;
if (clk->rate != 0)
return clk->rate;
if (clk->get_rate != NULL)
return (clk->get_rate)(clk);
if (clk->parent != NULL)
return clk_get_rate(clk->parent);
return clk->rate;
}
long clk_round_rate(struct clk *clk, unsigned long rate)
{
if (!IS_ERR(clk) && clk->round_rate)
return (clk->round_rate)(clk, rate);
return rate;
}
int clk_set_rate(struct clk *clk, unsigned long rate)
{
int ret;
if (IS_ERR(clk))
return -EINVAL;
/* We do not default just do a clk->rate = rate as
* the clock may have been made this way by choice.
*/
WARN_ON(clk->set_rate == NULL);
if (clk->set_rate == NULL)
return -EINVAL;
spin_lock(&clocks_lock);
ret = (clk->set_rate)(clk, rate);
spin_unlock(&clocks_lock);
return ret;
}
struct clk *clk_get_parent(struct clk *clk)
{
return clk->parent;
}
int clk_set_parent(struct clk *clk, struct clk *parent)
{
int ret = 0;
if (IS_ERR(clk))
return -EINVAL;
spin_lock(&clocks_lock);
if (clk->set_parent)
ret = (clk->set_parent)(clk, parent);
spin_unlock(&clocks_lock);
return ret;
}
EXPORT_SYMBOL(clk_get);
EXPORT_SYMBOL(clk_put);
EXPORT_SYMBOL(clk_enable);
EXPORT_SYMBOL(clk_disable);
EXPORT_SYMBOL(clk_get_rate);
EXPORT_SYMBOL(clk_round_rate);
EXPORT_SYMBOL(clk_set_rate);
EXPORT_SYMBOL(clk_get_parent);
EXPORT_SYMBOL(clk_set_parent);
/* base clocks */
static int clk_default_setrate(struct clk *clk, unsigned long rate)
{
clk->rate = rate;
return 0;
}
struct clk clk_xtal = {
.name = "xtal",
.id = -1,
.rate = 0,
.parent = NULL,
.ctrlbit = 0,
};
struct clk clk_ext = {
.name = "ext",
.id = -1,
};
struct clk clk_epll = {
.name = "epll",
.id = -1,
};
struct clk clk_mpll = {
.name = "mpll",
.id = -1,
.set_rate = clk_default_setrate,
};
struct clk clk_upll = {
.name = "upll",
.id = -1,
.parent = NULL,
.ctrlbit = 0,
};
struct clk clk_f = {
.name = "fclk",
.id = -1,
.rate = 0,
.parent = &clk_mpll,
.ctrlbit = 0,
.set_rate = clk_default_setrate,
};
struct clk clk_h = {
.name = "hclk",
.id = -1,
.rate = 0,
.parent = NULL,
.ctrlbit = 0,
.set_rate = clk_default_setrate,
};
struct clk clk_p = {
.name = "pclk",
.id = -1,
.rate = 0,
.parent = NULL,
.ctrlbit = 0,
.set_rate = clk_default_setrate,
};
struct clk clk_usb_bus = {
.name = "usb-bus",
.id = -1,
.rate = 0,
.parent = &clk_upll,
};
struct clk s3c24xx_uclk = {
.name = "uclk",
.id = -1,
};
/* initialise the clock system */
int s3c24xx_register_clock(struct clk *clk)
{
clk->owner = THIS_MODULE;
if (clk->enable == NULL)
clk->enable = clk_null_enable;
/* add to the list of available clocks */
/* Quick check to see if this clock has already been registered. */
BUG_ON(clk->list.prev != clk->list.next);
spin_lock(&clocks_lock);
list_add(&clk->list, &clocks);
spin_unlock(&clocks_lock);
return 0;
}
int s3c24xx_register_clocks(struct clk **clks, int nr_clks)
{
int fails = 0;
for (; nr_clks > 0; nr_clks--, clks++) {
if (s3c24xx_register_clock(*clks) < 0)
fails++;
}
return fails;
}
/* initalise all the clocks */
int __init s3c24xx_register_baseclocks(unsigned long xtal)
{
printk(KERN_INFO "S3C24XX Clocks, (c) 2004 Simtec Electronics\n");
clk_xtal.rate = xtal;
/* register our clocks */
if (s3c24xx_register_clock(&clk_xtal) < 0)
printk(KERN_ERR "failed to register master xtal\n");
if (s3c24xx_register_clock(&clk_mpll) < 0)
printk(KERN_ERR "failed to register mpll clock\n");
if (s3c24xx_register_clock(&clk_upll) < 0)
printk(KERN_ERR "failed to register upll clock\n");
if (s3c24xx_register_clock(&clk_f) < 0)
printk(KERN_ERR "failed to register cpu fclk\n");
if (s3c24xx_register_clock(&clk_h) < 0)
printk(KERN_ERR "failed to register cpu hclk\n");
if (s3c24xx_register_clock(&clk_p) < 0)
printk(KERN_ERR "failed to register cpu pclk\n");
return 0;
}

72
arch/arm/plat-s3c/dev-fb.c Normal file
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@ -0,0 +1,72 @@
/* linux/arch/arm/plat-s3c/dev-fb.c
*
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C series device definition for framebuffer device
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/platform_device.h>
#include <linux/fb.h>
#include <mach/map.h>
#include <mach/regs-fb.h>
#include <plat/fb.h>
#include <plat/devs.h>
#include <plat/cpu.h>
static struct resource s3c_fb_resource[] = {
[0] = {
.start = S3C_PA_FB,
.end = S3C_PA_FB + SZ_16K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_LCD_VSYNC,
.end = IRQ_LCD_VSYNC,
.flags = IORESOURCE_IRQ,
},
[2] = {
.start = IRQ_LCD_FIFO,
.end = IRQ_LCD_FIFO,
.flags = IORESOURCE_IRQ,
},
[3] = {
.start = IRQ_LCD_SYSTEM,
.end = IRQ_LCD_SYSTEM,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device s3c_device_fb = {
.name = "s3c-fb",
.id = -1,
.num_resources = ARRAY_SIZE(s3c_fb_resource),
.resource = s3c_fb_resource,
.dev.dma_mask = &s3c_device_fb.dev.coherent_dma_mask,
.dev.coherent_dma_mask = 0xffffffffUL,
};
void __init s3c_fb_set_platdata(struct s3c_fb_platdata *pd)
{
struct s3c_fb_platdata *npd;
if (!pd) {
printk(KERN_ERR "%s: no platform data\n", __func__);
return;
}
npd = kmemdup(pd, sizeof(struct s3c_fb_platdata), GFP_KERNEL);
if (!npd)
printk(KERN_ERR "%s: no memory for platform data\n", __func__);
s3c_device_fb.dev.platform_data = npd;
}

68
arch/arm/plat-s3c/dev-hsmmc.c Normal file
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@ -0,0 +1,68 @@
/* linux/arch/arm/plat-s3c/dev-hsmmc.c
*
* Copyright (c) 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C series device definition for hsmmc devices
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/mmc/host.h>
#include <mach/map.h>
#include <plat/sdhci.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#define S3C_SZ_HSMMC (0x1000)
static struct resource s3c_hsmmc_resource[] = {
[0] = {
.start = S3C_PA_HSMMC0,
.end = S3C_PA_HSMMC0 + S3C_SZ_HSMMC - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_HSMMC0,
.end = IRQ_HSMMC0,
.flags = IORESOURCE_IRQ,
}
};
static u64 s3c_device_hsmmc_dmamask = 0xffffffffUL;
struct s3c_sdhci_platdata s3c_hsmmc0_def_platdata = {
.max_width = 4,
.host_caps = (MMC_CAP_4_BIT_DATA |
MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
};
struct platform_device s3c_device_hsmmc0 = {
.name = "s3c-sdhci",
.id = 0,
.num_resources = ARRAY_SIZE(s3c_hsmmc_resource),
.resource = s3c_hsmmc_resource,
.dev = {
.dma_mask = &s3c_device_hsmmc_dmamask,
.coherent_dma_mask = 0xffffffffUL,
.platform_data = &s3c_hsmmc0_def_platdata,
},
};
void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd)
{
struct s3c_sdhci_platdata *set = &s3c_hsmmc0_def_platdata;
set->max_width = pd->max_width;
if (pd->cfg_gpio)
set->cfg_gpio = pd->cfg_gpio;
if (pd->cfg_card)
set->cfg_card = pd->cfg_card;
}

68
arch/arm/plat-s3c/dev-hsmmc1.c Normal file
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@ -0,0 +1,68 @@
/* linux/arch/arm/plat-s3c/dev-hsmmc1.c
*
* Copyright (c) 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C series device definition for hsmmc device 1
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/mmc/host.h>
#include <mach/map.h>
#include <plat/sdhci.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#define S3C_SZ_HSMMC (0x1000)
static struct resource s3c_hsmmc1_resource[] = {
[0] = {
.start = S3C_PA_HSMMC1,
.end = S3C_PA_HSMMC1 + S3C_SZ_HSMMC - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_HSMMC1,
.end = IRQ_HSMMC1,
.flags = IORESOURCE_IRQ,
}
};
static u64 s3c_device_hsmmc1_dmamask = 0xffffffffUL;
struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata = {
.max_width = 4,
.host_caps = (MMC_CAP_4_BIT_DATA |
MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
};
struct platform_device s3c_device_hsmmc1 = {
.name = "s3c-sdhci",
.id = 1,
.num_resources = ARRAY_SIZE(s3c_hsmmc1_resource),
.resource = s3c_hsmmc1_resource,
.dev = {
.dma_mask = &s3c_device_hsmmc1_dmamask,
.coherent_dma_mask = 0xffffffffUL,
.platform_data = &s3c_hsmmc1_def_platdata,
},
};
void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd)
{
struct s3c_sdhci_platdata *set = &s3c_hsmmc1_def_platdata;
set->max_width = pd->max_width;
if (pd->cfg_gpio)
set->cfg_gpio = pd->cfg_gpio;
if (pd->cfg_card)
set->cfg_card = pd->cfg_card;
}

71
arch/arm/plat-s3c/dev-i2c0.c Normal file
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@ -0,0 +1,71 @@
/* linux/arch/arm/plat-s3c/dev-i2c0.c
*
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C series device definition for i2c device 0
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/platform_device.h>
#include <mach/map.h>
#include <plat/regs-iic.h>
#include <plat/iic.h>
#include <plat/devs.h>
#include <plat/cpu.h>
static struct resource s3c_i2c_resource[] = {
[0] = {
.start = S3C_PA_IIC,
.end = S3C_PA_IIC + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_IIC,
.end = IRQ_IIC,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device s3c_device_i2c0 = {
.name = "s3c2410-i2c",
#ifdef CONFIG_S3C_DEV_I2C1
.id = 0,
#else
.id = -1,
#endif
.num_resources = ARRAY_SIZE(s3c_i2c_resource),
.resource = s3c_i2c_resource,
};
static struct s3c2410_platform_i2c default_i2c_data0 __initdata = {
.flags = 0,
.slave_addr = 0x10,
.bus_freq = 100*1000,
.max_freq = 400*1000,
.sda_delay = S3C2410_IICLC_SDA_DELAY5 | S3C2410_IICLC_FILTER_ON,
};
void __init s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *pd)
{
struct s3c2410_platform_i2c *npd;
if (!pd)
pd = &default_i2c_data0;
npd = kmemdup(pd, sizeof(struct s3c2410_platform_i2c), GFP_KERNEL);
if (!npd)
printk(KERN_ERR "%s: no memory for platform data\n", __func__);
else if (!npd->cfg_gpio)
npd->cfg_gpio = s3c_i2c0_cfg_gpio;
s3c_device_i2c0.dev.platform_data = npd;
}

68
arch/arm/plat-s3c/dev-i2c1.c Normal file
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@ -0,0 +1,68 @@
/* linux/arch/arm/plat-s3c/dev-i2c1.c
*
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C series device definition for i2c device 1
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/platform_device.h>
#include <mach/map.h>
#include <plat/regs-iic.h>
#include <plat/iic.h>
#include <plat/devs.h>
#include <plat/cpu.h>
static struct resource s3c_i2c_resource[] = {
[0] = {
.start = S3C_PA_IIC1,
.end = S3C_PA_IIC1 + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_IIC1,
.end = IRQ_IIC1,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device s3c_device_i2c1 = {
.name = "s3c2410-i2c",
.id = 1,
.num_resources = ARRAY_SIZE(s3c_i2c_resource),
.resource = s3c_i2c_resource,
};
static struct s3c2410_platform_i2c default_i2c_data1 __initdata = {
.flags = 0,
.bus_num = 1,
.slave_addr = 0x10,
.bus_freq = 100*1000,
.max_freq = 400*1000,
.sda_delay = S3C2410_IICLC_SDA_DELAY5 | S3C2410_IICLC_FILTER_ON,
};
void __init s3c_i2c1_set_platdata(struct s3c2410_platform_i2c *pd)
{
struct s3c2410_platform_i2c *npd;
if (!pd)
pd = &default_i2c_data1;
npd = kmemdup(pd, sizeof(struct s3c2410_platform_i2c), GFP_KERNEL);
if (!npd)
printk(KERN_ERR "%s: no memory for platform data\n", __func__);
else if (!npd->cfg_gpio)
npd->cfg_gpio = s3c_i2c1_cfg_gpio;
s3c_device_i2c1.dev.platform_data = npd;
}

163
arch/arm/plat-s3c/gpio-config.c Normal file
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@ -0,0 +1,163 @@
/* linux/arch/arm/plat-s3c/gpio-config.c
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C series GPIO configuration core
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/gpio.h>
#include <linux/io.h>
#include <mach/gpio-core.h>
#include <plat/gpio-cfg.h>
#include <plat/gpio-cfg-helpers.h>
int s3c_gpio_cfgpin(unsigned int pin, unsigned int config)
{
struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
unsigned long flags;
int offset;
int ret;
if (!chip)
return -EINVAL;
offset = pin - chip->chip.base;
local_irq_save(flags);
ret = s3c_gpio_do_setcfg(chip, offset, config);
local_irq_restore(flags);
return ret;
}
int s3c_gpio_setpull(unsigned int pin, s3c_gpio_pull_t pull)
{
struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
unsigned long flags;
int offset, ret;
if (!chip)
return -EINVAL;
offset = pin - chip->chip.base;
local_irq_save(flags);
ret = s3c_gpio_do_setpull(chip, offset, pull);
local_irq_restore(flags);
return ret;
}
#ifdef CONFIG_S3C_GPIO_CFG_S3C24XX
int s3c_gpio_setcfg_s3c24xx_banka(struct s3c_gpio_chip *chip,
unsigned int off, unsigned int cfg)
{
void __iomem *reg = chip->base;
unsigned int shift = off;
u32 con;
if (s3c_gpio_is_cfg_special(cfg)) {
cfg &= 0xf;
/* Map output to 0, and SFN2 to 1 */
cfg -= 1;
if (cfg > 1)
return -EINVAL;
cfg <<= shift;
}
con = __raw_readl(reg);
con &= ~(0x1 << shift);
con |= cfg;
__raw_writel(con, reg);
return 0;
}
int s3c_gpio_setcfg_s3c24xx(struct s3c_gpio_chip *chip,
unsigned int off, unsigned int cfg)
{
void __iomem *reg = chip->base;
unsigned int shift = off * 2;
u32 con;
if (s3c_gpio_is_cfg_special(cfg)) {
cfg &= 0xf;
if (cfg > 3)
return -EINVAL;
cfg <<= shift;
}
con = __raw_readl(reg);
con &= ~(0x3 << shift);
con |= cfg;
__raw_writel(con, reg);
return 0;
}
#endif
#ifdef CONFIG_S3C_GPIO_CFG_S3C64XX
int s3c_gpio_setcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip,
unsigned int off, unsigned int cfg)
{
void __iomem *reg = chip->base;
unsigned int shift = (off & 7) * 4;
u32 con;
if (off < 8 && chip->chip.ngpio >= 8)
reg -= 4;
if (s3c_gpio_is_cfg_special(cfg)) {
cfg &= 0xf;
cfg <<= shift;
}
con = __raw_readl(reg);
con &= ~(0xf << shift);
con |= cfg;
__raw_writel(con, reg);
return 0;
}
#endif /* CONFIG_S3C_GPIO_CFG_S3C64XX */
#ifdef CONFIG_S3C_GPIO_PULL_UPDOWN
int s3c_gpio_setpull_updown(struct s3c_gpio_chip *chip,
unsigned int off, s3c_gpio_pull_t pull)
{
void __iomem *reg = chip->base + 0x08;
int shift = off * 2;
u32 pup;
pup = __raw_readl(reg);
pup &= ~(3 << shift);
pup |= pull << shift;
__raw_writel(pup, reg);
return 0;
}
s3c_gpio_pull_t s3c_gpio_getpull_updown(struct s3c_gpio_chip *chip,
unsigned int off)
{
void __iomem *reg = chip->base + 0x08;
int shift = off * 2;
u32 pup = __raw_readl(reg);
pup >>= shift;
pup &= 0x3;
return (__force s3c_gpio_pull_t)pup;
}
#endif

147
arch/arm/plat-s3c/gpio.c Normal file
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@ -0,0 +1,147 @@
/* linux/arch/arm/plat-s3c/gpio.c
*
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C series GPIO core
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <plat/gpio-core.h>
#ifdef CONFIG_S3C_GPIO_TRACK
struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END];
static __init void s3c_gpiolib_track(struct s3c_gpio_chip *chip)
{
unsigned int gpn;
int i;
gpn = chip->chip.base;
for (i = 0; i < chip->chip.ngpio; i++, gpn++) {
BUG_ON(gpn > ARRAY_SIZE(s3c_gpios));
s3c_gpios[gpn] = chip;
}
}
#endif /* CONFIG_S3C_GPIO_TRACK */
/* Default routines for controlling GPIO, based on the original S3C24XX
* GPIO functions which deal with the case where each gpio bank of the
* chip is as following:
*
* base + 0x00: Control register, 2 bits per gpio
* gpio n: 2 bits starting at (2*n)
* 00 = input, 01 = output, others mean special-function
* base + 0x04: Data register, 1 bit per gpio
* bit n: data bit n
*/
static int s3c_gpiolib_input(struct gpio_chip *chip, unsigned offset)
{
struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
void __iomem *base = ourchip->base;
unsigned long flags;
unsigned long con;
local_irq_save(flags);
con = __raw_readl(base + 0x00);
con &= ~(3 << (offset * 2));
__raw_writel(con, base + 0x00);
local_irq_restore(flags);
return 0;
}
static int s3c_gpiolib_output(struct gpio_chip *chip,
unsigned offset, int value)
{
struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
void __iomem *base = ourchip->base;
unsigned long flags;
unsigned long dat;
unsigned long con;
local_irq_save(flags);
dat = __raw_readl(base + 0x04);
dat &= ~(1 << offset);
if (value)
dat |= 1 << offset;
__raw_writel(dat, base + 0x04);
con = __raw_readl(base + 0x00);
con &= ~(3 << (offset * 2));
con |= 1 << (offset * 2);
__raw_writel(con, base + 0x00);
__raw_writel(dat, base + 0x04);
local_irq_restore(flags);
return 0;
}
static void s3c_gpiolib_set(struct gpio_chip *chip,
unsigned offset, int value)
{
struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
void __iomem *base = ourchip->base;
unsigned long flags;
unsigned long dat;
local_irq_save(flags);
dat = __raw_readl(base + 0x04);
dat &= ~(1 << offset);
if (value)
dat |= 1 << offset;
__raw_writel(dat, base + 0x04);
local_irq_restore(flags);
}
static int s3c_gpiolib_get(struct gpio_chip *chip, unsigned offset)
{
struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
unsigned long val;
val = __raw_readl(ourchip->base + 0x04);
val >>= offset;
val &= 1;
return val;
}
__init void s3c_gpiolib_add(struct s3c_gpio_chip *chip)
{
struct gpio_chip *gc = &chip->chip;
int ret;
BUG_ON(!chip->base);
BUG_ON(!gc->label);
BUG_ON(!gc->ngpio);
if (!gc->direction_input)
gc->direction_input = s3c_gpiolib_input;
if (!gc->direction_output)
gc->direction_output = s3c_gpiolib_output;
if (!gc->set)
gc->set = s3c_gpiolib_set;
if (!gc->get)
gc->get = s3c_gpiolib_get;
/* gpiochip_add() prints own failure message on error. */
ret = gpiochip_add(gc);
if (ret >= 0)
s3c_gpiolib_track(chip);
}

18
arch/arm/plat-s3c/include/mach/io.h Normal file
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@ -0,0 +1,18 @@
/* arch/arm/plat-s3c/include/mach/io.h
*
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben-linux@fluff.org>
*
* Default IO routines for plat-s3c based systems, such as S3C24A0
*/
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
/* No current ISA/PCI bus support. */
#define __io(a) ((void __iomem *)(a))
#define __mem_pci(a) (a)
#define IO_SPACE_LIMIT (0xFFFFFFFF)
#endif

0
arch/arm/mach-s3c2410/include/mach/timex.h → arch/arm/plat-s3c/include/mach/timex.h
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2
arch/arm/mach-s3c2410/include/mach/vmalloc.h → arch/arm/plat-s3c/include/mach/vmalloc.h
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@ -1,4 +1,4 @@
/* arch/arm/mach-s3c2410/include/mach/vmalloc.h
/* arch/arm/plat-s3c/include/mach/vmalloc.h
*
* from arch/arm/mach-iop3xx/include/mach/vmalloc.h
*

29
arch/arm/plat-s3c/include/plat/adc.h Normal file
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@ -0,0 +1,29 @@
/* arch/arm/plat-s3c/include/plat/adc.h
*
* Copyright (c) 2008 Simtec Electronics
* http://armlinux.simnte.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S3C24XX ADC driver information
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_PLAT_ADC_H
#define __ASM_PLAT_ADC_H __FILE__
struct s3c_adc_client;
extern int s3c_adc_start(struct s3c_adc_client *client,
unsigned int channel, unsigned int nr_samples);
extern struct s3c_adc_client *s3c_adc_register(struct platform_device *pdev,
void (*select)(unsigned selected),
void (*conv)(unsigned d0, unsigned d1),
unsigned int is_ts);
extern void s3c_adc_release(struct s3c_adc_client *client);
#endif /* __ASM_PLAT_ADC_H */

38
arch/arm/plat-s3c24xx/include/plat/clock.h → arch/arm/plat-s3c/include/plat/clock.h
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@ -1,5 +1,4 @@
/* linux/include/asm-arm/plat-s3c24xx/clock.h
* linux/arch/arm/mach-s3c2410/clock.h
/* linux/arch/arm/plat-s3c/include/plat/clock.h
*
* Copyright (c) 2004-2005 Simtec Electronics
* http://www.simtec.co.uk/products/SWLINUX/
@ -10,6 +9,8 @@
* published by the Free Software Foundation.
*/
#include <linux/spinlock.h>
struct clk {
struct list_head list;
struct module *owner;
@ -44,21 +45,44 @@ extern struct clk clk_h;
extern struct clk clk_p;
extern struct clk clk_mpll;
extern struct clk clk_upll;
extern struct clk clk_epll;
extern struct clk clk_xtal;
extern struct clk clk_ext;
/* S3C64XX specific clocks */
extern struct clk clk_27m;
extern struct clk clk_48m;
/* exports for arch/arm/mach-s3c2410
*
* Please DO NOT use these outside of arch/arm/mach-s3c2410
*/
extern struct mutex clocks_mutex;
extern spinlock_t clocks_lock;
extern int s3c2410_clkcon_enable(struct clk *clk, int enable);
extern int s3c24xx_register_clock(struct clk *clk);
extern int s3c24xx_register_clocks(struct clk **clk, int nr_clks);
extern int s3c24xx_setup_clocks(unsigned long xtal,
unsigned long fclk,
unsigned long hclk,
unsigned long pclk);
extern int s3c24xx_register_baseclocks(unsigned long xtal);
extern void s3c64xx_register_clocks(void);
extern void s3c24xx_setup_clocks(unsigned long fclk,
unsigned long hclk,
unsigned long pclk);
extern void s3c2410_setup_clocks(void);
extern void s3c2412_setup_clocks(void);
extern void s3c244x_setup_clocks(void);
extern void s3c2443_setup_clocks(void);
/* S3C64XX specific functions and clocks */
extern int s3c64xx_sclk_ctrl(struct clk *clk, int enable);
/* Init for pwm clock code */
extern void s3c_pwmclk_init(void);

94
arch/arm/plat-s3c/include/plat/cpu-freq.h Normal file
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@ -0,0 +1,94 @@
/* arch/arm/plat-s3c/include/plat/cpu-freq.h
*
* Copyright (c) 2006,2007 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S3C CPU frequency scaling support - driver and board
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/cpufreq.h>
struct s3c_cpufreq_info;
struct s3c_cpufreq_board;
struct s3c_iotimings;
struct s3c_freq {
unsigned long fclk;
unsigned long armclk;
unsigned long hclk_tns; /* in 10ths of ns */
unsigned long hclk;
unsigned long pclk;
};
/* wrapper 'struct cpufreq_freqs' so that any drivers receiving the
* notification can use this information that is not provided by just
* having the core frequency alone.
*/
struct s3c_cpufreq_freqs {
struct cpufreq_freqs freqs;
struct s3c_freq old;
struct s3c_freq new;
};
#define to_s3c_cpufreq(_cf) container_of(_cf, struct s3c_cpufreq_freqs, freqs)
struct s3c_clkdivs {
int p_divisor; /* fclk / pclk */
int h_divisor; /* fclk / hclk */
int arm_divisor; /* not all cpus have this. */
unsigned char dvs; /* using dvs mode to arm. */
};
#define PLLVAL(_m, _p, _s) (((_m) << 12) | ((_p) << 4) | (_s))
struct s3c_pllval {
unsigned long freq;
unsigned long pll_reg;
};
struct s3c_cpufreq_config {
struct s3c_freq freq;
struct s3c_pllval pll;
struct s3c_clkdivs divs;
struct s3c_cpufreq_info *info; /* for core, not drivers */
struct s3c_cpufreq_board *board;
};
/* s3c_cpufreq_board
*
* per-board configuraton information, such as memory refresh and
* how to initialise IO timings.
*/
struct s3c_cpufreq_board {
unsigned int refresh; /* refresh period in ns */
unsigned int auto_io:1; /* automatically init io timings. */
unsigned int need_io:1; /* set if needs io timing support. */
/* any non-zero field in here is taken as an upper limit. */
struct s3c_freq max; /* frequency limits */
};
/* Things depending on frequency scaling. */
#ifdef CONFIG_CPU_FREQ_S3C
#define __init_or_cpufreq
#else
#define __init_or_cpufreq __init
#endif
/* Board functions */
#ifdef CONFIG_CPU_FREQ_S3C
extern int s3c_cpufreq_setboard(struct s3c_cpufreq_board *board);
#else
static inline int s3c_cpufreq_setboard(struct s3c_cpufreq_board *board)
{
return 0;
}
#endif /* CONFIG_CPU_FREQ_S3C */

21
arch/arm/plat-s3c24xx/include/plat/cpu.h → arch/arm/plat-s3c/include/plat/cpu.h
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@ -1,4 +1,4 @@
/* linux/include/asm-arm/plat-s3c24xx/cpu.h
/* linux/arch/arm/plat-s3c/include/plat/cpu.h
*
* Copyright (c) 2004-2005 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
@ -18,7 +18,7 @@
#define MHZ (1000*1000)
#endif
#define print_mhz(m) ((m) / MHZ), ((m / 1000) % 1000)
#define print_mhz(m) ((m) / MHZ), (((m) / 1000) % 1000)
/* forward declaration */
struct s3c24xx_uart_resources;
@ -26,11 +26,28 @@ struct platform_device;
struct s3c2410_uartcfg;
struct map_desc;
/* per-cpu initialisation function table. */
struct cpu_table {
unsigned long idcode;
unsigned long idmask;
void (*map_io)(void);
void (*init_uarts)(struct s3c2410_uartcfg *cfg, int no);
void (*init_clocks)(int xtal);
int (*init)(void);
const char *name;
};
extern void s3c_init_cpu(unsigned long idcode,
struct cpu_table *cpus, unsigned int cputab_size);
/* core initialisation functions */
extern void s3c24xx_init_irq(void);
extern void s3c64xx_init_irq(u32 vic0, u32 vic1);
extern void s3c24xx_init_io(struct map_desc *mach_desc, int size);
extern void s3c64xx_init_io(struct map_desc *mach_desc, int size);
extern void s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no);

2
arch/arm/plat-s3c/include/plat/debug-macro.S
View File

@ -20,7 +20,7 @@
.endm
#ifndef fifo_level
#define fifo_level fifo_level_s3c2410
#define fifo_level fifo_level_s3c2440
#endif
.macro fifo_full_s3c2440 rd, rx

9
arch/arm/plat-s3c24xx/include/plat/devs.h → arch/arm/plat-s3c/include/plat/devs.h
View File

@ -17,21 +17,26 @@ struct s3c24xx_uart_resources {
};
extern struct s3c24xx_uart_resources s3c2410_uart_resources[];
extern struct s3c24xx_uart_resources s3c64xx_uart_resources[];
extern struct platform_device *s3c24xx_uart_devs[];
extern struct platform_device *s3c24xx_uart_src[];
extern struct platform_device s3c_device_timer[];
extern struct platform_device s3c_device_fb;
extern struct platform_device s3c_device_usb;
extern struct platform_device s3c_device_lcd;
extern struct platform_device s3c_device_wdt;
extern struct platform_device s3c_device_i2c;
extern struct platform_device s3c_device_i2c0;
extern struct platform_device s3c_device_i2c1;
extern struct platform_device s3c_device_iis;
extern struct platform_device s3c_device_rtc;
extern struct platform_device s3c_device_adc;
extern struct platform_device s3c_device_sdi;
extern struct platform_device s3c_device_hsmmc;
extern struct platform_device s3c_device_hsmmc0;
extern struct platform_device s3c_device_hsmmc1;
extern struct platform_device s3c_device_hsmmc2;
extern struct platform_device s3c_device_spi0;
extern struct platform_device s3c_device_spi1;

73
arch/arm/plat-s3c/include/plat/fb.h Normal file
View File

@ -0,0 +1,73 @@
/* linux/arch/arm/plat-s3c/include/plat/fb.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S3C - FB platform data definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __PLAT_S3C_FB_H
#define __PLAT_S3C_FB_H __FILE__
/**
* struct s3c_fb_pd_win - per window setup data
* @win_mode: The display parameters to initialise (not for window 0)
* @virtual_x: The virtual X size.
* @virtual_y: The virtual Y size.
*/
struct s3c_fb_pd_win {
struct fb_videomode win_mode;
unsigned short default_bpp;
unsigned short max_bpp;
unsigned short virtual_x;
unsigned short virtual_y;
};
/**
* struct s3c_fb_platdata - S3C driver platform specific information
* @setup_gpio: Setup the external GPIO pins to the right state to transfer
* the data from the display system to the connected display
* device.
* @vidcon0: The base vidcon0 values to control the panel data format.
* @vidcon1: The base vidcon1 values to control the panel data output.
* @win: The setup data for each hardware window, or NULL for unused.
* @display_mode: The LCD output display mode.
*
* The platform data supplies the video driver with all the information
* it requires to work with the display(s) attached to the machine. It
* controls the initial mode, the number of display windows (0 is always
* the base framebuffer) that are initialised etc.
*
*/
struct s3c_fb_platdata {
void (*setup_gpio)(void);
struct s3c_fb_pd_win *win[S3C_FB_MAX_WIN];
u32 vidcon0;
u32 vidcon1;
};
/**
* s3c_fb_set_platdata() - Setup the FB device with platform data.
* @pd: The platform data to set. The data is copied from the passed structure
* so the machine data can mark the data __initdata so that any unused
* machines will end up dumping their data at runtime.
*/
extern void s3c_fb_set_platdata(struct s3c_fb_platdata *pd);
/**
* s3c64xx_fb_gpio_setup_24bpp() - S3C64XX setup function for 24bpp LCD
*
* Initialise the GPIO for an 24bpp LCD display on the RGB interface.
*/
extern void s3c64xx_fb_gpio_setup_24bpp(void);
#endif /* __PLAT_S3C_FB_H */

176
arch/arm/plat-s3c/include/plat/gpio-cfg-helpers.h Normal file
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@ -0,0 +1,176 @@
/* linux/arch/arm/plat-s3c/include/plat/gpio-cfg-helper.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S3C Platform - GPIO pin configuration helper definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/* This is meant for core cpu support, machine or other driver files
* should not be including this header.
*/
#ifndef __PLAT_GPIO_CFG_HELPERS_H
#define __PLAT_GPIO_CFG_HELPERS_H __FILE__
/* As a note, all gpio configuration functions are entered exclusively, either
* with the relevant lock held or the system prevented from doing anything else
* by disabling interrupts.
*/
static inline int s3c_gpio_do_setcfg(struct s3c_gpio_chip *chip,
unsigned int off, unsigned int config)
{
return (chip->config->set_config)(chip, off, config);
}
static inline int s3c_gpio_do_setpull(struct s3c_gpio_chip *chip,
unsigned int off, s3c_gpio_pull_t pull)
{
return (chip->config->set_pull)(chip, off, pull);
}
/**
* s3c_gpio_setcfg_s3c24xx - S3C24XX style GPIO configuration.
* @chip: The gpio chip that is being configured.
* @off: The offset for the GPIO being configured.
* @cfg: The configuration value to set.
*
* This helper deal with the GPIO cases where the control register
* has two bits of configuration per gpio, which have the following
* functions:
* 00 = input
* 01 = output
* 1x = special function
*/
extern int s3c_gpio_setcfg_s3c24xx(struct s3c_gpio_chip *chip,
unsigned int off, unsigned int cfg);
/**
* s3c_gpio_setcfg_s3c24xx_a - S3C24XX style GPIO configuration (Bank A)
* @chip: The gpio chip that is being configured.
* @off: The offset for the GPIO being configured.
* @cfg: The configuration value to set.
*
* This helper deal with the GPIO cases where the control register
* has one bit of configuration for the gpio, where setting the bit
* means the pin is in special function mode and unset means output.
*/
extern int s3c_gpio_setcfg_s3c24xx_a(struct s3c_gpio_chip *chip,
unsigned int off, unsigned int cfg);
/**
* s3c_gpio_setcfg_s3c64xx_4bit - S3C64XX 4bit single register GPIO config.
* @chip: The gpio chip that is being configured.
* @off: The offset for the GPIO being configured.
* @cfg: The configuration value to set.
*
* This helper deal with the GPIO cases where the control register has 4 bits
* of control per GPIO, generally in the form of:
* 0000 = Input
* 0001 = Output
* others = Special functions (dependant on bank)
*
* Note, since the code to deal with the case where there are two control
* registers instead of one, we do not have a seperate set of functions for
* each case.
*/
extern int s3c_gpio_setcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip,
unsigned int off, unsigned int cfg);
/* Pull-{up,down} resistor controls.
*
* S3C2410,S3C2440,S3C24A0 = Pull-UP,
* S3C2412,S3C2413 = Pull-Down
* S3C6400,S3C6410 = Pull-Both [None,Down,Up,Undef]
* S3C2443 = Pull-Both [not same as S3C6400]
*/
/**
* s3c_gpio_setpull_1up() - Pull configuration for choice of up or none.
* @chip: The gpio chip that is being configured.
* @off: The offset for the GPIO being configured.
* @param: pull: The pull mode being requested.
*
* This is a helper function for the case where we have GPIOs with one
* bit configuring the presence of a pull-up resistor.
*/
extern int s3c_gpio_setpull_1up(struct s3c_gpio_chip *chip,
unsigned int off, s3c_gpio_pull_t pull);
/**
* s3c_gpio_setpull_1down() - Pull configuration for choice of down or none
* @chip: The gpio chip that is being configured
* @off: The offset for the GPIO being configured
* @param: pull: The pull mode being requested
*
* This is a helper function for the case where we have GPIOs with one
* bit configuring the presence of a pull-down resistor.
*/
extern int s3c_gpio_setpull_1down(struct s3c_gpio_chip *chip,
unsigned int off, s3c_gpio_pull_t pull);
/**
* s3c_gpio_setpull_upown() - Pull configuration for choice of up, down or none
* @chip: The gpio chip that is being configured.
* @off: The offset for the GPIO being configured.
* @param: pull: The pull mode being requested.
*
* This is a helper function for the case where we have GPIOs with two
* bits configuring the presence of a pull resistor, in the following
* order:
* 00 = No pull resistor connected
* 01 = Pull-up resistor connected
* 10 = Pull-down resistor connected
*/
extern int s3c_gpio_setpull_updown(struct s3c_gpio_chip *chip,
unsigned int off, s3c_gpio_pull_t pull);
/**
* s3c_gpio_getpull_updown() - Get configuration for choice of up, down or none
* @chip: The gpio chip that the GPIO pin belongs to
* @off: The offset to the pin to get the configuration of.
*
* This helper function reads the state of the pull-{up,down} resistor for the
* given GPIO in the same case as s3c_gpio_setpull_upown.
*/
extern s3c_gpio_pull_t s3c_gpio_getpull_updown(struct s3c_gpio_chip *chip,
unsigned int off);
/**
* s3c_gpio_setpull_s3c2443() - Pull configuration for s3c2443.
* @chip: The gpio chip that is being configured.
* @off: The offset for the GPIO being configured.
* @param: pull: The pull mode being requested.
*
* This is a helper function for the case where we have GPIOs with two
* bits configuring the presence of a pull resistor, in the following
* order:
* 00 = Pull-up resistor connected
* 10 = Pull-down resistor connected
* x1 = No pull up resistor
*/
extern int s3c_gpio_setpull_s3c2443(struct s3c_gpio_chip *chip,
unsigned int off, s3c_gpio_pull_t pull);
/**
* s3c_gpio_getpull_s3c2443() - Get configuration for s3c2443 pull resistors
* @chip: The gpio chip that the GPIO pin belongs to.
* @off: The offset to the pin to get the configuration of.
*
* This helper function reads the state of the pull-{up,down} resistor for the
* given GPIO in the same case as s3c_gpio_setpull_upown.
*/
extern s3c_gpio_pull_t s3c_gpio_getpull_s3c24xx(struct s3c_gpio_chip *chip,
unsigned int off);
#endif /* __PLAT_GPIO_CFG_HELPERS_H */

110
arch/arm/plat-s3c/include/plat/gpio-cfg.h Normal file
View File

@ -0,0 +1,110 @@
/* linux/arch/arm/plat-s3c/include/plat/gpio-cfg.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S3C Platform - GPIO pin configuration
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/* This file contains the necessary definitions to get the basic gpio
* pin configuration done such as setting a pin to input or output or
* changing the pull-{up,down} configurations.
*/
/* Note, this interface is being added to the s3c64xx arch first and will
* be added to the s3c24xx systems later.
*/
#ifndef __PLAT_GPIO_CFG_H
#define __PLAT_GPIO_CFG_H __FILE__
typedef unsigned int __bitwise__ s3c_gpio_pull_t;
/* forward declaration if gpio-core.h hasn't been included */
struct s3c_gpio_chip;
/**
* struct s3c_gpio_cfg GPIO configuration
* @cfg_eint: Configuration setting when used for external interrupt source
* @get_pull: Read the current pull configuration for the GPIO
* @set_pull: Set the current pull configuraiton for the GPIO
* @set_config: Set the current configuration for the GPIO
* @get_config: Read the current configuration for the GPIO
*
* Each chip can have more than one type of GPIO bank available and some
* have different capabilites even when they have the same control register
* layouts. Provide an point to vector control routine and provide any
* per-bank configuration information that other systems such as the
* external interrupt code will need.
*/
struct s3c_gpio_cfg {
unsigned int cfg_eint;
s3c_gpio_pull_t (*get_pull)(struct s3c_gpio_chip *chip, unsigned offs);
int (*set_pull)(struct s3c_gpio_chip *chip, unsigned offs,
s3c_gpio_pull_t pull);
unsigned (*get_config)(struct s3c_gpio_chip *chip, unsigned offs);
int (*set_config)(struct s3c_gpio_chip *chip, unsigned offs,
unsigned config);
};
#define S3C_GPIO_SPECIAL_MARK (0xfffffff0)
#define S3C_GPIO_SPECIAL(x) (S3C_GPIO_SPECIAL_MARK | (x))
/* Defines for generic pin configurations */
#define S3C_GPIO_INPUT (S3C_GPIO_SPECIAL(0))
#define S3C_GPIO_OUTPUT (S3C_GPIO_SPECIAL(1))
#define S3C_GPIO_SFN(x) (S3C_GPIO_SPECIAL(x))
#define s3c_gpio_is_cfg_special(_cfg) \
(((_cfg) & S3C_GPIO_SPECIAL_MARK) == S3C_GPIO_SPECIAL_MARK)
/**
* s3c_gpio_cfgpin() - Change the GPIO function of a pin.
* @pin pin The pin number to configure.
* @pin to The configuration for the pin's function.
*
* Configure which function is actually connected to the external
* pin, such as an gpio input, output or some form of special function
* connected to an internal peripheral block.
*/
extern int s3c_gpio_cfgpin(unsigned int pin, unsigned int to);
/* Define values for the pull-{up,down} available for each gpio pin.
*
* These values control the state of the weak pull-{up,down} resistors
* available on most pins on the S3C series. Not all chips support both
* up or down settings, and it may be dependant on the chip that is being
* used to whether the particular mode is available.
*/
#define S3C_GPIO_PULL_NONE ((__force s3c_gpio_pull_t)0x00)
#define S3C_GPIO_PULL_DOWN ((__force s3c_gpio_pull_t)0x01)
#define S3C_GPIO_PULL_UP ((__force s3c_gpio_pull_t)0x02)
/**
* s3c_gpio_setpull() - set the state of a gpio pin pull resistor
* @pin: The pin number to configure the pull resistor.
* @pull: The configuration for the pull resistor.
*
* This function sets the state of the pull-{up,down} resistor for the
* specified pin. It will return 0 if successfull, or a negative error
* code if the pin cannot support the requested pull setting.
*/
extern int s3c_gpio_setpull(unsigned int pin, s3c_gpio_pull_t pull);
/**
* s3c_gpio_getpull() - get the pull resistor state of a gpio pin
* @pin: The pin number to get the settings for
*
* Read the pull resistor value for the specified pin.
*/
extern s3c_gpio_pull_t s3c_gpio_getpull(unsigned int pin);
#endif /* __PLAT_GPIO_CFG_H */

77
arch/arm/plat-s3c/include/plat/gpio-core.h Normal file
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@ -0,0 +1,77 @@
/* linux/arch/arm/plat-s3c/include/plat/gpio-core.h
*
* Copyright 2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S3C Platform - GPIO core
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/* Define the core gpiolib support functions that the s3c platforms may
* need to extend or change depending on the hardware and the s3c chip
* selected at build or found at run time.
*
* These definitions are not intended for driver inclusion, there is
* nothing here that should not live outside the platform and core
* specific code.
*/
struct s3c_gpio_cfg;
/**
* struct s3c_gpio_chip - wrapper for specific implementation of gpio
* @chip: The chip structure to be exported via gpiolib.
* @base: The base pointer to the gpio configuration registers.
* @config: special function and pull-resistor control information.
*
* This wrapper provides the necessary information for the Samsung
* specific gpios being registered with gpiolib.
*/
struct s3c_gpio_chip {
struct gpio_chip chip;
struct s3c_gpio_cfg *config;
void __iomem *base;
};
static inline struct s3c_gpio_chip *to_s3c_gpio(struct gpio_chip *gpc)
{
return container_of(gpc, struct s3c_gpio_chip, chip);
}
/** s3c_gpiolib_add() - add the s3c specific version of a gpio_chip.
* @chip: The chip to register
*
* This is a wrapper to gpiochip_add() that takes our specific gpio chip
* information and makes the necessary alterations for the platform and
* notes the information for use with the configuration systems and any
* other parts of the system.
*/
extern void s3c_gpiolib_add(struct s3c_gpio_chip *chip);
/* CONFIG_S3C_GPIO_TRACK enables the tracking of the s3c specific gpios
* for use with the configuration calls, and other parts of the s3c gpiolib
* support code.
*
* Not all s3c support code will need this, as some configurations of cpu
* may only support one or two different configuration options and have an
* easy gpio to s3c_gpio_chip mapping function. If this is the case, then
* the machine support file should provide its own s3c_gpiolib_getchip()
* and any other necessary functions.
*/
#ifdef CONFIG_S3C_GPIO_TRACK
extern struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END];
static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int chip)
{
return (chip < S3C_GPIO_END) ? s3c_gpios[chip] : NULL;
}
#else
/* machine specific code should provide s3c_gpiolib_getchip */
static inline void s3c_gpiolib_track(struct s3c_gpio_chip *chip) { }
#endif

35
arch/arm/plat-s3c/include/plat/iic-core.h Normal file
View File

@ -0,0 +1,35 @@
/* arch/arm/mach-s3c2410/include/mach/iic-core.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* S3C - I2C Controller core functions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_IIC_CORE_H
#define __ASM_ARCH_IIC_CORE_H __FILE__
/* These functions are only for use with the core support code, such as
* the cpu specific initialisation code
*/
/* re-define device name depending on support. */
static inline void s3c_i2c0_setname(char *name)
{
/* currently this device is always compiled in */
s3c_device_i2c0.name = name;
}
static inline void s3c_i2c1_setname(char *name)
{
#ifdef CONFIG_S3C_DEV_I2C1
s3c_device_i2c1.name = name;
#endif
}
#endif /* __ASM_ARCH_IIC_H */

24
arch/arm/plat-s3c/include/plat/iic.h
View File

@ -28,6 +28,30 @@ struct s3c2410_platform_i2c {
unsigned long max_freq; /* max frequency for the bus */
unsigned long min_freq; /* min frequency for the bus */
unsigned int sda_delay; /* pclks (s3c2440 only) */
void (*cfg_gpio)(struct platform_device *dev);
};
/**
* s3c_i2c0_set_platdata - set platform data for i2c0 device
* @i2c: The platform data to set, or NULL for default data.
*
* Register the given platform data for use with the i2c0 device. This
* call copies the platform data, so the caller can use __initdata for
* their copy.
*
* This call will set cfg_gpio if is null to the default platform
* implementation.
*
* Any user of s3c_device_i2c0 should call this, even if it is with
* NULL to ensure that the device is given the default platform data
* as the driver will no longer carry defaults.
*/
extern void s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *i2c);
extern void s3c_i2c1_set_platdata(struct s3c2410_platform_i2c *i2c);
/* defined by architecture to configure gpio */
extern void s3c_i2c0_cfg_gpio(struct platform_device *dev);
extern void s3c_i2c1_cfg_gpio(struct platform_device *dev);
#endif /* __ASM_ARCH_IIC_H */

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