Merge branch 'dmaengine' into async-tx-raid6
This commit is contained in:
commit
fd74ea6588
|
@ -298,3 +298,15 @@ over a rather long period of time, but improvements are always welcome!
|
|||
|
||||
Note that, rcu_assign_pointer() and rcu_dereference() relate to
|
||||
SRCU just as they do to other forms of RCU.
|
||||
|
||||
15. The whole point of call_rcu(), synchronize_rcu(), and friends
|
||||
is to wait until all pre-existing readers have finished before
|
||||
carrying out some otherwise-destructive operation. It is
|
||||
therefore critically important to -first- remove any path
|
||||
that readers can follow that could be affected by the
|
||||
destructive operation, and -only- -then- invoke call_rcu(),
|
||||
synchronize_rcu(), or friends.
|
||||
|
||||
Because these primitives only wait for pre-existing readers,
|
||||
it is the caller's responsibility to guarantee safety to
|
||||
any subsequent readers.
|
||||
|
|
|
@ -373,10 +373,10 @@ Filesystem Resizing http://ext2resize.sourceforge.net/
|
|||
Compression (*) http://e2compr.sourceforge.net/
|
||||
|
||||
Implementations for:
|
||||
Windows 95/98/NT/2000 http://uranus.it.swin.edu.au/~jn/linux/Explore2fs.htm
|
||||
Windows 95 (*) http://www.yipton.demon.co.uk/content.html#FSDEXT2
|
||||
Windows 95/98/NT/2000 http://www.chrysocome.net/explore2fs
|
||||
Windows 95 (*) http://www.yipton.net/content.html#FSDEXT2
|
||||
DOS client (*) ftp://metalab.unc.edu/pub/Linux/system/filesystems/ext2/
|
||||
OS/2 http://perso.wanadoo.fr/matthieu.willm/ext2-os2/
|
||||
RISC OS client ftp://ftp.barnet.ac.uk/pub/acorn/armlinux/iscafs/
|
||||
OS/2 (*) ftp://metalab.unc.edu/pub/Linux/system/filesystems/ext2/
|
||||
RISC OS client http://www.esw-heim.tu-clausthal.de/~marco/smorbrod/IscaFS/
|
||||
|
||||
(*) no longer actively developed/supported (as of Apr 2001)
|
||||
(*) no longer actively developed/supported (as of Mar 2009)
|
||||
|
|
|
@ -198,5 +198,5 @@ kernel source: <file:fs/ext3/>
|
|||
programs: http://e2fsprogs.sourceforge.net/
|
||||
http://ext2resize.sourceforge.net
|
||||
|
||||
useful links: http://www-106.ibm.com/developerworks/linux/library/l-fs7/
|
||||
http://www-106.ibm.com/developerworks/linux/library/l-fs8/
|
||||
useful links: http://www.ibm.com/developerworks/library/l-fs7.html
|
||||
http://www.ibm.com/developerworks/library/l-fs8.html
|
||||
|
|
|
@ -42,6 +42,11 @@ Supported chips:
|
|||
Addresses scanned: I2C 0x4e
|
||||
Datasheet: Publicly available at the Maxim website
|
||||
http://www.maxim-ic.com/quick_view2.cfm/qv_pk/3497
|
||||
* Maxim MAX6648
|
||||
Prefix: 'max6646'
|
||||
Addresses scanned: I2C 0x4c
|
||||
Datasheet: Publicly available at the Maxim website
|
||||
http://www.maxim-ic.com/quick_view2.cfm/qv_pk/3500
|
||||
* Maxim MAX6649
|
||||
Prefix: 'max6646'
|
||||
Addresses scanned: I2C 0x4c
|
||||
|
@ -74,6 +79,11 @@ Supported chips:
|
|||
0x4c, 0x4d and 0x4e
|
||||
Datasheet: Publicly available at the Maxim website
|
||||
http://www.maxim-ic.com/quick_view2.cfm/qv_pk/3370
|
||||
* Maxim MAX6692
|
||||
Prefix: 'max6646'
|
||||
Addresses scanned: I2C 0x4c
|
||||
Datasheet: Publicly available at the Maxim website
|
||||
http://www.maxim-ic.com/quick_view2.cfm/qv_pk/3500
|
||||
|
||||
|
||||
Author: Jean Delvare <khali@linux-fr.org>
|
||||
|
|
|
@ -1469,8 +1469,6 @@ L: linux-acpi@vger.kernel.org
|
|||
S: Supported
|
||||
|
||||
DOCUMENTATION (/Documentation directory)
|
||||
P: Michael Kerrisk
|
||||
M: mtk.manpages@gmail.com
|
||||
P: Randy Dunlap
|
||||
M: rdunlap@xenotime.net
|
||||
L: linux-doc@vger.kernel.org
|
||||
|
@ -2879,7 +2877,7 @@ P: Michael Kerrisk
|
|||
M: mtk.manpages@gmail.com
|
||||
W: http://www.kernel.org/doc/man-pages
|
||||
L: linux-man@vger.kernel.org
|
||||
S: Supported
|
||||
S: Maintained
|
||||
|
||||
MARVELL LIBERTAS WIRELESS DRIVER
|
||||
P: Dan Williams
|
||||
|
|
20
Makefile
20
Makefile
|
@ -1,7 +1,7 @@
|
|||
VERSION = 2
|
||||
PATCHLEVEL = 6
|
||||
SUBLEVEL = 29
|
||||
EXTRAVERSION = -rc7
|
||||
EXTRAVERSION = -rc8
|
||||
NAME = Erotic Pickled Herring
|
||||
|
||||
# *DOCUMENTATION*
|
||||
|
@ -904,12 +904,18 @@ localver = $(subst $(space),, $(string) \
|
|||
# and if the SCM is know a tag from the SCM is appended.
|
||||
# The appended tag is determined by the SCM used.
|
||||
#
|
||||
# Currently, only git is supported.
|
||||
# Other SCMs can edit scripts/setlocalversion and add the appropriate
|
||||
# checks as needed.
|
||||
# .scmversion is used when generating rpm packages so we do not loose
|
||||
# the version information from the SCM when we do the build of the kernel
|
||||
# from the copied source
|
||||
ifdef CONFIG_LOCALVERSION_AUTO
|
||||
_localver-auto = $(shell $(CONFIG_SHELL) \
|
||||
$(srctree)/scripts/setlocalversion $(srctree))
|
||||
|
||||
ifeq ($(wildcard .scmversion),)
|
||||
_localver-auto = $(shell $(CONFIG_SHELL) \
|
||||
$(srctree)/scripts/setlocalversion $(srctree))
|
||||
else
|
||||
_localver-auto = $(shell cat .scmversion 2> /dev/null)
|
||||
endif
|
||||
|
||||
localver-auto = $(LOCALVERSION)$(_localver-auto)
|
||||
endif
|
||||
|
||||
|
@ -1537,7 +1543,7 @@ quiet_cmd_depmod = DEPMOD $(KERNELRELEASE)
|
|||
cmd_depmod = \
|
||||
if [ -r System.map -a -x $(DEPMOD) ]; then \
|
||||
$(DEPMOD) -ae -F System.map \
|
||||
$(if $(strip $(INSTALL_MOD_PATH)), -b $(INSTALL_MOD_PATH) -r) \
|
||||
$(if $(strip $(INSTALL_MOD_PATH)), -b $(INSTALL_MOD_PATH) ) \
|
||||
$(KERNELRELEASE); \
|
||||
fi
|
||||
|
||||
|
|
|
@ -17,6 +17,7 @@
|
|||
#include <asm/coldfire.h>
|
||||
#include <asm/mcfsim.h>
|
||||
#include <asm/mcfdma.h>
|
||||
#include <asm/mcfuart.h>
|
||||
|
||||
/***************************************************************************/
|
||||
|
||||
|
|
|
@ -24,7 +24,6 @@
|
|||
#include <asm/coldfire.h>
|
||||
#include <asm/mcfsim.h>
|
||||
#include <asm/mcfuart.h>
|
||||
#include <asm/mcfqspi.h>
|
||||
|
||||
#ifdef CONFIG_MTD_PARTITIONS
|
||||
#include <linux/mtd/partitions.h>
|
||||
|
@ -33,233 +32,6 @@
|
|||
/***************************************************************************/
|
||||
|
||||
void coldfire_reset(void);
|
||||
static void coldfire_qspi_cs_control(u8 cs, u8 command);
|
||||
|
||||
/***************************************************************************/
|
||||
|
||||
#if defined(CONFIG_SPI)
|
||||
|
||||
#if defined(CONFIG_WILDFIRE)
|
||||
#define SPI_NUM_CHIPSELECTS 0x02
|
||||
#define SPI_PAR_VAL 0x07 /* Enable DIN, DOUT, CLK */
|
||||
#define SPI_CS_MASK 0x18
|
||||
|
||||
#define FLASH_BLOCKSIZE (1024*64)
|
||||
#define FLASH_NUMBLOCKS 16
|
||||
#define FLASH_TYPE "m25p80"
|
||||
|
||||
#define M25P80_CS 0
|
||||
#define MMC_CS 1
|
||||
|
||||
#ifdef CONFIG_MTD_PARTITIONS
|
||||
static struct mtd_partition stm25p_partitions[] = {
|
||||
/* sflash */
|
||||
[0] = {
|
||||
.name = "stm25p80",
|
||||
.offset = 0x00000000,
|
||||
.size = FLASH_BLOCKSIZE * FLASH_NUMBLOCKS,
|
||||
.mask_flags = 0
|
||||
}
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#elif defined(CONFIG_WILDFIREMOD)
|
||||
|
||||
#define SPI_NUM_CHIPSELECTS 0x08
|
||||
#define SPI_PAR_VAL 0x07 /* Enable DIN, DOUT, CLK */
|
||||
#define SPI_CS_MASK 0x78
|
||||
|
||||
#define FLASH_BLOCKSIZE (1024*64)
|
||||
#define FLASH_NUMBLOCKS 64
|
||||
#define FLASH_TYPE "m25p32"
|
||||
/* Reserve 1M for the kernel parition */
|
||||
#define FLASH_KERNEL_SIZE (1024 * 1024)
|
||||
|
||||
#define M25P80_CS 5
|
||||
#define MMC_CS 6
|
||||
|
||||
#ifdef CONFIG_MTD_PARTITIONS
|
||||
static struct mtd_partition stm25p_partitions[] = {
|
||||
/* sflash */
|
||||
[0] = {
|
||||
.name = "kernel",
|
||||
.offset = FLASH_BLOCKSIZE * FLASH_NUMBLOCKS - FLASH_KERNEL_SIZE,
|
||||
.size = FLASH_KERNEL_SIZE,
|
||||
.mask_flags = 0
|
||||
},
|
||||
[1] = {
|
||||
.name = "image",
|
||||
.offset = 0x00000000,
|
||||
.size = FLASH_BLOCKSIZE * FLASH_NUMBLOCKS - FLASH_KERNEL_SIZE,
|
||||
.mask_flags = 0
|
||||
},
|
||||
[2] = {
|
||||
.name = "all",
|
||||
.offset = 0x00000000,
|
||||
.size = FLASH_BLOCKSIZE * FLASH_NUMBLOCKS,
|
||||
.mask_flags = 0
|
||||
}
|
||||
};
|
||||
#endif
|
||||
|
||||
#else
|
||||
#define SPI_NUM_CHIPSELECTS 0x04
|
||||
#define SPI_PAR_VAL 0x7F /* Enable DIN, DOUT, CLK, CS0 - CS4 */
|
||||
#endif
|
||||
|
||||
#ifdef MMC_CS
|
||||
static struct coldfire_spi_chip flash_chip_info = {
|
||||
.mode = SPI_MODE_0,
|
||||
.bits_per_word = 16,
|
||||
.del_cs_to_clk = 17,
|
||||
.del_after_trans = 1,
|
||||
.void_write_data = 0
|
||||
};
|
||||
|
||||
static struct coldfire_spi_chip mmc_chip_info = {
|
||||
.mode = SPI_MODE_0,
|
||||
.bits_per_word = 16,
|
||||
.del_cs_to_clk = 17,
|
||||
.del_after_trans = 1,
|
||||
.void_write_data = 0xFFFF
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef M25P80_CS
|
||||
static struct flash_platform_data stm25p80_platform_data = {
|
||||
.name = "ST M25P80 SPI Flash chip",
|
||||
#ifdef CONFIG_MTD_PARTITIONS
|
||||
.parts = stm25p_partitions,
|
||||
.nr_parts = sizeof(stm25p_partitions) / sizeof(*stm25p_partitions),
|
||||
#endif
|
||||
.type = FLASH_TYPE
|
||||
};
|
||||
#endif
|
||||
|
||||
static struct spi_board_info spi_board_info[] __initdata = {
|
||||
#ifdef M25P80_CS
|
||||
{
|
||||
.modalias = "m25p80",
|
||||
.max_speed_hz = 16000000,
|
||||
.bus_num = 1,
|
||||
.chip_select = M25P80_CS,
|
||||
.platform_data = &stm25p80_platform_data,
|
||||
.controller_data = &flash_chip_info
|
||||
},
|
||||
#endif
|
||||
#ifdef MMC_CS
|
||||
{
|
||||
.modalias = "mmc_spi",
|
||||
.max_speed_hz = 16000000,
|
||||
.bus_num = 1,
|
||||
.chip_select = MMC_CS,
|
||||
.controller_data = &mmc_chip_info
|
||||
}
|
||||
#endif
|
||||
};
|
||||
|
||||
static struct coldfire_spi_master coldfire_master_info = {
|
||||
.bus_num = 1,
|
||||
.num_chipselect = SPI_NUM_CHIPSELECTS,
|
||||
.irq_source = MCF5282_QSPI_IRQ_SOURCE,
|
||||
.irq_vector = MCF5282_QSPI_IRQ_VECTOR,
|
||||
.irq_mask = ((0x01 << MCF5282_QSPI_IRQ_SOURCE) | 0x01),
|
||||
.irq_lp = 0x2B, /* Level 5 and Priority 3 */
|
||||
.par_val = SPI_PAR_VAL,
|
||||
.cs_control = coldfire_qspi_cs_control,
|
||||
};
|
||||
|
||||
static struct resource coldfire_spi_resources[] = {
|
||||
[0] = {
|
||||
.name = "qspi-par",
|
||||
.start = MCF5282_QSPI_PAR,
|
||||
.end = MCF5282_QSPI_PAR,
|
||||
.flags = IORESOURCE_MEM
|
||||
},
|
||||
|
||||
[1] = {
|
||||
.name = "qspi-module",
|
||||
.start = MCF5282_QSPI_QMR,
|
||||
.end = MCF5282_QSPI_QMR + 0x18,
|
||||
.flags = IORESOURCE_MEM
|
||||
},
|
||||
|
||||
[2] = {
|
||||
.name = "qspi-int-level",
|
||||
.start = MCF5282_INTC0 + MCFINTC_ICR0 + MCF5282_QSPI_IRQ_SOURCE,
|
||||
.end = MCF5282_INTC0 + MCFINTC_ICR0 + MCF5282_QSPI_IRQ_SOURCE,
|
||||
.flags = IORESOURCE_MEM
|
||||
},
|
||||
|
||||
[3] = {
|
||||
.name = "qspi-int-mask",
|
||||
.start = MCF5282_INTC0 + MCFINTC_IMRL,
|
||||
.end = MCF5282_INTC0 + MCFINTC_IMRL,
|
||||
.flags = IORESOURCE_MEM
|
||||
}
|
||||
};
|
||||
|
||||
static struct platform_device coldfire_spi = {
|
||||
.name = "spi_coldfire",
|
||||
.id = -1,
|
||||
.resource = coldfire_spi_resources,
|
||||
.num_resources = ARRAY_SIZE(coldfire_spi_resources),
|
||||
.dev = {
|
||||
.platform_data = &coldfire_master_info,
|
||||
}
|
||||
};
|
||||
|
||||
static void coldfire_qspi_cs_control(u8 cs, u8 command)
|
||||
{
|
||||
u8 cs_bit = ((0x01 << cs) << 3) & SPI_CS_MASK;
|
||||
|
||||
#if defined(CONFIG_WILDFIRE)
|
||||
u8 cs_mask = ~(((0x01 << cs) << 3) & SPI_CS_MASK);
|
||||
#endif
|
||||
#if defined(CONFIG_WILDFIREMOD)
|
||||
u8 cs_mask = (cs << 3) & SPI_CS_MASK;
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Don't do anything if the chip select is not
|
||||
* one of the port qs pins.
|
||||
*/
|
||||
if (command & QSPI_CS_INIT) {
|
||||
#if defined(CONFIG_WILDFIRE)
|
||||
MCF5282_GPIO_DDRQS |= cs_bit;
|
||||
MCF5282_GPIO_PQSPAR &= ~cs_bit;
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_WILDFIREMOD)
|
||||
MCF5282_GPIO_DDRQS |= SPI_CS_MASK;
|
||||
MCF5282_GPIO_PQSPAR &= ~SPI_CS_MASK;
|
||||
#endif
|
||||
}
|
||||
|
||||
if (command & QSPI_CS_ASSERT) {
|
||||
MCF5282_GPIO_PORTQS &= ~SPI_CS_MASK;
|
||||
MCF5282_GPIO_PORTQS |= cs_mask;
|
||||
} else if (command & QSPI_CS_DROP) {
|
||||
MCF5282_GPIO_PORTQS |= SPI_CS_MASK;
|
||||
}
|
||||
}
|
||||
|
||||
static int __init spi_dev_init(void)
|
||||
{
|
||||
int retval;
|
||||
|
||||
retval = platform_device_register(&coldfire_spi);
|
||||
if (retval < 0)
|
||||
return retval;
|
||||
|
||||
if (ARRAY_SIZE(spi_board_info))
|
||||
retval = spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_SPI */
|
||||
|
||||
/***************************************************************************/
|
||||
|
||||
|
|
|
@ -512,7 +512,7 @@ CONFIG_MD_LINEAR=m
|
|||
CONFIG_MD_RAID0=y
|
||||
CONFIG_MD_RAID1=y
|
||||
CONFIG_MD_RAID10=m
|
||||
CONFIG_MD_RAID456=m
|
||||
CONFIG_MD_RAID456=y
|
||||
CONFIG_MD_RAID5_RESHAPE=y
|
||||
CONFIG_MD_MULTIPATH=m
|
||||
CONFIG_MD_FAULTY=m
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
#
|
||||
# Automatically generated make config: don't edit
|
||||
# Linux kernel version: 2.6.26-rc9
|
||||
# Fri Jul 11 23:01:36 2008
|
||||
# Linux kernel version: 2.6.29-rc7
|
||||
# Wed Mar 4 23:07:16 2009
|
||||
#
|
||||
CONFIG_MIPS=y
|
||||
|
||||
|
@ -18,8 +18,10 @@ CONFIG_MIPS=y
|
|||
# CONFIG_LEMOTE_FULONG is not set
|
||||
# CONFIG_MIPS_MALTA is not set
|
||||
# CONFIG_MIPS_SIM is not set
|
||||
# CONFIG_MARKEINS is not set
|
||||
# CONFIG_MACH_EMMA is not set
|
||||
# CONFIG_MACH_VR41XX is not set
|
||||
# CONFIG_NXP_STB220 is not set
|
||||
# CONFIG_NXP_STB225 is not set
|
||||
# CONFIG_PNX8550_JBS is not set
|
||||
# CONFIG_PNX8550_STB810 is not set
|
||||
# CONFIG_PMC_MSP is not set
|
||||
|
@ -39,7 +41,11 @@ CONFIG_MIPS=y
|
|||
# CONFIG_SNI_RM is not set
|
||||
CONFIG_MACH_TX39XX=y
|
||||
# CONFIG_MACH_TX49XX is not set
|
||||
# CONFIG_MIKROTIK_RB532 is not set
|
||||
# CONFIG_WR_PPMC is not set
|
||||
# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set
|
||||
# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set
|
||||
CONFIG_MACH_TXX9=y
|
||||
CONFIG_TOSHIBA_JMR3927=y
|
||||
CONFIG_SOC_TX3927=y
|
||||
# CONFIG_TOSHIBA_FPCIB0 is not set
|
||||
|
@ -54,12 +60,14 @@ CONFIG_GENERIC_CALIBRATE_DELAY=y
|
|||
CONFIG_GENERIC_CLOCKEVENTS=y
|
||||
CONFIG_GENERIC_TIME=y
|
||||
CONFIG_GENERIC_CMOS_UPDATE=y
|
||||
CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
|
||||
CONFIG_SCHED_OMIT_FRAME_POINTER=y
|
||||
CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
|
||||
CONFIG_CEVT_TXX9=y
|
||||
CONFIG_GPIO_TXX9=y
|
||||
CONFIG_DMA_NONCOHERENT=y
|
||||
CONFIG_DMA_NEED_PCI_MAP_STATE=y
|
||||
CONFIG_EARLY_PRINTK=y
|
||||
CONFIG_SYS_HAS_EARLY_PRINTK=y
|
||||
# CONFIG_HOTPLUG_CPU is not set
|
||||
# CONFIG_NO_IOPORT is not set
|
||||
CONFIG_GENERIC_GPIO=y
|
||||
|
@ -87,6 +95,7 @@ CONFIG_CPU_TX39XX=y
|
|||
# CONFIG_CPU_TX49XX is not set
|
||||
# CONFIG_CPU_R5000 is not set
|
||||
# CONFIG_CPU_R5432 is not set
|
||||
# CONFIG_CPU_R5500 is not set
|
||||
# CONFIG_CPU_R6000 is not set
|
||||
# CONFIG_CPU_NEVADA is not set
|
||||
# CONFIG_CPU_R8000 is not set
|
||||
|
@ -94,6 +103,7 @@ CONFIG_CPU_TX39XX=y
|
|||
# CONFIG_CPU_RM7000 is not set
|
||||
# CONFIG_CPU_RM9000 is not set
|
||||
# CONFIG_CPU_SB1 is not set
|
||||
# CONFIG_CPU_CAVIUM_OCTEON is not set
|
||||
CONFIG_SYS_HAS_CPU_TX39XX=y
|
||||
CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
|
||||
CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
|
||||
|
@ -117,14 +127,12 @@ CONFIG_ARCH_FLATMEM_ENABLE=y
|
|||
CONFIG_ARCH_POPULATES_NODE_MAP=y
|
||||
CONFIG_FLATMEM=y
|
||||
CONFIG_FLAT_NODE_MEM_MAP=y
|
||||
# CONFIG_SPARSEMEM_STATIC is not set
|
||||
# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
|
||||
CONFIG_PAGEFLAGS_EXTENDED=y
|
||||
CONFIG_SPLIT_PTLOCK_CPUS=4
|
||||
# CONFIG_RESOURCES_64BIT is not set
|
||||
# CONFIG_PHYS_ADDR_T_64BIT is not set
|
||||
CONFIG_ZONE_DMA_FLAG=0
|
||||
CONFIG_VIRT_TO_BUS=y
|
||||
# CONFIG_TICK_ONESHOT is not set
|
||||
CONFIG_UNEVICTABLE_LRU=y
|
||||
# CONFIG_NO_HZ is not set
|
||||
# CONFIG_HIGH_RES_TIMERS is not set
|
||||
CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
|
||||
|
@ -159,6 +167,15 @@ CONFIG_SYSVIPC_SYSCTL=y
|
|||
# CONFIG_BSD_PROCESS_ACCT is not set
|
||||
# CONFIG_TASKSTATS is not set
|
||||
# CONFIG_AUDIT is not set
|
||||
|
||||
#
|
||||
# RCU Subsystem
|
||||
#
|
||||
CONFIG_CLASSIC_RCU=y
|
||||
# CONFIG_TREE_RCU is not set
|
||||
# CONFIG_PREEMPT_RCU is not set
|
||||
# CONFIG_TREE_RCU_TRACE is not set
|
||||
# CONFIG_PREEMPT_RCU_TRACE is not set
|
||||
# CONFIG_IKCONFIG is not set
|
||||
CONFIG_LOG_BUF_SHIFT=14
|
||||
# CONFIG_CGROUPS is not set
|
||||
|
@ -171,7 +188,6 @@ CONFIG_CC_OPTIMIZE_FOR_SIZE=y
|
|||
CONFIG_SYSCTL=y
|
||||
CONFIG_EMBEDDED=y
|
||||
CONFIG_SYSCTL_SYSCALL=y
|
||||
CONFIG_SYSCTL_SYSCALL_CHECK=y
|
||||
CONFIG_KALLSYMS=y
|
||||
# CONFIG_KALLSYMS_EXTRA_PASS is not set
|
||||
# CONFIG_HOTPLUG is not set
|
||||
|
@ -188,26 +204,23 @@ CONFIG_SIGNALFD=y
|
|||
CONFIG_TIMERFD=y
|
||||
CONFIG_EVENTFD=y
|
||||
CONFIG_SHMEM=y
|
||||
CONFIG_AIO=y
|
||||
CONFIG_VM_EVENT_COUNTERS=y
|
||||
CONFIG_PCI_QUIRKS=y
|
||||
CONFIG_SLAB=y
|
||||
# CONFIG_SLUB is not set
|
||||
# CONFIG_SLOB is not set
|
||||
# CONFIG_PROFILING is not set
|
||||
# CONFIG_MARKERS is not set
|
||||
CONFIG_HAVE_OPROFILE=y
|
||||
# CONFIG_HAVE_KPROBES is not set
|
||||
# CONFIG_HAVE_KRETPROBES is not set
|
||||
# CONFIG_HAVE_DMA_ATTRS is not set
|
||||
CONFIG_PROC_PAGE_MONITOR=y
|
||||
# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
|
||||
CONFIG_SLABINFO=y
|
||||
CONFIG_RT_MUTEXES=y
|
||||
# CONFIG_TINY_SHMEM is not set
|
||||
CONFIG_BASE_SMALL=0
|
||||
# CONFIG_MODULES is not set
|
||||
CONFIG_BLOCK=y
|
||||
# CONFIG_LBD is not set
|
||||
# CONFIG_BLK_DEV_IO_TRACE is not set
|
||||
# CONFIG_LSF is not set
|
||||
# CONFIG_BLK_DEV_INTEGRITY is not set
|
||||
|
||||
#
|
||||
# IO Schedulers
|
||||
|
@ -221,7 +234,7 @@ CONFIG_IOSCHED_CFQ=y
|
|||
CONFIG_DEFAULT_CFQ=y
|
||||
# CONFIG_DEFAULT_NOOP is not set
|
||||
CONFIG_DEFAULT_IOSCHED="cfq"
|
||||
CONFIG_CLASSIC_RCU=y
|
||||
# CONFIG_FREEZER is not set
|
||||
|
||||
#
|
||||
# Bus options (PCI, PCMCIA, EISA, ISA, TC)
|
||||
|
@ -231,12 +244,15 @@ CONFIG_PCI=y
|
|||
CONFIG_PCI_DOMAINS=y
|
||||
# CONFIG_ARCH_SUPPORTS_MSI is not set
|
||||
CONFIG_PCI_LEGACY=y
|
||||
# CONFIG_PCI_STUB is not set
|
||||
CONFIG_MMU=y
|
||||
|
||||
#
|
||||
# Executable file formats
|
||||
#
|
||||
CONFIG_BINFMT_ELF=y
|
||||
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
|
||||
# CONFIG_HAVE_AOUT is not set
|
||||
# CONFIG_BINFMT_MISC is not set
|
||||
CONFIG_TRAD_SIGNALS=y
|
||||
|
||||
|
@ -245,15 +261,12 @@ CONFIG_TRAD_SIGNALS=y
|
|||
#
|
||||
CONFIG_ARCH_SUSPEND_POSSIBLE=y
|
||||
# CONFIG_PM is not set
|
||||
|
||||
#
|
||||
# Networking
|
||||
#
|
||||
CONFIG_NET=y
|
||||
|
||||
#
|
||||
# Networking options
|
||||
#
|
||||
CONFIG_COMPAT_NET_DEV_OPS=y
|
||||
CONFIG_PACKET=y
|
||||
# CONFIG_PACKET_MMAP is not set
|
||||
CONFIG_UNIX=y
|
||||
|
@ -293,6 +306,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
|
|||
# CONFIG_IPX is not set
|
||||
# CONFIG_ATALK is not set
|
||||
# CONFIG_NET_SCHED is not set
|
||||
# CONFIG_DCB is not set
|
||||
|
||||
#
|
||||
# Network testing
|
||||
|
@ -302,14 +316,9 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
|
|||
# CONFIG_CAN is not set
|
||||
# CONFIG_IRDA is not set
|
||||
# CONFIG_BT is not set
|
||||
|
||||
#
|
||||
# Wireless
|
||||
#
|
||||
# CONFIG_CFG80211 is not set
|
||||
# CONFIG_WIRELESS_EXT is not set
|
||||
# CONFIG_MAC80211 is not set
|
||||
# CONFIG_IEEE80211 is not set
|
||||
# CONFIG_PHONET is not set
|
||||
# CONFIG_WIRELESS is not set
|
||||
# CONFIG_WIMAX is not set
|
||||
# CONFIG_RFKILL is not set
|
||||
|
||||
#
|
||||
|
@ -323,7 +332,89 @@ CONFIG_STANDALONE=y
|
|||
CONFIG_PREVENT_FIRMWARE_BUILD=y
|
||||
# CONFIG_SYS_HYPERVISOR is not set
|
||||
# CONFIG_CONNECTOR is not set
|
||||
# CONFIG_MTD is not set
|
||||
CONFIG_MTD=y
|
||||
# CONFIG_MTD_DEBUG is not set
|
||||
# CONFIG_MTD_CONCAT is not set
|
||||
CONFIG_MTD_PARTITIONS=y
|
||||
# CONFIG_MTD_REDBOOT_PARTS is not set
|
||||
CONFIG_MTD_CMDLINE_PARTS=y
|
||||
# CONFIG_MTD_AR7_PARTS is not set
|
||||
|
||||
#
|
||||
# User Modules And Translation Layers
|
||||
#
|
||||
CONFIG_MTD_CHAR=y
|
||||
# CONFIG_MTD_BLKDEVS is not set
|
||||
# CONFIG_MTD_BLOCK is not set
|
||||
# CONFIG_MTD_BLOCK_RO is not set
|
||||
# CONFIG_FTL is not set
|
||||
# CONFIG_NFTL is not set
|
||||
# CONFIG_INFTL is not set
|
||||
# CONFIG_RFD_FTL is not set
|
||||
# CONFIG_SSFDC is not set
|
||||
# CONFIG_MTD_OOPS is not set
|
||||
|
||||
#
|
||||
# RAM/ROM/Flash chip drivers
|
||||
#
|
||||
CONFIG_MTD_CFI=y
|
||||
CONFIG_MTD_JEDECPROBE=y
|
||||
CONFIG_MTD_GEN_PROBE=y
|
||||
# CONFIG_MTD_CFI_ADV_OPTIONS is not set
|
||||
CONFIG_MTD_MAP_BANK_WIDTH_1=y
|
||||
CONFIG_MTD_MAP_BANK_WIDTH_2=y
|
||||
CONFIG_MTD_MAP_BANK_WIDTH_4=y
|
||||
# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
|
||||
# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
|
||||
# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
|
||||
CONFIG_MTD_CFI_I1=y
|
||||
CONFIG_MTD_CFI_I2=y
|
||||
# CONFIG_MTD_CFI_I4 is not set
|
||||
# CONFIG_MTD_CFI_I8 is not set
|
||||
# CONFIG_MTD_CFI_INTELEXT is not set
|
||||
CONFIG_MTD_CFI_AMDSTD=y
|
||||
# CONFIG_MTD_CFI_STAA is not set
|
||||
CONFIG_MTD_CFI_UTIL=y
|
||||
# CONFIG_MTD_RAM is not set
|
||||
# CONFIG_MTD_ROM is not set
|
||||
# CONFIG_MTD_ABSENT is not set
|
||||
|
||||
#
|
||||
# Mapping drivers for chip access
|
||||
#
|
||||
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
|
||||
CONFIG_MTD_PHYSMAP=y
|
||||
# CONFIG_MTD_PHYSMAP_COMPAT is not set
|
||||
# CONFIG_MTD_INTEL_VR_NOR is not set
|
||||
# CONFIG_MTD_PLATRAM is not set
|
||||
|
||||
#
|
||||
# Self-contained MTD device drivers
|
||||
#
|
||||
# CONFIG_MTD_PMC551 is not set
|
||||
# CONFIG_MTD_SLRAM is not set
|
||||
# CONFIG_MTD_PHRAM is not set
|
||||
# CONFIG_MTD_MTDRAM is not set
|
||||
# CONFIG_MTD_BLOCK2MTD is not set
|
||||
|
||||
#
|
||||
# Disk-On-Chip Device Drivers
|
||||
#
|
||||
# CONFIG_MTD_DOC2000 is not set
|
||||
# CONFIG_MTD_DOC2001 is not set
|
||||
# CONFIG_MTD_DOC2001PLUS is not set
|
||||
# CONFIG_MTD_NAND is not set
|
||||
# CONFIG_MTD_ONENAND is not set
|
||||
|
||||
#
|
||||
# LPDDR flash memory drivers
|
||||
#
|
||||
# CONFIG_MTD_LPDDR is not set
|
||||
|
||||
#
|
||||
# UBI - Unsorted block images
|
||||
#
|
||||
# CONFIG_MTD_UBI is not set
|
||||
# CONFIG_PARPORT is not set
|
||||
CONFIG_BLK_DEV=y
|
||||
# CONFIG_BLK_CPQ_DA is not set
|
||||
|
@ -336,6 +427,7 @@ CONFIG_BLK_DEV=y
|
|||
# CONFIG_BLK_DEV_RAM is not set
|
||||
# CONFIG_CDROM_PKTCDVD is not set
|
||||
# CONFIG_ATA_OVER_ETH is not set
|
||||
# CONFIG_BLK_DEV_HD is not set
|
||||
# CONFIG_MISC_DEVICES is not set
|
||||
CONFIG_HAVE_IDE=y
|
||||
# CONFIG_IDE is not set
|
||||
|
@ -361,7 +453,6 @@ CONFIG_HAVE_IDE=y
|
|||
# CONFIG_IEEE1394 is not set
|
||||
# CONFIG_I2O is not set
|
||||
CONFIG_NETDEVICES=y
|
||||
# CONFIG_NETDEVICES_MULTIQUEUE is not set
|
||||
# CONFIG_DUMMY is not set
|
||||
# CONFIG_BONDING is not set
|
||||
# CONFIG_EQUALIZER is not set
|
||||
|
@ -383,6 +474,9 @@ CONFIG_PHYLIB=y
|
|||
# CONFIG_BROADCOM_PHY is not set
|
||||
# CONFIG_ICPLUS_PHY is not set
|
||||
# CONFIG_REALTEK_PHY is not set
|
||||
# CONFIG_NATIONAL_PHY is not set
|
||||
# CONFIG_STE10XP is not set
|
||||
# CONFIG_LSI_ET1011C_PHY is not set
|
||||
# CONFIG_FIXED_PHY is not set
|
||||
# CONFIG_MDIO_BITBANG is not set
|
||||
CONFIG_NET_ETHERNET=y
|
||||
|
@ -392,6 +486,7 @@ CONFIG_NET_ETHERNET=y
|
|||
# CONFIG_SUNGEM is not set
|
||||
# CONFIG_CASSINI is not set
|
||||
# CONFIG_NET_VENDOR_3COM is not set
|
||||
# CONFIG_SMC91X is not set
|
||||
# CONFIG_DM9000 is not set
|
||||
# CONFIG_NET_TULIP is not set
|
||||
# CONFIG_HP100 is not set
|
||||
|
@ -399,6 +494,9 @@ CONFIG_NET_ETHERNET=y
|
|||
# CONFIG_IBM_NEW_EMAC_RGMII is not set
|
||||
# CONFIG_IBM_NEW_EMAC_TAH is not set
|
||||
# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
|
||||
# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
|
||||
# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
|
||||
# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
|
||||
CONFIG_NET_PCI=y
|
||||
# CONFIG_PCNET32 is not set
|
||||
# CONFIG_AMD8111_ETH is not set
|
||||
|
@ -406,7 +504,6 @@ CONFIG_NET_PCI=y
|
|||
# CONFIG_B44 is not set
|
||||
# CONFIG_FORCEDETH is not set
|
||||
CONFIG_TC35815=y
|
||||
# CONFIG_EEPRO100 is not set
|
||||
# CONFIG_E100 is not set
|
||||
# CONFIG_FEALNX is not set
|
||||
# CONFIG_NATSEMI is not set
|
||||
|
@ -415,9 +512,11 @@ CONFIG_TC35815=y
|
|||
# CONFIG_R6040 is not set
|
||||
# CONFIG_SIS900 is not set
|
||||
# CONFIG_EPIC100 is not set
|
||||
# CONFIG_SMSC9420 is not set
|
||||
# CONFIG_SUNDANCE is not set
|
||||
# CONFIG_TLAN is not set
|
||||
# CONFIG_VIA_RHINE is not set
|
||||
# CONFIG_ATL2 is not set
|
||||
# CONFIG_NETDEV_1000 is not set
|
||||
# CONFIG_NETDEV_10000 is not set
|
||||
# CONFIG_TR is not set
|
||||
|
@ -428,6 +527,10 @@ CONFIG_TC35815=y
|
|||
# CONFIG_WLAN_PRE80211 is not set
|
||||
# CONFIG_WLAN_80211 is not set
|
||||
# CONFIG_IWLWIFI_LEDS is not set
|
||||
|
||||
#
|
||||
# Enable WiMAX (Networking options) to see the WiMAX drivers
|
||||
#
|
||||
# CONFIG_WAN is not set
|
||||
# CONFIG_FDDI is not set
|
||||
# CONFIG_PPP is not set
|
||||
|
@ -440,27 +543,7 @@ CONFIG_TC35815=y
|
|||
#
|
||||
# Input device support
|
||||
#
|
||||
CONFIG_INPUT=y
|
||||
# CONFIG_INPUT_FF_MEMLESS is not set
|
||||
# CONFIG_INPUT_POLLDEV is not set
|
||||
|
||||
#
|
||||
# Userland interfaces
|
||||
#
|
||||
# CONFIG_INPUT_MOUSEDEV is not set
|
||||
# CONFIG_INPUT_JOYDEV is not set
|
||||
# CONFIG_INPUT_EVDEV is not set
|
||||
# CONFIG_INPUT_EVBUG is not set
|
||||
|
||||
#
|
||||
# Input Device Drivers
|
||||
#
|
||||
# CONFIG_INPUT_KEYBOARD is not set
|
||||
# CONFIG_INPUT_MOUSE is not set
|
||||
# CONFIG_INPUT_JOYSTICK is not set
|
||||
# CONFIG_INPUT_TABLET is not set
|
||||
# CONFIG_INPUT_TOUCHSCREEN is not set
|
||||
# CONFIG_INPUT_MISC is not set
|
||||
# CONFIG_INPUT is not set
|
||||
|
||||
#
|
||||
# Hardware I/O ports
|
||||
|
@ -517,16 +600,22 @@ CONFIG_LEGACY_PTY_COUNT=256
|
|||
CONFIG_DEVPORT=y
|
||||
# CONFIG_I2C is not set
|
||||
# CONFIG_SPI is not set
|
||||
CONFIG_HAVE_GPIO_LIB=y
|
||||
CONFIG_ARCH_REQUIRE_GPIOLIB=y
|
||||
CONFIG_GPIOLIB=y
|
||||
|
||||
#
|
||||
# GPIO Support
|
||||
# Memory mapped GPIO expanders:
|
||||
#
|
||||
|
||||
#
|
||||
# I2C GPIO expanders:
|
||||
#
|
||||
|
||||
#
|
||||
# PCI GPIO expanders:
|
||||
#
|
||||
# CONFIG_GPIO_BT8XX is not set
|
||||
|
||||
#
|
||||
# SPI GPIO expanders:
|
||||
#
|
||||
|
@ -542,6 +631,7 @@ CONFIG_WATCHDOG=y
|
|||
# Watchdog Device Drivers
|
||||
#
|
||||
# CONFIG_SOFT_WATCHDOG is not set
|
||||
# CONFIG_ALIM7101_WDT is not set
|
||||
CONFIG_TXX9_WDT=y
|
||||
|
||||
#
|
||||
|
@ -549,18 +639,21 @@ CONFIG_TXX9_WDT=y
|
|||
#
|
||||
# CONFIG_PCIPCWATCHDOG is not set
|
||||
# CONFIG_WDTPCI is not set
|
||||
CONFIG_SSB_POSSIBLE=y
|
||||
|
||||
#
|
||||
# Sonics Silicon Backplane
|
||||
#
|
||||
CONFIG_SSB_POSSIBLE=y
|
||||
# CONFIG_SSB is not set
|
||||
|
||||
#
|
||||
# Multifunction device drivers
|
||||
#
|
||||
# CONFIG_MFD_CORE is not set
|
||||
# CONFIG_MFD_SM501 is not set
|
||||
# CONFIG_HTC_PASIC3 is not set
|
||||
# CONFIG_MFD_TMIO is not set
|
||||
# CONFIG_REGULATOR is not set
|
||||
|
||||
#
|
||||
# Multimedia devices
|
||||
|
@ -591,16 +684,26 @@ CONFIG_SSB_POSSIBLE=y
|
|||
# Display device support
|
||||
#
|
||||
# CONFIG_DISPLAY_SUPPORT is not set
|
||||
|
||||
#
|
||||
# Sound
|
||||
#
|
||||
# CONFIG_SOUND is not set
|
||||
# CONFIG_HID_SUPPORT is not set
|
||||
# CONFIG_USB_SUPPORT is not set
|
||||
# CONFIG_MMC is not set
|
||||
# CONFIG_MEMSTICK is not set
|
||||
# CONFIG_NEW_LEDS is not set
|
||||
CONFIG_NEW_LEDS=y
|
||||
CONFIG_LEDS_CLASS=y
|
||||
|
||||
#
|
||||
# LED drivers
|
||||
#
|
||||
CONFIG_LEDS_GPIO=y
|
||||
|
||||
#
|
||||
# LED Triggers
|
||||
#
|
||||
CONFIG_LEDS_TRIGGERS=y
|
||||
# CONFIG_LEDS_TRIGGER_TIMER is not set
|
||||
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
|
||||
# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
|
||||
# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
|
||||
# CONFIG_ACCESSIBILITY is not set
|
||||
# CONFIG_INFINIBAND is not set
|
||||
CONFIG_RTC_LIB=y
|
||||
|
@ -626,27 +729,34 @@ CONFIG_RTC_INTF_DEV=y
|
|||
# Platform RTC drivers
|
||||
#
|
||||
# CONFIG_RTC_DRV_CMOS is not set
|
||||
# CONFIG_RTC_DRV_DS1286 is not set
|
||||
# CONFIG_RTC_DRV_DS1511 is not set
|
||||
# CONFIG_RTC_DRV_DS1553 is not set
|
||||
CONFIG_RTC_DRV_DS1742=y
|
||||
# CONFIG_RTC_DRV_STK17TA8 is not set
|
||||
# CONFIG_RTC_DRV_M48T86 is not set
|
||||
# CONFIG_RTC_DRV_M48T35 is not set
|
||||
# CONFIG_RTC_DRV_M48T59 is not set
|
||||
# CONFIG_RTC_DRV_BQ4802 is not set
|
||||
# CONFIG_RTC_DRV_V3020 is not set
|
||||
|
||||
#
|
||||
# on-CPU RTC drivers
|
||||
#
|
||||
# CONFIG_DMADEVICES is not set
|
||||
# CONFIG_UIO is not set
|
||||
# CONFIG_STAGING is not set
|
||||
|
||||
#
|
||||
# File systems
|
||||
#
|
||||
# CONFIG_EXT2_FS is not set
|
||||
# CONFIG_EXT3_FS is not set
|
||||
# CONFIG_EXT4_FS is not set
|
||||
# CONFIG_REISERFS_FS is not set
|
||||
# CONFIG_JFS_FS is not set
|
||||
# CONFIG_FS_POSIX_ACL is not set
|
||||
CONFIG_FILE_LOCKING=y
|
||||
# CONFIG_XFS_FS is not set
|
||||
# CONFIG_OCFS2_FS is not set
|
||||
CONFIG_DNOTIFY=y
|
||||
|
@ -676,28 +786,17 @@ CONFIG_INOTIFY_USER=y
|
|||
CONFIG_PROC_FS=y
|
||||
CONFIG_PROC_KCORE=y
|
||||
CONFIG_PROC_SYSCTL=y
|
||||
CONFIG_PROC_PAGE_MONITOR=y
|
||||
CONFIG_SYSFS=y
|
||||
# CONFIG_TMPFS is not set
|
||||
# CONFIG_HUGETLB_PAGE is not set
|
||||
# CONFIG_CONFIGFS_FS is not set
|
||||
|
||||
#
|
||||
# Miscellaneous filesystems
|
||||
#
|
||||
# CONFIG_HFSPLUS_FS is not set
|
||||
# CONFIG_CRAMFS is not set
|
||||
# CONFIG_VXFS_FS is not set
|
||||
# CONFIG_MINIX_FS is not set
|
||||
# CONFIG_HPFS_FS is not set
|
||||
# CONFIG_QNX4FS_FS is not set
|
||||
# CONFIG_ROMFS_FS is not set
|
||||
# CONFIG_SYSV_FS is not set
|
||||
# CONFIG_UFS_FS is not set
|
||||
# CONFIG_MISC_FILESYSTEMS is not set
|
||||
CONFIG_NETWORK_FILESYSTEMS=y
|
||||
CONFIG_NFS_FS=y
|
||||
# CONFIG_NFS_V3 is not set
|
||||
# CONFIG_NFSD is not set
|
||||
CONFIG_ROOT_NFS=y
|
||||
# CONFIG_NFSD is not set
|
||||
CONFIG_LOCKD=y
|
||||
CONFIG_NFS_COMMON=y
|
||||
CONFIG_SUNRPC=y
|
||||
|
@ -726,7 +825,16 @@ CONFIG_FRAME_WARN=1024
|
|||
# CONFIG_DEBUG_FS is not set
|
||||
# CONFIG_HEADERS_CHECK is not set
|
||||
# CONFIG_DEBUG_KERNEL is not set
|
||||
# CONFIG_DEBUG_MEMORY_INIT is not set
|
||||
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
|
||||
CONFIG_SYSCTL_SYSCALL_CHECK=y
|
||||
|
||||
#
|
||||
# Tracers
|
||||
#
|
||||
# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
|
||||
# CONFIG_SAMPLES is not set
|
||||
CONFIG_HAVE_ARCH_KGDB=y
|
||||
CONFIG_CMDLINE=""
|
||||
|
||||
#
|
||||
|
@ -734,15 +842,18 @@ CONFIG_CMDLINE=""
|
|||
#
|
||||
# CONFIG_KEYS is not set
|
||||
# CONFIG_SECURITY is not set
|
||||
# CONFIG_SECURITYFS is not set
|
||||
# CONFIG_SECURITY_FILE_CAPABILITIES is not set
|
||||
# CONFIG_CRYPTO is not set
|
||||
|
||||
#
|
||||
# Library routines
|
||||
#
|
||||
CONFIG_BITREVERSE=y
|
||||
# CONFIG_GENERIC_FIND_FIRST_BIT is not set
|
||||
CONFIG_GENERIC_FIND_LAST_BIT=y
|
||||
# CONFIG_CRC_CCITT is not set
|
||||
# CONFIG_CRC16 is not set
|
||||
# CONFIG_CRC_T10DIF is not set
|
||||
# CONFIG_CRC_ITU_T is not set
|
||||
CONFIG_CRC32=y
|
||||
# CONFIG_CRC7 is not set
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
#
|
||||
# Automatically generated make config: don't edit
|
||||
# Linux kernel version: 2.6.26-rc9
|
||||
# Fri Jul 11 23:03:21 2008
|
||||
# Linux kernel version: 2.6.29-rc7
|
||||
# Wed Mar 4 23:08:06 2009
|
||||
#
|
||||
CONFIG_MIPS=y
|
||||
|
||||
|
@ -18,8 +18,10 @@ CONFIG_MIPS=y
|
|||
# CONFIG_LEMOTE_FULONG is not set
|
||||
# CONFIG_MIPS_MALTA is not set
|
||||
# CONFIG_MIPS_SIM is not set
|
||||
# CONFIG_MARKEINS is not set
|
||||
# CONFIG_MACH_EMMA is not set
|
||||
# CONFIG_MACH_VR41XX is not set
|
||||
# CONFIG_NXP_STB220 is not set
|
||||
# CONFIG_NXP_STB225 is not set
|
||||
# CONFIG_PNX8550_JBS is not set
|
||||
# CONFIG_PNX8550_STB810 is not set
|
||||
# CONFIG_PMC_MSP is not set
|
||||
|
@ -39,20 +41,28 @@ CONFIG_MIPS=y
|
|||
# CONFIG_SNI_RM is not set
|
||||
# CONFIG_MACH_TX39XX is not set
|
||||
CONFIG_MACH_TX49XX=y
|
||||
# CONFIG_MIKROTIK_RB532 is not set
|
||||
# CONFIG_WR_PPMC is not set
|
||||
# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set
|
||||
# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set
|
||||
CONFIG_MACH_TXX9=y
|
||||
CONFIG_TOSHIBA_RBTX4927=y
|
||||
CONFIG_TOSHIBA_RBTX4938=y
|
||||
CONFIG_TOSHIBA_RBTX4939=y
|
||||
CONFIG_SOC_TX4927=y
|
||||
CONFIG_SOC_TX4938=y
|
||||
CONFIG_SOC_TX4939=y
|
||||
CONFIG_TXX9_7SEGLED=y
|
||||
# CONFIG_TOSHIBA_FPCIB0 is not set
|
||||
CONFIG_PICMG_PCI_BACKPLANE_DEFAULT=y
|
||||
|
||||
#
|
||||
# Multiplex Pin Select
|
||||
#
|
||||
CONFIG_TOSHIBA_RBTX4938_MPLEX_PIO58_61=y
|
||||
# CONFIG_TOSHIBA_RBTX4938_MPLEX_PIO58_61 is not set
|
||||
# CONFIG_TOSHIBA_RBTX4938_MPLEX_NAND is not set
|
||||
# CONFIG_TOSHIBA_RBTX4938_MPLEX_ATA is not set
|
||||
CONFIG_TOSHIBA_RBTX4938_MPLEX_KEEP=y
|
||||
CONFIG_PCI_TX4927=y
|
||||
CONFIG_RWSEM_GENERIC_SPINLOCK=y
|
||||
# CONFIG_ARCH_HAS_ILOG2_U32 is not set
|
||||
|
@ -64,14 +74,18 @@ CONFIG_GENERIC_CALIBRATE_DELAY=y
|
|||
CONFIG_GENERIC_CLOCKEVENTS=y
|
||||
CONFIG_GENERIC_TIME=y
|
||||
CONFIG_GENERIC_CMOS_UPDATE=y
|
||||
CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
|
||||
CONFIG_SCHED_OMIT_FRAME_POINTER=y
|
||||
CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
|
||||
CONFIG_CEVT_R4K_LIB=y
|
||||
CONFIG_CEVT_R4K=y
|
||||
CONFIG_CEVT_TXX9=y
|
||||
CONFIG_CSRC_R4K_LIB=y
|
||||
CONFIG_CSRC_R4K=y
|
||||
CONFIG_GPIO_TXX9=y
|
||||
CONFIG_DMA_NONCOHERENT=y
|
||||
CONFIG_DMA_NEED_PCI_MAP_STATE=y
|
||||
CONFIG_EARLY_PRINTK=y
|
||||
CONFIG_SYS_HAS_EARLY_PRINTK=y
|
||||
# CONFIG_HOTPLUG_CPU is not set
|
||||
# CONFIG_NO_IOPORT is not set
|
||||
CONFIG_GENERIC_GPIO=y
|
||||
|
@ -100,6 +114,7 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
|
|||
CONFIG_CPU_TX49XX=y
|
||||
# CONFIG_CPU_R5000 is not set
|
||||
# CONFIG_CPU_R5432 is not set
|
||||
# CONFIG_CPU_R5500 is not set
|
||||
# CONFIG_CPU_R6000 is not set
|
||||
# CONFIG_CPU_NEVADA is not set
|
||||
# CONFIG_CPU_R8000 is not set
|
||||
|
@ -107,6 +122,7 @@ CONFIG_CPU_TX49XX=y
|
|||
# CONFIG_CPU_RM7000 is not set
|
||||
# CONFIG_CPU_RM9000 is not set
|
||||
# CONFIG_CPU_SB1 is not set
|
||||
# CONFIG_CPU_CAVIUM_OCTEON is not set
|
||||
CONFIG_SYS_HAS_CPU_TX49XX=y
|
||||
CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
|
||||
CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
|
||||
|
@ -134,13 +150,12 @@ CONFIG_ARCH_FLATMEM_ENABLE=y
|
|||
CONFIG_ARCH_POPULATES_NODE_MAP=y
|
||||
CONFIG_FLATMEM=y
|
||||
CONFIG_FLAT_NODE_MEM_MAP=y
|
||||
# CONFIG_SPARSEMEM_STATIC is not set
|
||||
# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
|
||||
CONFIG_PAGEFLAGS_EXTENDED=y
|
||||
CONFIG_SPLIT_PTLOCK_CPUS=4
|
||||
# CONFIG_RESOURCES_64BIT is not set
|
||||
# CONFIG_PHYS_ADDR_T_64BIT is not set
|
||||
CONFIG_ZONE_DMA_FLAG=0
|
||||
CONFIG_VIRT_TO_BUS=y
|
||||
CONFIG_UNEVICTABLE_LRU=y
|
||||
CONFIG_TICK_ONESHOT=y
|
||||
CONFIG_NO_HZ=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
|
@ -176,6 +191,15 @@ CONFIG_SYSVIPC_SYSCTL=y
|
|||
# CONFIG_BSD_PROCESS_ACCT is not set
|
||||
# CONFIG_TASKSTATS is not set
|
||||
# CONFIG_AUDIT is not set
|
||||
|
||||
#
|
||||
# RCU Subsystem
|
||||
#
|
||||
CONFIG_CLASSIC_RCU=y
|
||||
# CONFIG_TREE_RCU is not set
|
||||
# CONFIG_PREEMPT_RCU is not set
|
||||
# CONFIG_TREE_RCU_TRACE is not set
|
||||
# CONFIG_PREEMPT_RCU_TRACE is not set
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
CONFIG_LOG_BUF_SHIFT=14
|
||||
|
@ -190,7 +214,6 @@ CONFIG_CC_OPTIMIZE_FOR_SIZE=y
|
|||
CONFIG_SYSCTL=y
|
||||
CONFIG_EMBEDDED=y
|
||||
CONFIG_SYSCTL_SYSCALL=y
|
||||
CONFIG_SYSCTL_SYSCALL_CHECK=y
|
||||
CONFIG_KALLSYMS=y
|
||||
# CONFIG_KALLSYMS_EXTRA_PASS is not set
|
||||
# CONFIG_HOTPLUG is not set
|
||||
|
@ -207,30 +230,26 @@ CONFIG_SIGNALFD=y
|
|||
CONFIG_TIMERFD=y
|
||||
CONFIG_EVENTFD=y
|
||||
CONFIG_SHMEM=y
|
||||
CONFIG_AIO=y
|
||||
CONFIG_VM_EVENT_COUNTERS=y
|
||||
CONFIG_PCI_QUIRKS=y
|
||||
CONFIG_SLAB=y
|
||||
# CONFIG_SLUB is not set
|
||||
# CONFIG_SLOB is not set
|
||||
# CONFIG_PROFILING is not set
|
||||
# CONFIG_MARKERS is not set
|
||||
CONFIG_HAVE_OPROFILE=y
|
||||
# CONFIG_HAVE_KPROBES is not set
|
||||
# CONFIG_HAVE_KRETPROBES is not set
|
||||
# CONFIG_HAVE_DMA_ATTRS is not set
|
||||
CONFIG_PROC_PAGE_MONITOR=y
|
||||
# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
|
||||
CONFIG_SLABINFO=y
|
||||
# CONFIG_TINY_SHMEM is not set
|
||||
CONFIG_BASE_SMALL=0
|
||||
CONFIG_MODULES=y
|
||||
# CONFIG_MODULE_FORCE_LOAD is not set
|
||||
# CONFIG_MODULE_UNLOAD is not set
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
# CONFIG_MODVERSIONS is not set
|
||||
# CONFIG_MODULE_SRCVERSION_ALL is not set
|
||||
CONFIG_KMOD=y
|
||||
CONFIG_BLOCK=y
|
||||
# CONFIG_LBD is not set
|
||||
# CONFIG_BLK_DEV_IO_TRACE is not set
|
||||
# CONFIG_LSF is not set
|
||||
# CONFIG_BLK_DEV_INTEGRITY is not set
|
||||
|
||||
#
|
||||
# IO Schedulers
|
||||
|
@ -244,7 +263,8 @@ CONFIG_DEFAULT_AS=y
|
|||
# CONFIG_DEFAULT_CFQ is not set
|
||||
# CONFIG_DEFAULT_NOOP is not set
|
||||
CONFIG_DEFAULT_IOSCHED="anticipatory"
|
||||
CONFIG_CLASSIC_RCU=y
|
||||
# CONFIG_PROBE_INITRD_HEADER is not set
|
||||
# CONFIG_FREEZER is not set
|
||||
|
||||
#
|
||||
# Bus options (PCI, PCMCIA, EISA, ISA, TC)
|
||||
|
@ -254,12 +274,15 @@ CONFIG_PCI=y
|
|||
CONFIG_PCI_DOMAINS=y
|
||||
# CONFIG_ARCH_SUPPORTS_MSI is not set
|
||||
# CONFIG_PCI_LEGACY is not set
|
||||
# CONFIG_PCI_STUB is not set
|
||||
CONFIG_MMU=y
|
||||
|
||||
#
|
||||
# Executable file formats
|
||||
#
|
||||
CONFIG_BINFMT_ELF=y
|
||||
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
|
||||
# CONFIG_HAVE_AOUT is not set
|
||||
# CONFIG_BINFMT_MISC is not set
|
||||
CONFIG_TRAD_SIGNALS=y
|
||||
|
||||
|
@ -268,15 +291,12 @@ CONFIG_TRAD_SIGNALS=y
|
|||
#
|
||||
CONFIG_ARCH_SUSPEND_POSSIBLE=y
|
||||
# CONFIG_PM is not set
|
||||
|
||||
#
|
||||
# Networking
|
||||
#
|
||||
CONFIG_NET=y
|
||||
|
||||
#
|
||||
# Networking options
|
||||
#
|
||||
CONFIG_COMPAT_NET_DEV_OPS=y
|
||||
CONFIG_PACKET=y
|
||||
# CONFIG_PACKET_MMAP is not set
|
||||
CONFIG_UNIX=y
|
||||
|
@ -318,6 +338,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
|
|||
# CONFIG_IPX is not set
|
||||
# CONFIG_ATALK is not set
|
||||
# CONFIG_NET_SCHED is not set
|
||||
# CONFIG_DCB is not set
|
||||
|
||||
#
|
||||
# Network testing
|
||||
|
@ -327,14 +348,9 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
|
|||
# CONFIG_CAN is not set
|
||||
# CONFIG_IRDA is not set
|
||||
# CONFIG_BT is not set
|
||||
|
||||
#
|
||||
# Wireless
|
||||
#
|
||||
# CONFIG_CFG80211 is not set
|
||||
# CONFIG_WIRELESS_EXT is not set
|
||||
# CONFIG_MAC80211 is not set
|
||||
# CONFIG_IEEE80211 is not set
|
||||
# CONFIG_PHONET is not set
|
||||
# CONFIG_WIRELESS is not set
|
||||
# CONFIG_WIMAX is not set
|
||||
# CONFIG_RFKILL is not set
|
||||
|
||||
#
|
||||
|
@ -348,7 +364,90 @@ CONFIG_STANDALONE=y
|
|||
CONFIG_PREVENT_FIRMWARE_BUILD=y
|
||||
# CONFIG_SYS_HYPERVISOR is not set
|
||||
# CONFIG_CONNECTOR is not set
|
||||
# CONFIG_MTD is not set
|
||||
CONFIG_MTD=y
|
||||
# CONFIG_MTD_DEBUG is not set
|
||||
# CONFIG_MTD_CONCAT is not set
|
||||
CONFIG_MTD_PARTITIONS=y
|
||||
# CONFIG_MTD_TESTS is not set
|
||||
# CONFIG_MTD_REDBOOT_PARTS is not set
|
||||
CONFIG_MTD_CMDLINE_PARTS=y
|
||||
# CONFIG_MTD_AR7_PARTS is not set
|
||||
|
||||
#
|
||||
# User Modules And Translation Layers
|
||||
#
|
||||
CONFIG_MTD_CHAR=y
|
||||
# CONFIG_MTD_BLKDEVS is not set
|
||||
# CONFIG_MTD_BLOCK is not set
|
||||
# CONFIG_MTD_BLOCK_RO is not set
|
||||
# CONFIG_FTL is not set
|
||||
# CONFIG_NFTL is not set
|
||||
# CONFIG_INFTL is not set
|
||||
# CONFIG_RFD_FTL is not set
|
||||
# CONFIG_SSFDC is not set
|
||||
# CONFIG_MTD_OOPS is not set
|
||||
|
||||
#
|
||||
# RAM/ROM/Flash chip drivers
|
||||
#
|
||||
CONFIG_MTD_CFI=y
|
||||
CONFIG_MTD_JEDECPROBE=y
|
||||
CONFIG_MTD_GEN_PROBE=y
|
||||
# CONFIG_MTD_CFI_ADV_OPTIONS is not set
|
||||
CONFIG_MTD_MAP_BANK_WIDTH_1=y
|
||||
CONFIG_MTD_MAP_BANK_WIDTH_2=y
|
||||
CONFIG_MTD_MAP_BANK_WIDTH_4=y
|
||||
# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
|
||||
# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
|
||||
# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
|
||||
CONFIG_MTD_CFI_I1=y
|
||||
CONFIG_MTD_CFI_I2=y
|
||||
# CONFIG_MTD_CFI_I4 is not set
|
||||
# CONFIG_MTD_CFI_I8 is not set
|
||||
# CONFIG_MTD_CFI_INTELEXT is not set
|
||||
CONFIG_MTD_CFI_AMDSTD=y
|
||||
# CONFIG_MTD_CFI_STAA is not set
|
||||
CONFIG_MTD_CFI_UTIL=y
|
||||
# CONFIG_MTD_RAM is not set
|
||||
# CONFIG_MTD_ROM is not set
|
||||
# CONFIG_MTD_ABSENT is not set
|
||||
|
||||
#
|
||||
# Mapping drivers for chip access
|
||||
#
|
||||
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
|
||||
CONFIG_MTD_PHYSMAP=y
|
||||
# CONFIG_MTD_PHYSMAP_COMPAT is not set
|
||||
# CONFIG_MTD_INTEL_VR_NOR is not set
|
||||
# CONFIG_MTD_PLATRAM is not set
|
||||
|
||||
#
|
||||
# Self-contained MTD device drivers
|
||||
#
|
||||
# CONFIG_MTD_PMC551 is not set
|
||||
# CONFIG_MTD_SLRAM is not set
|
||||
# CONFIG_MTD_PHRAM is not set
|
||||
# CONFIG_MTD_MTDRAM is not set
|
||||
# CONFIG_MTD_BLOCK2MTD is not set
|
||||
|
||||
#
|
||||
# Disk-On-Chip Device Drivers
|
||||
#
|
||||
# CONFIG_MTD_DOC2000 is not set
|
||||
# CONFIG_MTD_DOC2001 is not set
|
||||
# CONFIG_MTD_DOC2001PLUS is not set
|
||||
# CONFIG_MTD_NAND is not set
|
||||
# CONFIG_MTD_ONENAND is not set
|
||||
|
||||
#
|
||||
# LPDDR flash memory drivers
|
||||
#
|
||||
# CONFIG_MTD_LPDDR is not set
|
||||
|
||||
#
|
||||
# UBI - Unsorted block images
|
||||
#
|
||||
# CONFIG_MTD_UBI is not set
|
||||
# CONFIG_PARPORT is not set
|
||||
CONFIG_BLK_DEV=y
|
||||
# CONFIG_BLK_CPQ_DA is not set
|
||||
|
@ -365,9 +464,60 @@ CONFIG_BLK_DEV_RAM_SIZE=8192
|
|||
# CONFIG_BLK_DEV_XIP is not set
|
||||
# CONFIG_CDROM_PKTCDVD is not set
|
||||
# CONFIG_ATA_OVER_ETH is not set
|
||||
# CONFIG_BLK_DEV_HD is not set
|
||||
# CONFIG_MISC_DEVICES is not set
|
||||
CONFIG_HAVE_IDE=y
|
||||
# CONFIG_IDE is not set
|
||||
CONFIG_IDE=y
|
||||
|
||||
#
|
||||
# Please see Documentation/ide/ide.txt for help/info on IDE drives
|
||||
#
|
||||
CONFIG_IDE_TIMINGS=y
|
||||
# CONFIG_BLK_DEV_IDE_SATA is not set
|
||||
CONFIG_IDE_GD=y
|
||||
CONFIG_IDE_GD_ATA=y
|
||||
# CONFIG_IDE_GD_ATAPI is not set
|
||||
# CONFIG_BLK_DEV_IDECD is not set
|
||||
# CONFIG_BLK_DEV_IDETAPE is not set
|
||||
# CONFIG_IDE_TASK_IOCTL is not set
|
||||
CONFIG_IDE_PROC_FS=y
|
||||
|
||||
#
|
||||
# IDE chipset support/bugfixes
|
||||
#
|
||||
# CONFIG_IDE_GENERIC is not set
|
||||
# CONFIG_BLK_DEV_PLATFORM is not set
|
||||
CONFIG_BLK_DEV_IDEDMA_SFF=y
|
||||
|
||||
#
|
||||
# PCI IDE chipsets support
|
||||
#
|
||||
# CONFIG_BLK_DEV_GENERIC is not set
|
||||
# CONFIG_BLK_DEV_AEC62XX is not set
|
||||
# CONFIG_BLK_DEV_ALI15X3 is not set
|
||||
# CONFIG_BLK_DEV_AMD74XX is not set
|
||||
# CONFIG_BLK_DEV_CMD64X is not set
|
||||
# CONFIG_BLK_DEV_TRIFLEX is not set
|
||||
# CONFIG_BLK_DEV_CS5530 is not set
|
||||
# CONFIG_BLK_DEV_HPT366 is not set
|
||||
# CONFIG_BLK_DEV_JMICRON is not set
|
||||
# CONFIG_BLK_DEV_SC1200 is not set
|
||||
# CONFIG_BLK_DEV_PIIX is not set
|
||||
# CONFIG_BLK_DEV_IT8172 is not set
|
||||
# CONFIG_BLK_DEV_IT8213 is not set
|
||||
# CONFIG_BLK_DEV_IT821X is not set
|
||||
# CONFIG_BLK_DEV_NS87415 is not set
|
||||
# CONFIG_BLK_DEV_PDC202XX_OLD is not set
|
||||
# CONFIG_BLK_DEV_PDC202XX_NEW is not set
|
||||
# CONFIG_BLK_DEV_SVWKS is not set
|
||||
# CONFIG_BLK_DEV_SIIMAGE is not set
|
||||
# CONFIG_BLK_DEV_SLC90E66 is not set
|
||||
# CONFIG_BLK_DEV_TRM290 is not set
|
||||
# CONFIG_BLK_DEV_VIA82CXXX is not set
|
||||
# CONFIG_BLK_DEV_TC86C001 is not set
|
||||
CONFIG_BLK_DEV_IDE_TX4938=y
|
||||
CONFIG_BLK_DEV_IDE_TX4939=y
|
||||
CONFIG_BLK_DEV_IDEDMA=y
|
||||
|
||||
#
|
||||
# SCSI device support
|
||||
|
@ -390,7 +540,6 @@ CONFIG_HAVE_IDE=y
|
|||
# CONFIG_IEEE1394 is not set
|
||||
# CONFIG_I2O is not set
|
||||
CONFIG_NETDEVICES=y
|
||||
# CONFIG_NETDEVICES_MULTIQUEUE is not set
|
||||
# CONFIG_DUMMY is not set
|
||||
# CONFIG_BONDING is not set
|
||||
# CONFIG_EQUALIZER is not set
|
||||
|
@ -412,15 +561,19 @@ CONFIG_PHYLIB=y
|
|||
# CONFIG_BROADCOM_PHY is not set
|
||||
# CONFIG_ICPLUS_PHY is not set
|
||||
# CONFIG_REALTEK_PHY is not set
|
||||
# CONFIG_NATIONAL_PHY is not set
|
||||
# CONFIG_STE10XP is not set
|
||||
# CONFIG_LSI_ET1011C_PHY is not set
|
||||
# CONFIG_FIXED_PHY is not set
|
||||
# CONFIG_MDIO_BITBANG is not set
|
||||
CONFIG_NET_ETHERNET=y
|
||||
# CONFIG_MII is not set
|
||||
CONFIG_MII=y
|
||||
# CONFIG_AX88796 is not set
|
||||
# CONFIG_HAPPYMEAL is not set
|
||||
# CONFIG_SUNGEM is not set
|
||||
# CONFIG_CASSINI is not set
|
||||
# CONFIG_NET_VENDOR_3COM is not set
|
||||
CONFIG_SMC91X=y
|
||||
# CONFIG_DM9000 is not set
|
||||
# CONFIG_NET_TULIP is not set
|
||||
# CONFIG_HP100 is not set
|
||||
|
@ -429,6 +582,9 @@ CONFIG_NE2000=y
|
|||
# CONFIG_IBM_NEW_EMAC_RGMII is not set
|
||||
# CONFIG_IBM_NEW_EMAC_TAH is not set
|
||||
# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
|
||||
# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
|
||||
# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
|
||||
# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
|
||||
CONFIG_NET_PCI=y
|
||||
# CONFIG_PCNET32 is not set
|
||||
# CONFIG_AMD8111_ETH is not set
|
||||
|
@ -436,7 +592,6 @@ CONFIG_NET_PCI=y
|
|||
# CONFIG_B44 is not set
|
||||
# CONFIG_FORCEDETH is not set
|
||||
CONFIG_TC35815=y
|
||||
# CONFIG_EEPRO100 is not set
|
||||
# CONFIG_E100 is not set
|
||||
# CONFIG_FEALNX is not set
|
||||
# CONFIG_NATSEMI is not set
|
||||
|
@ -445,9 +600,11 @@ CONFIG_TC35815=y
|
|||
# CONFIG_R6040 is not set
|
||||
# CONFIG_SIS900 is not set
|
||||
# CONFIG_EPIC100 is not set
|
||||
# CONFIG_SMSC9420 is not set
|
||||
# CONFIG_SUNDANCE is not set
|
||||
# CONFIG_TLAN is not set
|
||||
# CONFIG_VIA_RHINE is not set
|
||||
# CONFIG_ATL2 is not set
|
||||
# CONFIG_NETDEV_1000 is not set
|
||||
# CONFIG_NETDEV_10000 is not set
|
||||
# CONFIG_TR is not set
|
||||
|
@ -458,6 +615,10 @@ CONFIG_TC35815=y
|
|||
# CONFIG_WLAN_PRE80211 is not set
|
||||
# CONFIG_WLAN_80211 is not set
|
||||
# CONFIG_IWLWIFI_LEDS is not set
|
||||
|
||||
#
|
||||
# Enable WiMAX (Networking options) to see the WiMAX drivers
|
||||
#
|
||||
# CONFIG_WAN is not set
|
||||
# CONFIG_FDDI is not set
|
||||
# CONFIG_PPP is not set
|
||||
|
@ -502,6 +663,7 @@ CONFIG_SERIAL_TXX9_CONSOLE=y
|
|||
CONFIG_SERIAL_TXX9_STDSERIAL=y
|
||||
# CONFIG_SERIAL_JSM is not set
|
||||
CONFIG_UNIX98_PTYS=y
|
||||
# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
|
||||
CONFIG_LEGACY_PTYS=y
|
||||
CONFIG_LEGACY_PTY_COUNT=256
|
||||
# CONFIG_IPMI_HANDLER is not set
|
||||
|
@ -517,26 +679,34 @@ CONFIG_SPI_MASTER=y
|
|||
#
|
||||
# SPI Master Controller Drivers
|
||||
#
|
||||
# CONFIG_SPI_BITBANG is not set
|
||||
# CONFIG_SPI_GPIO is not set
|
||||
CONFIG_SPI_TXX9=y
|
||||
|
||||
#
|
||||
# SPI Protocol Masters
|
||||
#
|
||||
CONFIG_EEPROM_AT25=y
|
||||
# CONFIG_SPI_TLE62X0 is not set
|
||||
CONFIG_HAVE_GPIO_LIB=y
|
||||
CONFIG_ARCH_REQUIRE_GPIOLIB=y
|
||||
CONFIG_GPIOLIB=y
|
||||
|
||||
#
|
||||
# GPIO Support
|
||||
# Memory mapped GPIO expanders:
|
||||
#
|
||||
|
||||
#
|
||||
# I2C GPIO expanders:
|
||||
#
|
||||
|
||||
#
|
||||
# PCI GPIO expanders:
|
||||
#
|
||||
# CONFIG_GPIO_BT8XX is not set
|
||||
|
||||
#
|
||||
# SPI GPIO expanders:
|
||||
#
|
||||
# CONFIG_GPIO_MAX7301 is not set
|
||||
# CONFIG_GPIO_MCP23S08 is not set
|
||||
# CONFIG_W1 is not set
|
||||
# CONFIG_POWER_SUPPLY is not set
|
||||
|
@ -550,6 +720,7 @@ CONFIG_WATCHDOG=y
|
|||
# Watchdog Device Drivers
|
||||
#
|
||||
# CONFIG_SOFT_WATCHDOG is not set
|
||||
# CONFIG_ALIM7101_WDT is not set
|
||||
CONFIG_TXX9_WDT=m
|
||||
|
||||
#
|
||||
|
@ -557,18 +728,21 @@ CONFIG_TXX9_WDT=m
|
|||
#
|
||||
# CONFIG_PCIPCWATCHDOG is not set
|
||||
# CONFIG_WDTPCI is not set
|
||||
CONFIG_SSB_POSSIBLE=y
|
||||
|
||||
#
|
||||
# Sonics Silicon Backplane
|
||||
#
|
||||
CONFIG_SSB_POSSIBLE=y
|
||||
# CONFIG_SSB is not set
|
||||
|
||||
#
|
||||
# Multifunction device drivers
|
||||
#
|
||||
# CONFIG_MFD_CORE is not set
|
||||
# CONFIG_MFD_SM501 is not set
|
||||
# CONFIG_HTC_PASIC3 is not set
|
||||
# CONFIG_MFD_TMIO is not set
|
||||
# CONFIG_REGULATOR is not set
|
||||
|
||||
#
|
||||
# Multimedia devices
|
||||
|
@ -599,15 +773,27 @@ CONFIG_SSB_POSSIBLE=y
|
|||
# Display device support
|
||||
#
|
||||
# CONFIG_DISPLAY_SUPPORT is not set
|
||||
|
||||
#
|
||||
# Sound
|
||||
#
|
||||
# CONFIG_SOUND is not set
|
||||
# CONFIG_USB_SUPPORT is not set
|
||||
# CONFIG_MMC is not set
|
||||
# CONFIG_MEMSTICK is not set
|
||||
# CONFIG_NEW_LEDS is not set
|
||||
CONFIG_NEW_LEDS=y
|
||||
CONFIG_LEDS_CLASS=y
|
||||
|
||||
#
|
||||
# LED drivers
|
||||
#
|
||||
CONFIG_LEDS_GPIO=y
|
||||
|
||||
#
|
||||
# LED Triggers
|
||||
#
|
||||
CONFIG_LEDS_TRIGGERS=y
|
||||
# CONFIG_LEDS_TRIGGER_TIMER is not set
|
||||
CONFIG_LEDS_TRIGGER_IDE_DISK=y
|
||||
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
|
||||
# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
|
||||
# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
|
||||
# CONFIG_ACCESSIBILITY is not set
|
||||
# CONFIG_INFINIBAND is not set
|
||||
CONFIG_RTC_LIB=y
|
||||
|
@ -628,35 +814,47 @@ CONFIG_RTC_INTF_DEV_UIE_EMUL=y
|
|||
#
|
||||
# SPI RTC drivers
|
||||
#
|
||||
# CONFIG_RTC_DRV_M41T94 is not set
|
||||
# CONFIG_RTC_DRV_DS1305 is not set
|
||||
# CONFIG_RTC_DRV_DS1390 is not set
|
||||
# CONFIG_RTC_DRV_MAX6902 is not set
|
||||
# CONFIG_RTC_DRV_R9701 is not set
|
||||
CONFIG_RTC_DRV_RS5C348=y
|
||||
# CONFIG_RTC_DRV_DS3234 is not set
|
||||
|
||||
#
|
||||
# Platform RTC drivers
|
||||
#
|
||||
# CONFIG_RTC_DRV_CMOS is not set
|
||||
# CONFIG_RTC_DRV_DS1286 is not set
|
||||
# CONFIG_RTC_DRV_DS1511 is not set
|
||||
# CONFIG_RTC_DRV_DS1553 is not set
|
||||
CONFIG_RTC_DRV_DS1742=y
|
||||
# CONFIG_RTC_DRV_STK17TA8 is not set
|
||||
# CONFIG_RTC_DRV_M48T86 is not set
|
||||
# CONFIG_RTC_DRV_M48T35 is not set
|
||||
# CONFIG_RTC_DRV_M48T59 is not set
|
||||
# CONFIG_RTC_DRV_BQ4802 is not set
|
||||
# CONFIG_RTC_DRV_V3020 is not set
|
||||
|
||||
#
|
||||
# on-CPU RTC drivers
|
||||
#
|
||||
CONFIG_RTC_DRV_TX4939=y
|
||||
# CONFIG_DMADEVICES is not set
|
||||
# CONFIG_UIO is not set
|
||||
# CONFIG_STAGING is not set
|
||||
|
||||
#
|
||||
# File systems
|
||||
#
|
||||
# CONFIG_EXT2_FS is not set
|
||||
# CONFIG_EXT3_FS is not set
|
||||
# CONFIG_EXT4_FS is not set
|
||||
# CONFIG_REISERFS_FS is not set
|
||||
# CONFIG_JFS_FS is not set
|
||||
CONFIG_FS_POSIX_ACL=y
|
||||
CONFIG_FILE_LOCKING=y
|
||||
# CONFIG_XFS_FS is not set
|
||||
# CONFIG_OCFS2_FS is not set
|
||||
# CONFIG_DNOTIFY is not set
|
||||
|
@ -687,30 +885,19 @@ CONFIG_GENERIC_ACL=y
|
|||
CONFIG_PROC_FS=y
|
||||
# CONFIG_PROC_KCORE is not set
|
||||
CONFIG_PROC_SYSCTL=y
|
||||
CONFIG_PROC_PAGE_MONITOR=y
|
||||
CONFIG_SYSFS=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_TMPFS_POSIX_ACL=y
|
||||
# CONFIG_HUGETLB_PAGE is not set
|
||||
# CONFIG_CONFIGFS_FS is not set
|
||||
|
||||
#
|
||||
# Miscellaneous filesystems
|
||||
#
|
||||
# CONFIG_HFSPLUS_FS is not set
|
||||
# CONFIG_CRAMFS is not set
|
||||
# CONFIG_VXFS_FS is not set
|
||||
# CONFIG_MINIX_FS is not set
|
||||
# CONFIG_HPFS_FS is not set
|
||||
# CONFIG_QNX4FS_FS is not set
|
||||
# CONFIG_ROMFS_FS is not set
|
||||
# CONFIG_SYSV_FS is not set
|
||||
# CONFIG_UFS_FS is not set
|
||||
# CONFIG_MISC_FILESYSTEMS is not set
|
||||
CONFIG_NETWORK_FILESYSTEMS=y
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_NFS_V3=y
|
||||
# CONFIG_NFS_V3_ACL is not set
|
||||
# CONFIG_NFSD is not set
|
||||
CONFIG_ROOT_NFS=y
|
||||
# CONFIG_NFSD is not set
|
||||
CONFIG_LOCKD=y
|
||||
CONFIG_LOCKD_V4=y
|
||||
CONFIG_NFS_COMMON=y
|
||||
|
@ -740,7 +927,16 @@ CONFIG_FRAME_WARN=1024
|
|||
CONFIG_DEBUG_FS=y
|
||||
# CONFIG_HEADERS_CHECK is not set
|
||||
# CONFIG_DEBUG_KERNEL is not set
|
||||
# CONFIG_DEBUG_MEMORY_INIT is not set
|
||||
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
|
||||
CONFIG_SYSCTL_SYSCALL_CHECK=y
|
||||
|
||||
#
|
||||
# Tracers
|
||||
#
|
||||
# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
|
||||
# CONFIG_SAMPLES is not set
|
||||
CONFIG_HAVE_ARCH_KGDB=y
|
||||
CONFIG_CMDLINE=""
|
||||
|
||||
#
|
||||
|
@ -748,15 +944,18 @@ CONFIG_CMDLINE=""
|
|||
#
|
||||
# CONFIG_KEYS is not set
|
||||
# CONFIG_SECURITY is not set
|
||||
# CONFIG_SECURITYFS is not set
|
||||
# CONFIG_SECURITY_FILE_CAPABILITIES is not set
|
||||
# CONFIG_CRYPTO is not set
|
||||
|
||||
#
|
||||
# Library routines
|
||||
#
|
||||
CONFIG_BITREVERSE=y
|
||||
# CONFIG_GENERIC_FIND_FIRST_BIT is not set
|
||||
CONFIG_GENERIC_FIND_LAST_BIT=y
|
||||
# CONFIG_CRC_CCITT is not set
|
||||
# CONFIG_CRC16 is not set
|
||||
# CONFIG_CRC_T10DIF is not set
|
||||
# CONFIG_CRC_ITU_T is not set
|
||||
CONFIG_CRC32=y
|
||||
# CONFIG_CRC7 is not set
|
||||
|
|
|
@ -138,7 +138,8 @@ do { \
|
|||
__instruction_hazard(); \
|
||||
} while (0)
|
||||
|
||||
#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_CAVIUM_OCTEON)
|
||||
#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \
|
||||
defined(CONFIG_CPU_R5500)
|
||||
|
||||
/*
|
||||
* R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
|
||||
|
|
|
@ -26,7 +26,7 @@
|
|||
* Pref_WriteBackInvalidate is a nop and Pref_PrepareForStore is broken in
|
||||
* current versions due to erratum G105.
|
||||
*
|
||||
* VR7701 only implements the Load prefetch.
|
||||
* VR5500 (including VR5701 and VR7701) only implement load prefetch.
|
||||
*
|
||||
* Finally MIPS32 and MIPS64 implement all of the following hints.
|
||||
*/
|
||||
|
|
|
@ -149,6 +149,7 @@ void __init check_wait(void)
|
|||
case CPU_R4650:
|
||||
case CPU_R4700:
|
||||
case CPU_R5000:
|
||||
case CPU_R5500:
|
||||
case CPU_NEVADA:
|
||||
case CPU_4KC:
|
||||
case CPU_4KEC:
|
||||
|
|
|
@ -235,7 +235,7 @@ SYSCALL_DEFINE6(32_ipc, u32, call, long, first, long, second, long, third,
|
|||
#else
|
||||
|
||||
SYSCALL_DEFINE6(32_ipc, u32, call, int, first, int, second, int, third,
|
||||
u32, ptr, u32 fifth)
|
||||
u32, ptr, u32, fifth)
|
||||
{
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
|
|
@ -172,8 +172,9 @@ static void __cpuinit set_prefetch_parameters(void)
|
|||
*/
|
||||
cache_line_size = cpu_dcache_line_size();
|
||||
switch (current_cpu_type()) {
|
||||
case CPU_R5500:
|
||||
case CPU_TX49XX:
|
||||
/* TX49 supports only Pref_Load */
|
||||
/* These processors only support the Pref_Load. */
|
||||
pref_bias_copy_load = 256;
|
||||
break;
|
||||
|
||||
|
|
|
@ -318,6 +318,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
|
|||
case CPU_BCM4710:
|
||||
case CPU_LOONGSON2:
|
||||
case CPU_CAVIUM_OCTEON:
|
||||
case CPU_R5500:
|
||||
if (m4kc_tlbp_war())
|
||||
uasm_i_nop(p);
|
||||
tlbw(p);
|
||||
|
|
|
@ -686,7 +686,7 @@ CONFIG_SERIAL_UARTLITE_CONSOLE=y
|
|||
CONFIG_SERIAL_CORE=y
|
||||
CONFIG_SERIAL_CORE_CONSOLE=y
|
||||
# CONFIG_SERIAL_JSM is not set
|
||||
# CONFIG_SERIAL_OF_PLATFORM is not set
|
||||
CONFIG_SERIAL_OF_PLATFORM=y
|
||||
# CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL is not set
|
||||
CONFIG_UNIX98_PTYS=y
|
||||
# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
|
||||
|
|
|
@ -691,7 +691,7 @@ CONFIG_SERIAL_UARTLITE_CONSOLE=y
|
|||
CONFIG_SERIAL_CORE=y
|
||||
CONFIG_SERIAL_CORE_CONSOLE=y
|
||||
# CONFIG_SERIAL_JSM is not set
|
||||
# CONFIG_SERIAL_OF_PLATFORM is not set
|
||||
CONFIG_SERIAL_OF_PLATFORM=y
|
||||
# CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL is not set
|
||||
CONFIG_UNIX98_PTYS=y
|
||||
# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
#
|
||||
# Automatically generated make config: don't edit
|
||||
# Linux kernel version: 2.6.29-rc2
|
||||
# Mon Jan 26 15:35:29 2009
|
||||
# Linux kernel version: 2.6.29-rc6
|
||||
# Fri Mar 6 00:07:38 2009
|
||||
#
|
||||
# CONFIG_PPC64 is not set
|
||||
|
||||
|
@ -71,6 +71,15 @@ CONFIG_POSIX_MQUEUE=y
|
|||
# CONFIG_BSD_PROCESS_ACCT is not set
|
||||
# CONFIG_TASKSTATS is not set
|
||||
# CONFIG_AUDIT is not set
|
||||
|
||||
#
|
||||
# RCU Subsystem
|
||||
#
|
||||
CONFIG_CLASSIC_RCU=y
|
||||
# CONFIG_TREE_RCU is not set
|
||||
# CONFIG_PREEMPT_RCU is not set
|
||||
# CONFIG_TREE_RCU_TRACE is not set
|
||||
# CONFIG_PREEMPT_RCU_TRACE is not set
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
CONFIG_LOG_BUF_SHIFT=14
|
||||
|
@ -88,6 +97,7 @@ CONFIG_NAMESPACES=y
|
|||
# CONFIG_IPC_NS is not set
|
||||
# CONFIG_USER_NS is not set
|
||||
# CONFIG_PID_NS is not set
|
||||
# CONFIG_NET_NS is not set
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
CONFIG_INITRAMFS_SOURCE=""
|
||||
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
|
||||
|
@ -153,11 +163,6 @@ CONFIG_DEFAULT_AS=y
|
|||
# CONFIG_DEFAULT_CFQ is not set
|
||||
# CONFIG_DEFAULT_NOOP is not set
|
||||
CONFIG_DEFAULT_IOSCHED="anticipatory"
|
||||
CONFIG_CLASSIC_RCU=y
|
||||
# CONFIG_TREE_RCU is not set
|
||||
# CONFIG_PREEMPT_RCU is not set
|
||||
# CONFIG_TREE_RCU_TRACE is not set
|
||||
# CONFIG_PREEMPT_RCU_TRACE is not set
|
||||
# CONFIG_FREEZER is not set
|
||||
|
||||
#
|
||||
|
@ -294,7 +299,6 @@ CONFIG_NET=y
|
|||
#
|
||||
# Networking options
|
||||
#
|
||||
# CONFIG_NET_NS is not set
|
||||
CONFIG_COMPAT_NET_DEV_OPS=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_PACKET_MMAP=y
|
||||
|
@ -508,8 +512,8 @@ CONFIG_MTD_CONCAT=y
|
|||
CONFIG_MTD_PARTITIONS=y
|
||||
# CONFIG_MTD_TESTS is not set
|
||||
# CONFIG_MTD_REDBOOT_PARTS is not set
|
||||
# CONFIG_MTD_CMDLINE_PARTS is not set
|
||||
# CONFIG_MTD_OF_PARTS is not set
|
||||
CONFIG_MTD_CMDLINE_PARTS=y
|
||||
CONFIG_MTD_OF_PARTS=y
|
||||
# CONFIG_MTD_AR7_PARTS is not set
|
||||
|
||||
#
|
||||
|
@ -587,7 +591,6 @@ CONFIG_MTD_PHYSMAP=y
|
|||
# LPDDR flash memory drivers
|
||||
#
|
||||
# CONFIG_MTD_LPDDR is not set
|
||||
# CONFIG_MTD_QINFO_PROBE is not set
|
||||
|
||||
#
|
||||
# UBI - Unsorted block images
|
||||
|
@ -617,13 +620,19 @@ CONFIG_BLK_DEV_RAM_SIZE=8192
|
|||
# CONFIG_BLK_DEV_HD is not set
|
||||
CONFIG_MISC_DEVICES=y
|
||||
# CONFIG_PHANTOM is not set
|
||||
# CONFIG_EEPROM_93CX6 is not set
|
||||
# CONFIG_SGI_IOC4 is not set
|
||||
# CONFIG_TIFM_CORE is not set
|
||||
# CONFIG_ICS932S401 is not set
|
||||
# CONFIG_ENCLOSURE_SERVICES is not set
|
||||
# CONFIG_HP_ILO is not set
|
||||
# CONFIG_C2PORT is not set
|
||||
|
||||
#
|
||||
# EEPROM support
|
||||
#
|
||||
# CONFIG_EEPROM_AT24 is not set
|
||||
CONFIG_EEPROM_LEGACY=m
|
||||
# CONFIG_EEPROM_93CX6 is not set
|
||||
CONFIG_HAVE_IDE=y
|
||||
# CONFIG_IDE is not set
|
||||
|
||||
|
@ -839,6 +848,7 @@ CONFIG_R8169=y
|
|||
# CONFIG_QLA3XXX is not set
|
||||
# CONFIG_ATL1 is not set
|
||||
# CONFIG_ATL1E is not set
|
||||
# CONFIG_ATL1C is not set
|
||||
# CONFIG_JME is not set
|
||||
CONFIG_NETDEV_10000=y
|
||||
# CONFIG_CHELSIO_T1 is not set
|
||||
|
@ -1037,8 +1047,6 @@ CONFIG_I2C_MPC=y
|
|||
# Miscellaneous I2C Chip support
|
||||
#
|
||||
# CONFIG_DS1682 is not set
|
||||
# CONFIG_EEPROM_AT24 is not set
|
||||
CONFIG_EEPROM_LEGACY=m
|
||||
# CONFIG_SENSORS_PCF8574 is not set
|
||||
# CONFIG_PCF8575 is not set
|
||||
# CONFIG_SENSORS_PCA9539 is not set
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
#
|
||||
# Automatically generated make config: don't edit
|
||||
# Linux kernel version: 2.6.29-rc2
|
||||
# Mon Jan 26 15:35:46 2009
|
||||
# Linux kernel version: 2.6.29-rc6
|
||||
# Fri Mar 6 00:09:08 2009
|
||||
#
|
||||
# CONFIG_PPC64 is not set
|
||||
|
||||
|
@ -71,6 +71,15 @@ CONFIG_SYSVIPC_SYSCTL=y
|
|||
# CONFIG_BSD_PROCESS_ACCT is not set
|
||||
# CONFIG_TASKSTATS is not set
|
||||
# CONFIG_AUDIT is not set
|
||||
|
||||
#
|
||||
# RCU Subsystem
|
||||
#
|
||||
CONFIG_CLASSIC_RCU=y
|
||||
# CONFIG_TREE_RCU is not set
|
||||
# CONFIG_PREEMPT_RCU is not set
|
||||
# CONFIG_TREE_RCU_TRACE is not set
|
||||
# CONFIG_PREEMPT_RCU_TRACE is not set
|
||||
# CONFIG_IKCONFIG is not set
|
||||
CONFIG_LOG_BUF_SHIFT=14
|
||||
CONFIG_GROUP_SCHED=y
|
||||
|
@ -144,11 +153,6 @@ CONFIG_IOSCHED_CFQ=y
|
|||
CONFIG_DEFAULT_CFQ=y
|
||||
# CONFIG_DEFAULT_NOOP is not set
|
||||
CONFIG_DEFAULT_IOSCHED="cfq"
|
||||
CONFIG_CLASSIC_RCU=y
|
||||
# CONFIG_TREE_RCU is not set
|
||||
# CONFIG_PREEMPT_RCU is not set
|
||||
# CONFIG_TREE_RCU_TRACE is not set
|
||||
# CONFIG_PREEMPT_RCU_TRACE is not set
|
||||
# CONFIG_FREEZER is not set
|
||||
|
||||
#
|
||||
|
@ -377,8 +381,8 @@ CONFIG_MTD=y
|
|||
CONFIG_MTD_PARTITIONS=y
|
||||
# CONFIG_MTD_TESTS is not set
|
||||
# CONFIG_MTD_REDBOOT_PARTS is not set
|
||||
# CONFIG_MTD_CMDLINE_PARTS is not set
|
||||
# CONFIG_MTD_OF_PARTS is not set
|
||||
CONFIG_MTD_CMDLINE_PARTS=y
|
||||
CONFIG_MTD_OF_PARTS=y
|
||||
# CONFIG_MTD_AR7_PARTS is not set
|
||||
|
||||
#
|
||||
|
@ -452,7 +456,6 @@ CONFIG_MTD_PHYSMAP=y
|
|||
# LPDDR flash memory drivers
|
||||
#
|
||||
# CONFIG_MTD_LPDDR is not set
|
||||
# CONFIG_MTD_QINFO_PROBE is not set
|
||||
|
||||
#
|
||||
# UBI - Unsorted block images
|
||||
|
@ -478,13 +481,19 @@ CONFIG_BLK_DEV=y
|
|||
# CONFIG_BLK_DEV_HD is not set
|
||||
CONFIG_MISC_DEVICES=y
|
||||
# CONFIG_PHANTOM is not set
|
||||
# CONFIG_EEPROM_93CX6 is not set
|
||||
# CONFIG_SGI_IOC4 is not set
|
||||
# CONFIG_TIFM_CORE is not set
|
||||
# CONFIG_ICS932S401 is not set
|
||||
# CONFIG_ENCLOSURE_SERVICES is not set
|
||||
# CONFIG_HP_ILO is not set
|
||||
# CONFIG_C2PORT is not set
|
||||
|
||||
#
|
||||
# EEPROM support
|
||||
#
|
||||
# CONFIG_EEPROM_AT24 is not set
|
||||
# CONFIG_EEPROM_LEGACY is not set
|
||||
# CONFIG_EEPROM_93CX6 is not set
|
||||
CONFIG_HAVE_IDE=y
|
||||
CONFIG_IDE=y
|
||||
|
||||
|
@ -677,6 +686,7 @@ CONFIG_R8169=y
|
|||
# CONFIG_QLA3XXX is not set
|
||||
# CONFIG_ATL1 is not set
|
||||
# CONFIG_ATL1E is not set
|
||||
# CONFIG_ATL1C is not set
|
||||
# CONFIG_JME is not set
|
||||
# CONFIG_NETDEV_10000 is not set
|
||||
# CONFIG_TR is not set
|
||||
|
@ -818,8 +828,6 @@ CONFIG_I2C_MPC=y
|
|||
# Miscellaneous I2C Chip support
|
||||
#
|
||||
# CONFIG_DS1682 is not set
|
||||
# CONFIG_EEPROM_AT24 is not set
|
||||
# CONFIG_EEPROM_LEGACY is not set
|
||||
# CONFIG_SENSORS_PCF8574 is not set
|
||||
# CONFIG_PCF8575 is not set
|
||||
# CONFIG_SENSORS_PCA9539 is not set
|
||||
|
@ -1159,6 +1167,7 @@ CONFIG_JFFS2_RTIME=y
|
|||
# CONFIG_SYSV_FS is not set
|
||||
# CONFIG_UFS_FS is not set
|
||||
# CONFIG_NETWORK_FILESYSTEMS is not set
|
||||
CONFIG_EXPORTFS=m
|
||||
|
||||
#
|
||||
# Partition Types
|
||||
|
|
|
@ -12,7 +12,6 @@
|
|||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/initrd.h>
|
||||
#include <linux/mtd/physmap.h>
|
||||
#include <linux/of_platform.h>
|
||||
|
||||
#include <asm/time.h>
|
||||
|
@ -22,39 +21,6 @@
|
|||
|
||||
#include "mpc10x.h"
|
||||
|
||||
static struct mtd_partition linkstation_physmap_partitions[] = {
|
||||
{
|
||||
.name = "mtd_firmimg",
|
||||
.offset = 0x000000,
|
||||
.size = 0x300000,
|
||||
},
|
||||
{
|
||||
.name = "mtd_bootcode",
|
||||
.offset = 0x300000,
|
||||
.size = 0x070000,
|
||||
},
|
||||
{
|
||||
.name = "mtd_status",
|
||||
.offset = 0x370000,
|
||||
.size = 0x010000,
|
||||
},
|
||||
{
|
||||
.name = "mtd_conf",
|
||||
.offset = 0x380000,
|
||||
.size = 0x080000,
|
||||
},
|
||||
{
|
||||
.name = "mtd_allflash",
|
||||
.offset = 0x000000,
|
||||
.size = 0x400000,
|
||||
},
|
||||
{
|
||||
.name = "mtd_data",
|
||||
.offset = 0x310000,
|
||||
.size = 0x0f0000,
|
||||
},
|
||||
};
|
||||
|
||||
static __initdata struct of_device_id of_bus_ids[] = {
|
||||
{ .type = "soc", },
|
||||
{ .compatible = "simple-bus", },
|
||||
|
@ -99,10 +65,6 @@ static int __init linkstation_add_bridge(struct device_node *dev)
|
|||
static void __init linkstation_setup_arch(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
#ifdef CONFIG_MTD_PHYSMAP
|
||||
physmap_set_partitions(linkstation_physmap_partitions,
|
||||
ARRAY_SIZE(linkstation_physmap_partitions));
|
||||
#endif
|
||||
|
||||
/* Lookup PCI host bridges */
|
||||
for_each_compatible_node(np, "pci", "mpc10x-pci")
|
||||
|
|
|
@ -14,7 +14,6 @@
|
|||
#include <linux/kernel.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/initrd.h>
|
||||
#include <linux/mtd/physmap.h>
|
||||
#include <linux/of_platform.h>
|
||||
|
||||
#include <asm/system.h>
|
||||
|
@ -26,32 +25,6 @@
|
|||
#include "mpc10x.h"
|
||||
|
||||
|
||||
#ifdef CONFIG_MTD_PHYSMAP
|
||||
static struct mtd_partition storcenter_physmap_partitions[] = {
|
||||
{
|
||||
.name = "kernel",
|
||||
.offset = 0x000000,
|
||||
.size = 0x170000,
|
||||
},
|
||||
{
|
||||
.name = "rootfs",
|
||||
.offset = 0x170000,
|
||||
.size = 0x590000,
|
||||
},
|
||||
{
|
||||
.name = "uboot",
|
||||
.offset = 0x700000,
|
||||
.size = 0x040000,
|
||||
},
|
||||
{
|
||||
.name = "config",
|
||||
.offset = 0x740000,
|
||||
.size = 0x0c0000,
|
||||
},
|
||||
};
|
||||
#endif
|
||||
|
||||
|
||||
static __initdata struct of_device_id storcenter_of_bus[] = {
|
||||
{ .name = "soc", },
|
||||
{},
|
||||
|
@ -96,11 +69,6 @@ static void __init storcenter_setup_arch(void)
|
|||
{
|
||||
struct device_node *np;
|
||||
|
||||
#ifdef CONFIG_MTD_PHYSMAP
|
||||
physmap_set_partitions(storcenter_physmap_partitions,
|
||||
ARRAY_SIZE(storcenter_physmap_partitions));
|
||||
#endif
|
||||
|
||||
/* Lookup PCI host bridges */
|
||||
for_each_compatible_node(np, "pci", "mpc10x-pci")
|
||||
storcenter_add_bridge(np);
|
||||
|
|
|
@ -22,6 +22,7 @@
|
|||
#include <linux/gpio.h>
|
||||
#include <linux/spi/spi.h>
|
||||
#include <linux/spi/spi_gpio.h>
|
||||
#include <media/soc_camera.h>
|
||||
#include <media/soc_camera_platform.h>
|
||||
#include <media/sh_mobile_ceu.h>
|
||||
#include <video/sh_mobile_lcdc.h>
|
||||
|
|
|
@ -323,17 +323,25 @@ static void sun4u_set_affinity(unsigned int virt_irq,
|
|||
sun4u_irq_enable(virt_irq);
|
||||
}
|
||||
|
||||
/* Don't do anything. The desc->status check for IRQ_DISABLED in
|
||||
* handler_irq() will skip the handler call and that will leave the
|
||||
* interrupt in the sent state. The next ->enable() call will hit the
|
||||
* ICLR register to reset the state machine.
|
||||
*
|
||||
* This scheme is necessary, instead of clearing the Valid bit in the
|
||||
* IMAP register, to handle the case of IMAP registers being shared by
|
||||
* multiple INOs (and thus ICLR registers). Since we use a different
|
||||
* virtual IRQ for each shared IMAP instance, the generic code thinks
|
||||
* there is only one user so it prematurely calls ->disable() on
|
||||
* free_irq().
|
||||
*
|
||||
* We have to provide an explicit ->disable() method instead of using
|
||||
* NULL to get the default. The reason is that if the generic code
|
||||
* sees that, it also hooks up a default ->shutdown method which
|
||||
* invokes ->mask() which we do not want. See irq_chip_set_defaults().
|
||||
*/
|
||||
static void sun4u_irq_disable(unsigned int virt_irq)
|
||||
{
|
||||
struct irq_handler_data *data = get_irq_chip_data(virt_irq);
|
||||
|
||||
if (likely(data)) {
|
||||
unsigned long imap = data->imap;
|
||||
unsigned long tmp = upa_readq(imap);
|
||||
|
||||
tmp &= ~IMAP_VALID;
|
||||
upa_writeq(tmp, imap);
|
||||
}
|
||||
}
|
||||
|
||||
static void sun4u_irq_eoi(unsigned int virt_irq)
|
||||
|
@ -746,7 +754,8 @@ void handler_irq(int irq, struct pt_regs *regs)
|
|||
|
||||
desc = irq_desc + virt_irq;
|
||||
|
||||
desc->handle_irq(virt_irq, desc);
|
||||
if (!(desc->status & IRQ_DISABLED))
|
||||
desc->handle_irq(virt_irq, desc);
|
||||
|
||||
bucket_pa = next_pa;
|
||||
}
|
||||
|
|
|
@ -64,6 +64,11 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
|
|||
ret = poke_user(child, addr, data);
|
||||
break;
|
||||
|
||||
case PTRACE_SYSEMU:
|
||||
case PTRACE_SYSEMU_SINGLESTEP:
|
||||
ret = -EIO;
|
||||
break;
|
||||
|
||||
/* continue and stop at next (return from) syscall */
|
||||
case PTRACE_SYSCALL:
|
||||
/* restart after signal. */
|
||||
|
|
|
@ -14,7 +14,6 @@
|
|||
#undef memset
|
||||
|
||||
extern size_t strlen(const char *);
|
||||
extern void *memcpy(void *, const void *, size_t);
|
||||
extern void *memmove(void *, const void *, size_t);
|
||||
extern void *memset(void *, int, size_t);
|
||||
extern int printf(const char *, ...);
|
||||
|
@ -24,7 +23,11 @@ extern int printf(const char *, ...);
|
|||
EXPORT_SYMBOL(strstr);
|
||||
#endif
|
||||
|
||||
#ifndef __x86_64__
|
||||
extern void *memcpy(void *, const void *, size_t);
|
||||
EXPORT_SYMBOL(memcpy);
|
||||
#endif
|
||||
|
||||
EXPORT_SYMBOL(memmove);
|
||||
EXPORT_SYMBOL(memset);
|
||||
EXPORT_SYMBOL(printf);
|
||||
|
|
|
@ -451,23 +451,24 @@ static void rcu_free_kmmio_fault_pages(struct rcu_head *head)
|
|||
|
||||
static void remove_kmmio_fault_pages(struct rcu_head *head)
|
||||
{
|
||||
struct kmmio_delayed_release *dr = container_of(
|
||||
head,
|
||||
struct kmmio_delayed_release,
|
||||
rcu);
|
||||
struct kmmio_delayed_release *dr =
|
||||
container_of(head, struct kmmio_delayed_release, rcu);
|
||||
struct kmmio_fault_page *p = dr->release_list;
|
||||
struct kmmio_fault_page **prevp = &dr->release_list;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&kmmio_lock, flags);
|
||||
while (p) {
|
||||
if (!p->count)
|
||||
if (!p->count) {
|
||||
list_del_rcu(&p->list);
|
||||
else
|
||||
prevp = &p->release_next;
|
||||
} else {
|
||||
*prevp = p->release_next;
|
||||
prevp = &p->release_next;
|
||||
}
|
||||
p = p->release_next;
|
||||
}
|
||||
spin_unlock_irqrestore(&kmmio_lock, flags);
|
||||
|
||||
/* This is the real RCU destroy call. */
|
||||
call_rcu(&dr->rcu, rcu_free_kmmio_fault_pages);
|
||||
}
|
||||
|
|
|
@ -515,6 +515,17 @@ static int split_large_page(pte_t *kpte, unsigned long address)
|
|||
* primary protection behavior:
|
||||
*/
|
||||
__set_pmd_pte(kpte, address, mk_pte(base, __pgprot(_KERNPG_TABLE)));
|
||||
|
||||
/*
|
||||
* Intel Atom errata AAH41 workaround.
|
||||
*
|
||||
* The real fix should be in hw or in a microcode update, but
|
||||
* we also probabilistically try to reduce the window of having
|
||||
* a large TLB mixed with 4K TLBs while instruction fetches are
|
||||
* going on.
|
||||
*/
|
||||
__flush_tlb_all();
|
||||
|
||||
base = NULL;
|
||||
|
||||
out_unlock:
|
||||
|
|
|
@ -103,9 +103,6 @@ config MATH_EMULATION
|
|||
help
|
||||
Can we use information of configuration file?
|
||||
|
||||
config HIGHMEM
|
||||
bool "High memory support"
|
||||
|
||||
endmenu
|
||||
|
||||
menu "Platform options"
|
||||
|
|
|
@ -44,6 +44,8 @@
|
|||
#include <asm/setup.h>
|
||||
#include <asm/param.h>
|
||||
|
||||
#include <platform/hardware.h>
|
||||
|
||||
#if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
|
||||
struct screen_info screen_info = { 0, 24, 0, 0, 0, 80, 0, 0, 0, 24, 1, 16};
|
||||
#endif
|
||||
|
|
|
@ -30,6 +30,7 @@
|
|||
#include <linux/stringify.h>
|
||||
#include <linux/kallsyms.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/hardirq.h>
|
||||
|
||||
#include <asm/ptrace.h>
|
||||
#include <asm/timex.h>
|
||||
|
|
|
@ -14,6 +14,7 @@
|
|||
|
||||
#include <linux/mm.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/hardirq.h>
|
||||
#include <asm/mmu_context.h>
|
||||
#include <asm/cacheflush.h>
|
||||
#include <asm/hardirq.h>
|
||||
|
|
|
@ -140,16 +140,14 @@ static void rs_poll(unsigned long priv)
|
|||
}
|
||||
|
||||
|
||||
static void rs_put_char(struct tty_struct *tty, unsigned char ch)
|
||||
static int rs_put_char(struct tty_struct *tty, unsigned char ch)
|
||||
{
|
||||
char buf[2];
|
||||
|
||||
if (!tty)
|
||||
return;
|
||||
|
||||
buf[0] = ch;
|
||||
buf[1] = '\0'; /* Is this NULL necessary? */
|
||||
__simc (SYS_write, 1, (unsigned long) buf, 1, 0, 0);
|
||||
return 1;
|
||||
}
|
||||
|
||||
static void rs_flush_chars(struct tty_struct *tty)
|
||||
|
|
|
@ -30,7 +30,7 @@
|
|||
#ifdef CONFIG_DMA_ENGINE
|
||||
static int __init async_tx_init(void)
|
||||
{
|
||||
dmaengine_get();
|
||||
async_dmaengine_get();
|
||||
|
||||
printk(KERN_INFO "async_tx: api initialized (async)\n");
|
||||
|
||||
|
@ -39,7 +39,7 @@ static int __init async_tx_init(void)
|
|||
|
||||
static void __exit async_tx_exit(void)
|
||||
{
|
||||
dmaengine_put();
|
||||
async_dmaengine_put();
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -56,7 +56,7 @@ __async_tx_find_channel(struct dma_async_tx_descriptor *depend_tx,
|
|||
if (depend_tx &&
|
||||
dma_has_cap(tx_type, depend_tx->chan->device->cap_mask))
|
||||
return depend_tx->chan;
|
||||
return dma_find_channel(tx_type);
|
||||
return async_dma_find_channel(tx_type);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(__async_tx_find_channel);
|
||||
#else
|
||||
|
|
|
@ -30,11 +30,8 @@
|
|||
#include <linux/raid/xor.h>
|
||||
#include <linux/async_tx.h>
|
||||
|
||||
/* do_async_xor - dma map the pages and perform the xor with an engine.
|
||||
* This routine is marked __always_inline so it can be compiled away
|
||||
* when CONFIG_DMA_ENGINE=n
|
||||
*/
|
||||
static __always_inline struct dma_async_tx_descriptor *
|
||||
/* do_async_xor - dma map the pages and perform the xor with an engine */
|
||||
static __async_inline struct dma_async_tx_descriptor *
|
||||
do_async_xor(struct dma_chan *chan, struct page *dest, struct page **src_list,
|
||||
unsigned int offset, int src_cnt, size_t len,
|
||||
enum async_tx_flags flags,
|
||||
|
|
|
@ -303,7 +303,7 @@ int unregister_mem_sect_under_nodes(struct memory_block *mem_blk)
|
|||
sect_start_pfn = section_nr_to_pfn(mem_blk->phys_index);
|
||||
sect_end_pfn = sect_start_pfn + PAGES_PER_SECTION - 1;
|
||||
for (pfn = sect_start_pfn; pfn <= sect_end_pfn; pfn++) {
|
||||
unsigned int nid;
|
||||
int nid;
|
||||
|
||||
nid = get_nid_for_pfn(pfn);
|
||||
if (nid < 0)
|
||||
|
|
|
@ -271,15 +271,15 @@ static __devinit int fix_northbridge(struct pci_dev *nb, struct pci_dev *agp,
|
|||
nb_order = (nb_order >> 1) & 7;
|
||||
pci_read_config_dword(nb, AMD64_GARTAPERTUREBASE, &nb_base);
|
||||
nb_aper = nb_base << 25;
|
||||
if (agp_aperture_valid(nb_aper, (32*1024*1024)<<nb_order)) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Northbridge seems to contain crap. Try the AGP bridge. */
|
||||
|
||||
pci_read_config_word(agp, cap+0x14, &apsize);
|
||||
if (apsize == 0xffff)
|
||||
if (apsize == 0xffff) {
|
||||
if (agp_aperture_valid(nb_aper, (32*1024*1024)<<nb_order))
|
||||
return 0;
|
||||
return -1;
|
||||
}
|
||||
|
||||
apsize &= 0xfff;
|
||||
/* Some BIOS use weird encodings not in the AGPv3 table. */
|
||||
|
@ -301,6 +301,11 @@ static __devinit int fix_northbridge(struct pci_dev *nb, struct pci_dev *agp,
|
|||
order = nb_order;
|
||||
}
|
||||
|
||||
if (nb_order >= order) {
|
||||
if (agp_aperture_valid(nb_aper, (32*1024*1024)<<nb_order))
|
||||
return 0;
|
||||
}
|
||||
|
||||
dev_info(&agp->dev, "aperture from AGP @ %Lx size %u MB\n",
|
||||
aper, 32 << order);
|
||||
if (order < 0 || !agp_aperture_valid(aper, (32*1024*1024)<<order))
|
||||
|
|
|
@ -633,13 +633,15 @@ static void intel_i830_init_gtt_entries(void)
|
|||
break;
|
||||
}
|
||||
}
|
||||
if (gtt_entries > 0)
|
||||
if (gtt_entries > 0) {
|
||||
dev_info(&agp_bridge->dev->dev, "detected %dK %s memory\n",
|
||||
gtt_entries / KB(1), local ? "local" : "stolen");
|
||||
else
|
||||
gtt_entries /= KB(4);
|
||||
} else {
|
||||
dev_info(&agp_bridge->dev->dev,
|
||||
"no pre-allocated video memory detected\n");
|
||||
gtt_entries /= KB(4);
|
||||
gtt_entries = 0;
|
||||
}
|
||||
|
||||
intel_private.gtt_entries = gtt_entries;
|
||||
}
|
||||
|
|
|
@ -1139,15 +1139,6 @@ static int hvcs_open(struct tty_struct *tty, struct file *filp)
|
|||
hvcsd->tty = tty;
|
||||
tty->driver_data = hvcsd;
|
||||
|
||||
/*
|
||||
* Set this driver to low latency so that we actually have a chance at
|
||||
* catching a throttled TTY after we flip_buffer_push. Otherwise the
|
||||
* flush_to_async may not execute until after the kernel_thread has
|
||||
* yielded and resumed the next flip_buffer_push resulting in data
|
||||
* loss.
|
||||
*/
|
||||
tty->low_latency = 1;
|
||||
|
||||
memset(&hvcsd->buffer[0], 0x00, HVCS_BUFF_LEN);
|
||||
|
||||
/*
|
||||
|
|
|
@ -810,7 +810,6 @@ static int hvsi_open(struct tty_struct *tty, struct file *filp)
|
|||
hp = &hvsi_ports[line];
|
||||
|
||||
tty->driver_data = hp;
|
||||
tty->low_latency = 1; /* avoid throttle/tty_flip_buffer_push race */
|
||||
|
||||
mb();
|
||||
if (hp->state == HVSI_FSP_DIED)
|
||||
|
|
|
@ -98,6 +98,17 @@ config NET_DMA
|
|||
Say Y here if you enabled INTEL_IOATDMA or FSL_DMA, otherwise
|
||||
say N.
|
||||
|
||||
config ASYNC_TX_DMA
|
||||
bool "Async_tx: Offload support for the async_tx api"
|
||||
depends on DMA_ENGINE
|
||||
help
|
||||
This allows the async_tx api to take advantage of offload engines for
|
||||
memcpy, memset, xor, and raid6 p+q operations. If your platform has
|
||||
a dma engine that can perform raid operations and you have enabled
|
||||
MD_RAID456 say Y.
|
||||
|
||||
If unsure, say N.
|
||||
|
||||
config DMATEST
|
||||
tristate "DMA Test client"
|
||||
depends on DMA_ENGINE
|
||||
|
|
|
@ -507,6 +507,7 @@ struct dma_chan *__dma_request_channel(dma_cap_mask_t *mask, dma_filter_fn fn, v
|
|||
* published in the general-purpose allocator
|
||||
*/
|
||||
dma_cap_set(DMA_PRIVATE, device->cap_mask);
|
||||
device->privatecnt++;
|
||||
err = dma_chan_get(chan);
|
||||
|
||||
if (err == -ENODEV) {
|
||||
|
@ -518,6 +519,8 @@ struct dma_chan *__dma_request_channel(dma_cap_mask_t *mask, dma_filter_fn fn, v
|
|||
dma_chan_name(chan), err);
|
||||
else
|
||||
break;
|
||||
if (--device->privatecnt == 0)
|
||||
dma_cap_clear(DMA_PRIVATE, device->cap_mask);
|
||||
chan->private = NULL;
|
||||
chan = NULL;
|
||||
}
|
||||
|
@ -537,6 +540,9 @@ void dma_release_channel(struct dma_chan *chan)
|
|||
WARN_ONCE(chan->client_count != 1,
|
||||
"chan reference count %d != 1\n", chan->client_count);
|
||||
dma_chan_put(chan);
|
||||
/* drop PRIVATE cap enabled by __dma_request_channel() */
|
||||
if (--chan->device->privatecnt == 0)
|
||||
dma_cap_clear(DMA_PRIVATE, chan->device->cap_mask);
|
||||
chan->private = NULL;
|
||||
mutex_unlock(&dma_list_mutex);
|
||||
}
|
||||
|
@ -602,6 +608,24 @@ void dmaengine_put(void)
|
|||
}
|
||||
EXPORT_SYMBOL(dmaengine_put);
|
||||
|
||||
static int get_dma_id(struct dma_device *device)
|
||||
{
|
||||
int rc;
|
||||
|
||||
idr_retry:
|
||||
if (!idr_pre_get(&dma_idr, GFP_KERNEL))
|
||||
return -ENOMEM;
|
||||
mutex_lock(&dma_list_mutex);
|
||||
rc = idr_get_new(&dma_idr, NULL, &device->dev_id);
|
||||
mutex_unlock(&dma_list_mutex);
|
||||
if (rc == -EAGAIN)
|
||||
goto idr_retry;
|
||||
else if (rc != 0)
|
||||
return rc;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* dma_async_device_register - registers DMA devices found
|
||||
* @device: &dma_device
|
||||
|
@ -640,27 +664,25 @@ int dma_async_device_register(struct dma_device *device)
|
|||
idr_ref = kmalloc(sizeof(*idr_ref), GFP_KERNEL);
|
||||
if (!idr_ref)
|
||||
return -ENOMEM;
|
||||
atomic_set(idr_ref, 0);
|
||||
idr_retry:
|
||||
if (!idr_pre_get(&dma_idr, GFP_KERNEL))
|
||||
return -ENOMEM;
|
||||
mutex_lock(&dma_list_mutex);
|
||||
rc = idr_get_new(&dma_idr, NULL, &device->dev_id);
|
||||
mutex_unlock(&dma_list_mutex);
|
||||
if (rc == -EAGAIN)
|
||||
goto idr_retry;
|
||||
else if (rc != 0)
|
||||
rc = get_dma_id(device);
|
||||
if (rc != 0) {
|
||||
kfree(idr_ref);
|
||||
return rc;
|
||||
}
|
||||
|
||||
atomic_set(idr_ref, 0);
|
||||
|
||||
/* represent channels in sysfs. Probably want devs too */
|
||||
list_for_each_entry(chan, &device->channels, device_node) {
|
||||
rc = -ENOMEM;
|
||||
chan->local = alloc_percpu(typeof(*chan->local));
|
||||
if (chan->local == NULL)
|
||||
continue;
|
||||
goto err_out;
|
||||
chan->dev = kzalloc(sizeof(*chan->dev), GFP_KERNEL);
|
||||
if (chan->dev == NULL) {
|
||||
free_percpu(chan->local);
|
||||
continue;
|
||||
chan->local = NULL;
|
||||
goto err_out;
|
||||
}
|
||||
|
||||
chan->chan_id = chancnt++;
|
||||
|
@ -677,6 +699,8 @@ int dma_async_device_register(struct dma_device *device)
|
|||
if (rc) {
|
||||
free_percpu(chan->local);
|
||||
chan->local = NULL;
|
||||
kfree(chan->dev);
|
||||
atomic_dec(idr_ref);
|
||||
goto err_out;
|
||||
}
|
||||
chan->client_count = 0;
|
||||
|
@ -701,12 +725,23 @@ int dma_async_device_register(struct dma_device *device)
|
|||
}
|
||||
}
|
||||
list_add_tail_rcu(&device->global_node, &dma_device_list);
|
||||
if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
|
||||
device->privatecnt++; /* Always private */
|
||||
dma_channel_rebalance();
|
||||
mutex_unlock(&dma_list_mutex);
|
||||
|
||||
return 0;
|
||||
|
||||
err_out:
|
||||
/* if we never registered a channel just release the idr */
|
||||
if (atomic_read(idr_ref) == 0) {
|
||||
mutex_lock(&dma_list_mutex);
|
||||
idr_remove(&dma_idr, device->dev_id);
|
||||
mutex_unlock(&dma_list_mutex);
|
||||
kfree(idr_ref);
|
||||
return rc;
|
||||
}
|
||||
|
||||
list_for_each_entry(chan, &device->channels, device_node) {
|
||||
if (chan->local == NULL)
|
||||
continue;
|
||||
|
@ -893,6 +928,7 @@ void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
|
|||
{
|
||||
tx->chan = chan;
|
||||
spin_lock_init(&tx->lock);
|
||||
INIT_LIST_HEAD(&tx->tx_list);
|
||||
}
|
||||
EXPORT_SYMBOL(dma_async_tx_descriptor_init);
|
||||
|
||||
|
|
|
@ -38,6 +38,11 @@ module_param(max_channels, uint, S_IRUGO);
|
|||
MODULE_PARM_DESC(max_channels,
|
||||
"Maximum number of channels to use (default: all)");
|
||||
|
||||
static unsigned int xor_sources = 3;
|
||||
module_param(xor_sources, uint, S_IRUGO);
|
||||
MODULE_PARM_DESC(xor_sources,
|
||||
"Number of xor source buffers (default: 3)");
|
||||
|
||||
/*
|
||||
* Initialization patterns. All bytes in the source buffer has bit 7
|
||||
* set, all bytes in the destination buffer has bit 7 cleared.
|
||||
|
@ -59,8 +64,9 @@ struct dmatest_thread {
|
|||
struct list_head node;
|
||||
struct task_struct *task;
|
||||
struct dma_chan *chan;
|
||||
u8 *srcbuf;
|
||||
u8 *dstbuf;
|
||||
u8 **srcs;
|
||||
u8 **dsts;
|
||||
enum dma_transaction_type type;
|
||||
};
|
||||
|
||||
struct dmatest_chan {
|
||||
|
@ -98,30 +104,37 @@ static unsigned long dmatest_random(void)
|
|||
return buf;
|
||||
}
|
||||
|
||||
static void dmatest_init_srcbuf(u8 *buf, unsigned int start, unsigned int len)
|
||||
static void dmatest_init_srcs(u8 **bufs, unsigned int start, unsigned int len)
|
||||
{
|
||||
unsigned int i;
|
||||
u8 *buf;
|
||||
|
||||
for (i = 0; i < start; i++)
|
||||
buf[i] = PATTERN_SRC | (~i & PATTERN_COUNT_MASK);
|
||||
for ( ; i < start + len; i++)
|
||||
buf[i] = PATTERN_SRC | PATTERN_COPY
|
||||
| (~i & PATTERN_COUNT_MASK);;
|
||||
for ( ; i < test_buf_size; i++)
|
||||
buf[i] = PATTERN_SRC | (~i & PATTERN_COUNT_MASK);
|
||||
for (; (buf = *bufs); bufs++) {
|
||||
for (i = 0; i < start; i++)
|
||||
buf[i] = PATTERN_SRC | (~i & PATTERN_COUNT_MASK);
|
||||
for ( ; i < start + len; i++)
|
||||
buf[i] = PATTERN_SRC | PATTERN_COPY
|
||||
| (~i & PATTERN_COUNT_MASK);;
|
||||
for ( ; i < test_buf_size; i++)
|
||||
buf[i] = PATTERN_SRC | (~i & PATTERN_COUNT_MASK);
|
||||
buf++;
|
||||
}
|
||||
}
|
||||
|
||||
static void dmatest_init_dstbuf(u8 *buf, unsigned int start, unsigned int len)
|
||||
static void dmatest_init_dsts(u8 **bufs, unsigned int start, unsigned int len)
|
||||
{
|
||||
unsigned int i;
|
||||
u8 *buf;
|
||||
|
||||
for (i = 0; i < start; i++)
|
||||
buf[i] = PATTERN_DST | (~i & PATTERN_COUNT_MASK);
|
||||
for ( ; i < start + len; i++)
|
||||
buf[i] = PATTERN_DST | PATTERN_OVERWRITE
|
||||
| (~i & PATTERN_COUNT_MASK);
|
||||
for ( ; i < test_buf_size; i++)
|
||||
buf[i] = PATTERN_DST | (~i & PATTERN_COUNT_MASK);
|
||||
for (; (buf = *bufs); bufs++) {
|
||||
for (i = 0; i < start; i++)
|
||||
buf[i] = PATTERN_DST | (~i & PATTERN_COUNT_MASK);
|
||||
for ( ; i < start + len; i++)
|
||||
buf[i] = PATTERN_DST | PATTERN_OVERWRITE
|
||||
| (~i & PATTERN_COUNT_MASK);
|
||||
for ( ; i < test_buf_size; i++)
|
||||
buf[i] = PATTERN_DST | (~i & PATTERN_COUNT_MASK);
|
||||
}
|
||||
}
|
||||
|
||||
static void dmatest_mismatch(u8 actual, u8 pattern, unsigned int index,
|
||||
|
@ -150,23 +163,30 @@ static void dmatest_mismatch(u8 actual, u8 pattern, unsigned int index,
|
|||
thread_name, index, expected, actual);
|
||||
}
|
||||
|
||||
static unsigned int dmatest_verify(u8 *buf, unsigned int start,
|
||||
static unsigned int dmatest_verify(u8 **bufs, unsigned int start,
|
||||
unsigned int end, unsigned int counter, u8 pattern,
|
||||
bool is_srcbuf)
|
||||
{
|
||||
unsigned int i;
|
||||
unsigned int error_count = 0;
|
||||
u8 actual;
|
||||
u8 expected;
|
||||
u8 *buf;
|
||||
unsigned int counter_orig = counter;
|
||||
|
||||
for (i = start; i < end; i++) {
|
||||
actual = buf[i];
|
||||
if (actual != (pattern | (~counter & PATTERN_COUNT_MASK))) {
|
||||
if (error_count < 32)
|
||||
dmatest_mismatch(actual, pattern, i, counter,
|
||||
is_srcbuf);
|
||||
error_count++;
|
||||
for (; (buf = *bufs); bufs++) {
|
||||
counter = counter_orig;
|
||||
for (i = start; i < end; i++) {
|
||||
actual = buf[i];
|
||||
expected = pattern | (~counter & PATTERN_COUNT_MASK);
|
||||
if (actual != expected) {
|
||||
if (error_count < 32)
|
||||
dmatest_mismatch(actual, pattern, i,
|
||||
counter, is_srcbuf);
|
||||
error_count++;
|
||||
}
|
||||
counter++;
|
||||
}
|
||||
counter++;
|
||||
}
|
||||
|
||||
if (error_count > 32)
|
||||
|
@ -176,12 +196,17 @@ static unsigned int dmatest_verify(u8 *buf, unsigned int start,
|
|||
return error_count;
|
||||
}
|
||||
|
||||
static void dmatest_callback(void *completion)
|
||||
{
|
||||
complete(completion);
|
||||
}
|
||||
|
||||
/*
|
||||
* This function repeatedly tests DMA transfers of various lengths and
|
||||
* offsets until it is told to exit by kthread_stop(). There may be
|
||||
* multiple threads running this function in parallel for a single
|
||||
* channel, and there may be multiple channels being tested in
|
||||
* parallel.
|
||||
* offsets for a given operation type until it is told to exit by
|
||||
* kthread_stop(). There may be multiple threads running this function
|
||||
* in parallel for a single channel, and there may be multiple channels
|
||||
* being tested in parallel.
|
||||
*
|
||||
* Before each test, the source and destination buffer is initialized
|
||||
* with a known pattern. This pattern is different depending on
|
||||
|
@ -201,25 +226,57 @@ static int dmatest_func(void *data)
|
|||
unsigned int total_tests = 0;
|
||||
dma_cookie_t cookie;
|
||||
enum dma_status status;
|
||||
enum dma_ctrl_flags flags;
|
||||
int ret;
|
||||
int src_cnt;
|
||||
int dst_cnt;
|
||||
int i;
|
||||
|
||||
thread_name = current->comm;
|
||||
|
||||
ret = -ENOMEM;
|
||||
thread->srcbuf = kmalloc(test_buf_size, GFP_KERNEL);
|
||||
if (!thread->srcbuf)
|
||||
goto err_srcbuf;
|
||||
thread->dstbuf = kmalloc(test_buf_size, GFP_KERNEL);
|
||||
if (!thread->dstbuf)
|
||||
goto err_dstbuf;
|
||||
|
||||
smp_rmb();
|
||||
chan = thread->chan;
|
||||
if (thread->type == DMA_MEMCPY)
|
||||
src_cnt = dst_cnt = 1;
|
||||
else if (thread->type == DMA_XOR) {
|
||||
src_cnt = xor_sources | 1; /* force odd to ensure dst = src */
|
||||
dst_cnt = 1;
|
||||
} else
|
||||
goto err_srcs;
|
||||
|
||||
thread->srcs = kcalloc(src_cnt+1, sizeof(u8 *), GFP_KERNEL);
|
||||
if (!thread->srcs)
|
||||
goto err_srcs;
|
||||
for (i = 0; i < src_cnt; i++) {
|
||||
thread->srcs[i] = kmalloc(test_buf_size, GFP_KERNEL);
|
||||
if (!thread->srcs[i])
|
||||
goto err_srcbuf;
|
||||
}
|
||||
thread->srcs[i] = NULL;
|
||||
|
||||
thread->dsts = kcalloc(dst_cnt+1, sizeof(u8 *), GFP_KERNEL);
|
||||
if (!thread->dsts)
|
||||
goto err_dsts;
|
||||
for (i = 0; i < dst_cnt; i++) {
|
||||
thread->dsts[i] = kmalloc(test_buf_size, GFP_KERNEL);
|
||||
if (!thread->dsts[i])
|
||||
goto err_dstbuf;
|
||||
}
|
||||
thread->dsts[i] = NULL;
|
||||
|
||||
set_user_nice(current, 10);
|
||||
|
||||
flags = DMA_CTRL_ACK | DMA_COMPL_SKIP_DEST_UNMAP | DMA_PREP_INTERRUPT;
|
||||
|
||||
while (!kthread_should_stop()) {
|
||||
struct dma_device *dev = chan->device;
|
||||
struct dma_async_tx_descriptor *tx;
|
||||
dma_addr_t dma_src, dma_dest;
|
||||
struct dma_async_tx_descriptor *tx = NULL;
|
||||
dma_addr_t dma_srcs[src_cnt];
|
||||
dma_addr_t dma_dsts[dst_cnt];
|
||||
struct completion cmp;
|
||||
unsigned long tmo = msecs_to_jiffies(3000);
|
||||
|
||||
total_tests++;
|
||||
|
||||
|
@ -227,22 +284,41 @@ static int dmatest_func(void *data)
|
|||
src_off = dmatest_random() % (test_buf_size - len + 1);
|
||||
dst_off = dmatest_random() % (test_buf_size - len + 1);
|
||||
|
||||
dmatest_init_srcbuf(thread->srcbuf, src_off, len);
|
||||
dmatest_init_dstbuf(thread->dstbuf, dst_off, len);
|
||||
dmatest_init_srcs(thread->srcs, src_off, len);
|
||||
dmatest_init_dsts(thread->dsts, dst_off, len);
|
||||
|
||||
dma_src = dma_map_single(dev->dev, thread->srcbuf + src_off,
|
||||
len, DMA_TO_DEVICE);
|
||||
for (i = 0; i < src_cnt; i++) {
|
||||
u8 *buf = thread->srcs[i] + src_off;
|
||||
|
||||
dma_srcs[i] = dma_map_single(dev->dev, buf, len,
|
||||
DMA_TO_DEVICE);
|
||||
}
|
||||
/* map with DMA_BIDIRECTIONAL to force writeback/invalidate */
|
||||
dma_dest = dma_map_single(dev->dev, thread->dstbuf,
|
||||
test_buf_size, DMA_BIDIRECTIONAL);
|
||||
for (i = 0; i < dst_cnt; i++) {
|
||||
dma_dsts[i] = dma_map_single(dev->dev, thread->dsts[i],
|
||||
test_buf_size,
|
||||
DMA_BIDIRECTIONAL);
|
||||
}
|
||||
|
||||
if (thread->type == DMA_MEMCPY)
|
||||
tx = dev->device_prep_dma_memcpy(chan,
|
||||
dma_dsts[0] + dst_off,
|
||||
dma_srcs[0], len,
|
||||
flags);
|
||||
else if (thread->type == DMA_XOR)
|
||||
tx = dev->device_prep_dma_xor(chan,
|
||||
dma_dsts[0] + dst_off,
|
||||
dma_srcs, xor_sources,
|
||||
len, flags);
|
||||
|
||||
tx = dev->device_prep_dma_memcpy(chan, dma_dest + dst_off,
|
||||
dma_src, len,
|
||||
DMA_CTRL_ACK | DMA_COMPL_SKIP_DEST_UNMAP);
|
||||
if (!tx) {
|
||||
dma_unmap_single(dev->dev, dma_src, len, DMA_TO_DEVICE);
|
||||
dma_unmap_single(dev->dev, dma_dest,
|
||||
test_buf_size, DMA_BIDIRECTIONAL);
|
||||
for (i = 0; i < src_cnt; i++)
|
||||
dma_unmap_single(dev->dev, dma_srcs[i], len,
|
||||
DMA_TO_DEVICE);
|
||||
for (i = 0; i < dst_cnt; i++)
|
||||
dma_unmap_single(dev->dev, dma_dsts[i],
|
||||
test_buf_size,
|
||||
DMA_BIDIRECTIONAL);
|
||||
pr_warning("%s: #%u: prep error with src_off=0x%x "
|
||||
"dst_off=0x%x len=0x%x\n",
|
||||
thread_name, total_tests - 1,
|
||||
|
@ -251,7 +327,10 @@ static int dmatest_func(void *data)
|
|||
failed_tests++;
|
||||
continue;
|
||||
}
|
||||
tx->callback = NULL;
|
||||
|
||||
init_completion(&cmp);
|
||||
tx->callback = dmatest_callback;
|
||||
tx->callback_param = &cmp;
|
||||
cookie = tx->tx_submit(tx);
|
||||
|
||||
if (dma_submit_error(cookie)) {
|
||||
|
@ -263,44 +342,50 @@ static int dmatest_func(void *data)
|
|||
failed_tests++;
|
||||
continue;
|
||||
}
|
||||
dma_async_memcpy_issue_pending(chan);
|
||||
dma_async_issue_pending(chan);
|
||||
|
||||
do {
|
||||
msleep(1);
|
||||
status = dma_async_memcpy_complete(
|
||||
chan, cookie, NULL, NULL);
|
||||
} while (status == DMA_IN_PROGRESS);
|
||||
tmo = wait_for_completion_timeout(&cmp, tmo);
|
||||
status = dma_async_is_tx_complete(chan, cookie, NULL, NULL);
|
||||
|
||||
if (status == DMA_ERROR) {
|
||||
pr_warning("%s: #%u: error during copy\n",
|
||||
thread_name, total_tests - 1);
|
||||
if (tmo == 0) {
|
||||
pr_warning("%s: #%u: test timed out\n",
|
||||
thread_name, total_tests - 1);
|
||||
failed_tests++;
|
||||
continue;
|
||||
} else if (status != DMA_SUCCESS) {
|
||||
pr_warning("%s: #%u: got completion callback,"
|
||||
" but status is \'%s\'\n",
|
||||
thread_name, total_tests - 1,
|
||||
status == DMA_ERROR ? "error" : "in progress");
|
||||
failed_tests++;
|
||||
continue;
|
||||
}
|
||||
|
||||
/* Unmap by myself (see DMA_COMPL_SKIP_DEST_UNMAP above) */
|
||||
dma_unmap_single(dev->dev, dma_dest,
|
||||
test_buf_size, DMA_BIDIRECTIONAL);
|
||||
for (i = 0; i < dst_cnt; i++)
|
||||
dma_unmap_single(dev->dev, dma_dsts[i], test_buf_size,
|
||||
DMA_BIDIRECTIONAL);
|
||||
|
||||
error_count = 0;
|
||||
|
||||
pr_debug("%s: verifying source buffer...\n", thread_name);
|
||||
error_count += dmatest_verify(thread->srcbuf, 0, src_off,
|
||||
error_count += dmatest_verify(thread->srcs, 0, src_off,
|
||||
0, PATTERN_SRC, true);
|
||||
error_count += dmatest_verify(thread->srcbuf, src_off,
|
||||
error_count += dmatest_verify(thread->srcs, src_off,
|
||||
src_off + len, src_off,
|
||||
PATTERN_SRC | PATTERN_COPY, true);
|
||||
error_count += dmatest_verify(thread->srcbuf, src_off + len,
|
||||
error_count += dmatest_verify(thread->srcs, src_off + len,
|
||||
test_buf_size, src_off + len,
|
||||
PATTERN_SRC, true);
|
||||
|
||||
pr_debug("%s: verifying dest buffer...\n",
|
||||
thread->task->comm);
|
||||
error_count += dmatest_verify(thread->dstbuf, 0, dst_off,
|
||||
error_count += dmatest_verify(thread->dsts, 0, dst_off,
|
||||
0, PATTERN_DST, false);
|
||||
error_count += dmatest_verify(thread->dstbuf, dst_off,
|
||||
error_count += dmatest_verify(thread->dsts, dst_off,
|
||||
dst_off + len, src_off,
|
||||
PATTERN_SRC | PATTERN_COPY, false);
|
||||
error_count += dmatest_verify(thread->dstbuf, dst_off + len,
|
||||
error_count += dmatest_verify(thread->dsts, dst_off + len,
|
||||
test_buf_size, dst_off + len,
|
||||
PATTERN_DST, false);
|
||||
|
||||
|
@ -319,10 +404,16 @@ static int dmatest_func(void *data)
|
|||
}
|
||||
|
||||
ret = 0;
|
||||
kfree(thread->dstbuf);
|
||||
for (i = 0; thread->dsts[i]; i++)
|
||||
kfree(thread->dsts[i]);
|
||||
err_dstbuf:
|
||||
kfree(thread->srcbuf);
|
||||
kfree(thread->dsts);
|
||||
err_dsts:
|
||||
for (i = 0; thread->srcs[i]; i++)
|
||||
kfree(thread->srcs[i]);
|
||||
err_srcbuf:
|
||||
kfree(thread->srcs);
|
||||
err_srcs:
|
||||
pr_notice("%s: terminating after %u tests, %u failures (status %d)\n",
|
||||
thread_name, total_tests, failed_tests, ret);
|
||||
return ret;
|
||||
|
@ -344,11 +435,54 @@ static void dmatest_cleanup_channel(struct dmatest_chan *dtc)
|
|||
kfree(dtc);
|
||||
}
|
||||
|
||||
static int dmatest_add_threads(struct dmatest_chan *dtc, enum dma_transaction_type type)
|
||||
{
|
||||
struct dmatest_thread *thread;
|
||||
struct dma_chan *chan = dtc->chan;
|
||||
char *op;
|
||||
unsigned int i;
|
||||
|
||||
if (type == DMA_MEMCPY)
|
||||
op = "copy";
|
||||
else if (type == DMA_XOR)
|
||||
op = "xor";
|
||||
else
|
||||
return -EINVAL;
|
||||
|
||||
for (i = 0; i < threads_per_chan; i++) {
|
||||
thread = kzalloc(sizeof(struct dmatest_thread), GFP_KERNEL);
|
||||
if (!thread) {
|
||||
pr_warning("dmatest: No memory for %s-%s%u\n",
|
||||
dma_chan_name(chan), op, i);
|
||||
|
||||
break;
|
||||
}
|
||||
thread->chan = dtc->chan;
|
||||
thread->type = type;
|
||||
smp_wmb();
|
||||
thread->task = kthread_run(dmatest_func, thread, "%s-%s%u",
|
||||
dma_chan_name(chan), op, i);
|
||||
if (IS_ERR(thread->task)) {
|
||||
pr_warning("dmatest: Failed to run thread %s-%s%u\n",
|
||||
dma_chan_name(chan), op, i);
|
||||
kfree(thread);
|
||||
break;
|
||||
}
|
||||
|
||||
/* srcbuf and dstbuf are allocated by the thread itself */
|
||||
|
||||
list_add_tail(&thread->node, &dtc->threads);
|
||||
}
|
||||
|
||||
return i;
|
||||
}
|
||||
|
||||
static int dmatest_add_channel(struct dma_chan *chan)
|
||||
{
|
||||
struct dmatest_chan *dtc;
|
||||
struct dmatest_thread *thread;
|
||||
unsigned int i;
|
||||
struct dma_device *dma_dev = chan->device;
|
||||
unsigned int thread_count = 0;
|
||||
unsigned int cnt;
|
||||
|
||||
dtc = kmalloc(sizeof(struct dmatest_chan), GFP_KERNEL);
|
||||
if (!dtc) {
|
||||
|
@ -359,30 +493,17 @@ static int dmatest_add_channel(struct dma_chan *chan)
|
|||
dtc->chan = chan;
|
||||
INIT_LIST_HEAD(&dtc->threads);
|
||||
|
||||
for (i = 0; i < threads_per_chan; i++) {
|
||||
thread = kzalloc(sizeof(struct dmatest_thread), GFP_KERNEL);
|
||||
if (!thread) {
|
||||
pr_warning("dmatest: No memory for %s-test%u\n",
|
||||
dma_chan_name(chan), i);
|
||||
break;
|
||||
}
|
||||
thread->chan = dtc->chan;
|
||||
smp_wmb();
|
||||
thread->task = kthread_run(dmatest_func, thread, "%s-test%u",
|
||||
dma_chan_name(chan), i);
|
||||
if (IS_ERR(thread->task)) {
|
||||
pr_warning("dmatest: Failed to run thread %s-test%u\n",
|
||||
dma_chan_name(chan), i);
|
||||
kfree(thread);
|
||||
break;
|
||||
}
|
||||
|
||||
/* srcbuf and dstbuf are allocated by the thread itself */
|
||||
|
||||
list_add_tail(&thread->node, &dtc->threads);
|
||||
if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) {
|
||||
cnt = dmatest_add_threads(dtc, DMA_MEMCPY);
|
||||
thread_count += cnt > 0 ?: 0;
|
||||
}
|
||||
if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
|
||||
cnt = dmatest_add_threads(dtc, DMA_XOR);
|
||||
thread_count += cnt > 0 ?: 0;
|
||||
}
|
||||
|
||||
pr_info("dmatest: Started %u threads using %s\n", i, dma_chan_name(chan));
|
||||
pr_info("dmatest: Started %u threads using %s\n",
|
||||
thread_count, dma_chan_name(chan));
|
||||
|
||||
list_add_tail(&dtc->node, &dmatest_channels);
|
||||
nr_channels++;
|
||||
|
|
|
@ -363,6 +363,82 @@ static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc)
|
|||
dwc_descriptor_complete(dwc, bad_desc);
|
||||
}
|
||||
|
||||
/* --------------------- Cyclic DMA API extensions -------------------- */
|
||||
|
||||
inline dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan)
|
||||
{
|
||||
struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
|
||||
return channel_readl(dwc, SAR);
|
||||
}
|
||||
EXPORT_SYMBOL(dw_dma_get_src_addr);
|
||||
|
||||
inline dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan)
|
||||
{
|
||||
struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
|
||||
return channel_readl(dwc, DAR);
|
||||
}
|
||||
EXPORT_SYMBOL(dw_dma_get_dst_addr);
|
||||
|
||||
/* called with dwc->lock held and all DMAC interrupts disabled */
|
||||
static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc,
|
||||
u32 status_block, u32 status_err, u32 status_xfer)
|
||||
{
|
||||
if (status_block & dwc->mask) {
|
||||
void (*callback)(void *param);
|
||||
void *callback_param;
|
||||
|
||||
dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n",
|
||||
channel_readl(dwc, LLP));
|
||||
dma_writel(dw, CLEAR.BLOCK, dwc->mask);
|
||||
|
||||
callback = dwc->cdesc->period_callback;
|
||||
callback_param = dwc->cdesc->period_callback_param;
|
||||
if (callback) {
|
||||
spin_unlock(&dwc->lock);
|
||||
callback(callback_param);
|
||||
spin_lock(&dwc->lock);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Error and transfer complete are highly unlikely, and will most
|
||||
* likely be due to a configuration error by the user.
|
||||
*/
|
||||
if (unlikely(status_err & dwc->mask) ||
|
||||
unlikely(status_xfer & dwc->mask)) {
|
||||
int i;
|
||||
|
||||
dev_err(chan2dev(&dwc->chan), "cyclic DMA unexpected %s "
|
||||
"interrupt, stopping DMA transfer\n",
|
||||
status_xfer ? "xfer" : "error");
|
||||
dev_err(chan2dev(&dwc->chan),
|
||||
" SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
|
||||
channel_readl(dwc, SAR),
|
||||
channel_readl(dwc, DAR),
|
||||
channel_readl(dwc, LLP),
|
||||
channel_readl(dwc, CTL_HI),
|
||||
channel_readl(dwc, CTL_LO));
|
||||
|
||||
channel_clear_bit(dw, CH_EN, dwc->mask);
|
||||
while (dma_readl(dw, CH_EN) & dwc->mask)
|
||||
cpu_relax();
|
||||
|
||||
/* make sure DMA does not restart by loading a new list */
|
||||
channel_writel(dwc, LLP, 0);
|
||||
channel_writel(dwc, CTL_LO, 0);
|
||||
channel_writel(dwc, CTL_HI, 0);
|
||||
|
||||
dma_writel(dw, CLEAR.BLOCK, dwc->mask);
|
||||
dma_writel(dw, CLEAR.ERROR, dwc->mask);
|
||||
dma_writel(dw, CLEAR.XFER, dwc->mask);
|
||||
|
||||
for (i = 0; i < dwc->cdesc->periods; i++)
|
||||
dwc_dump_lli(dwc, &dwc->cdesc->desc[i]->lli);
|
||||
}
|
||||
}
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
static void dw_dma_tasklet(unsigned long data)
|
||||
{
|
||||
struct dw_dma *dw = (struct dw_dma *)data;
|
||||
|
@ -382,7 +458,10 @@ static void dw_dma_tasklet(unsigned long data)
|
|||
for (i = 0; i < dw->dma.chancnt; i++) {
|
||||
dwc = &dw->chan[i];
|
||||
spin_lock(&dwc->lock);
|
||||
if (status_err & (1 << i))
|
||||
if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags))
|
||||
dwc_handle_cyclic(dw, dwc, status_block, status_err,
|
||||
status_xfer);
|
||||
else if (status_err & (1 << i))
|
||||
dwc_handle_error(dw, dwc);
|
||||
else if ((status_block | status_xfer) & (1 << i))
|
||||
dwc_scan_descriptors(dw, dwc);
|
||||
|
@ -826,7 +905,6 @@ static int dwc_alloc_chan_resources(struct dma_chan *chan)
|
|||
dma_async_tx_descriptor_init(&desc->txd, chan);
|
||||
desc->txd.tx_submit = dwc_tx_submit;
|
||||
desc->txd.flags = DMA_CTRL_ACK;
|
||||
INIT_LIST_HEAD(&desc->txd.tx_list);
|
||||
desc->txd.phys = dma_map_single(chan2parent(chan), &desc->lli,
|
||||
sizeof(desc->lli), DMA_TO_DEVICE);
|
||||
dwc_desc_put(dwc, desc);
|
||||
|
@ -884,6 +962,257 @@ static void dwc_free_chan_resources(struct dma_chan *chan)
|
|||
dev_vdbg(chan2dev(chan), "free_chan_resources done\n");
|
||||
}
|
||||
|
||||
/* --------------------- Cyclic DMA API extensions -------------------- */
|
||||
|
||||
/**
|
||||
* dw_dma_cyclic_start - start the cyclic DMA transfer
|
||||
* @chan: the DMA channel to start
|
||||
*
|
||||
* Must be called with soft interrupts disabled. Returns zero on success or
|
||||
* -errno on failure.
|
||||
*/
|
||||
int dw_dma_cyclic_start(struct dma_chan *chan)
|
||||
{
|
||||
struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
|
||||
struct dw_dma *dw = to_dw_dma(dwc->chan.device);
|
||||
|
||||
if (!test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) {
|
||||
dev_err(chan2dev(&dwc->chan), "missing prep for cyclic DMA\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
spin_lock(&dwc->lock);
|
||||
|
||||
/* assert channel is idle */
|
||||
if (dma_readl(dw, CH_EN) & dwc->mask) {
|
||||
dev_err(chan2dev(&dwc->chan),
|
||||
"BUG: Attempted to start non-idle channel\n");
|
||||
dev_err(chan2dev(&dwc->chan),
|
||||
" SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
|
||||
channel_readl(dwc, SAR),
|
||||
channel_readl(dwc, DAR),
|
||||
channel_readl(dwc, LLP),
|
||||
channel_readl(dwc, CTL_HI),
|
||||
channel_readl(dwc, CTL_LO));
|
||||
spin_unlock(&dwc->lock);
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
dma_writel(dw, CLEAR.BLOCK, dwc->mask);
|
||||
dma_writel(dw, CLEAR.ERROR, dwc->mask);
|
||||
dma_writel(dw, CLEAR.XFER, dwc->mask);
|
||||
|
||||
/* setup DMAC channel registers */
|
||||
channel_writel(dwc, LLP, dwc->cdesc->desc[0]->txd.phys);
|
||||
channel_writel(dwc, CTL_LO, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
|
||||
channel_writel(dwc, CTL_HI, 0);
|
||||
|
||||
channel_set_bit(dw, CH_EN, dwc->mask);
|
||||
|
||||
spin_unlock(&dwc->lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(dw_dma_cyclic_start);
|
||||
|
||||
/**
|
||||
* dw_dma_cyclic_stop - stop the cyclic DMA transfer
|
||||
* @chan: the DMA channel to stop
|
||||
*
|
||||
* Must be called with soft interrupts disabled.
|
||||
*/
|
||||
void dw_dma_cyclic_stop(struct dma_chan *chan)
|
||||
{
|
||||
struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
|
||||
struct dw_dma *dw = to_dw_dma(dwc->chan.device);
|
||||
|
||||
spin_lock(&dwc->lock);
|
||||
|
||||
channel_clear_bit(dw, CH_EN, dwc->mask);
|
||||
while (dma_readl(dw, CH_EN) & dwc->mask)
|
||||
cpu_relax();
|
||||
|
||||
spin_unlock(&dwc->lock);
|
||||
}
|
||||
EXPORT_SYMBOL(dw_dma_cyclic_stop);
|
||||
|
||||
/**
|
||||
* dw_dma_cyclic_prep - prepare the cyclic DMA transfer
|
||||
* @chan: the DMA channel to prepare
|
||||
* @buf_addr: physical DMA address where the buffer starts
|
||||
* @buf_len: total number of bytes for the entire buffer
|
||||
* @period_len: number of bytes for each period
|
||||
* @direction: transfer direction, to or from device
|
||||
*
|
||||
* Must be called before trying to start the transfer. Returns a valid struct
|
||||
* dw_cyclic_desc if successful or an ERR_PTR(-errno) if not successful.
|
||||
*/
|
||||
struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
|
||||
dma_addr_t buf_addr, size_t buf_len, size_t period_len,
|
||||
enum dma_data_direction direction)
|
||||
{
|
||||
struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
|
||||
struct dw_cyclic_desc *cdesc;
|
||||
struct dw_cyclic_desc *retval = NULL;
|
||||
struct dw_desc *desc;
|
||||
struct dw_desc *last = NULL;
|
||||
struct dw_dma_slave *dws = chan->private;
|
||||
unsigned long was_cyclic;
|
||||
unsigned int reg_width;
|
||||
unsigned int periods;
|
||||
unsigned int i;
|
||||
|
||||
spin_lock_bh(&dwc->lock);
|
||||
if (!list_empty(&dwc->queue) || !list_empty(&dwc->active_list)) {
|
||||
spin_unlock_bh(&dwc->lock);
|
||||
dev_dbg(chan2dev(&dwc->chan),
|
||||
"queue and/or active list are not empty\n");
|
||||
return ERR_PTR(-EBUSY);
|
||||
}
|
||||
|
||||
was_cyclic = test_and_set_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
|
||||
spin_unlock_bh(&dwc->lock);
|
||||
if (was_cyclic) {
|
||||
dev_dbg(chan2dev(&dwc->chan),
|
||||
"channel already prepared for cyclic DMA\n");
|
||||
return ERR_PTR(-EBUSY);
|
||||
}
|
||||
|
||||
retval = ERR_PTR(-EINVAL);
|
||||
reg_width = dws->reg_width;
|
||||
periods = buf_len / period_len;
|
||||
|
||||
/* Check for too big/unaligned periods and unaligned DMA buffer. */
|
||||
if (period_len > (DWC_MAX_COUNT << reg_width))
|
||||
goto out_err;
|
||||
if (unlikely(period_len & ((1 << reg_width) - 1)))
|
||||
goto out_err;
|
||||
if (unlikely(buf_addr & ((1 << reg_width) - 1)))
|
||||
goto out_err;
|
||||
if (unlikely(!(direction & (DMA_TO_DEVICE | DMA_FROM_DEVICE))))
|
||||
goto out_err;
|
||||
|
||||
retval = ERR_PTR(-ENOMEM);
|
||||
|
||||
if (periods > NR_DESCS_PER_CHANNEL)
|
||||
goto out_err;
|
||||
|
||||
cdesc = kzalloc(sizeof(struct dw_cyclic_desc), GFP_KERNEL);
|
||||
if (!cdesc)
|
||||
goto out_err;
|
||||
|
||||
cdesc->desc = kzalloc(sizeof(struct dw_desc *) * periods, GFP_KERNEL);
|
||||
if (!cdesc->desc)
|
||||
goto out_err_alloc;
|
||||
|
||||
for (i = 0; i < periods; i++) {
|
||||
desc = dwc_desc_get(dwc);
|
||||
if (!desc)
|
||||
goto out_err_desc_get;
|
||||
|
||||
switch (direction) {
|
||||
case DMA_TO_DEVICE:
|
||||
desc->lli.dar = dws->tx_reg;
|
||||
desc->lli.sar = buf_addr + (period_len * i);
|
||||
desc->lli.ctllo = (DWC_DEFAULT_CTLLO
|
||||
| DWC_CTLL_DST_WIDTH(reg_width)
|
||||
| DWC_CTLL_SRC_WIDTH(reg_width)
|
||||
| DWC_CTLL_DST_FIX
|
||||
| DWC_CTLL_SRC_INC
|
||||
| DWC_CTLL_FC_M2P
|
||||
| DWC_CTLL_INT_EN);
|
||||
break;
|
||||
case DMA_FROM_DEVICE:
|
||||
desc->lli.dar = buf_addr + (period_len * i);
|
||||
desc->lli.sar = dws->rx_reg;
|
||||
desc->lli.ctllo = (DWC_DEFAULT_CTLLO
|
||||
| DWC_CTLL_SRC_WIDTH(reg_width)
|
||||
| DWC_CTLL_DST_WIDTH(reg_width)
|
||||
| DWC_CTLL_DST_INC
|
||||
| DWC_CTLL_SRC_FIX
|
||||
| DWC_CTLL_FC_P2M
|
||||
| DWC_CTLL_INT_EN);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
desc->lli.ctlhi = (period_len >> reg_width);
|
||||
cdesc->desc[i] = desc;
|
||||
|
||||
if (last) {
|
||||
last->lli.llp = desc->txd.phys;
|
||||
dma_sync_single_for_device(chan2parent(chan),
|
||||
last->txd.phys, sizeof(last->lli),
|
||||
DMA_TO_DEVICE);
|
||||
}
|
||||
|
||||
last = desc;
|
||||
}
|
||||
|
||||
/* lets make a cyclic list */
|
||||
last->lli.llp = cdesc->desc[0]->txd.phys;
|
||||
dma_sync_single_for_device(chan2parent(chan), last->txd.phys,
|
||||
sizeof(last->lli), DMA_TO_DEVICE);
|
||||
|
||||
dev_dbg(chan2dev(&dwc->chan), "cyclic prepared buf 0x%08x len %zu "
|
||||
"period %zu periods %d\n", buf_addr, buf_len,
|
||||
period_len, periods);
|
||||
|
||||
cdesc->periods = periods;
|
||||
dwc->cdesc = cdesc;
|
||||
|
||||
return cdesc;
|
||||
|
||||
out_err_desc_get:
|
||||
while (i--)
|
||||
dwc_desc_put(dwc, cdesc->desc[i]);
|
||||
out_err_alloc:
|
||||
kfree(cdesc);
|
||||
out_err:
|
||||
clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
|
||||
return (struct dw_cyclic_desc *)retval;
|
||||
}
|
||||
EXPORT_SYMBOL(dw_dma_cyclic_prep);
|
||||
|
||||
/**
|
||||
* dw_dma_cyclic_free - free a prepared cyclic DMA transfer
|
||||
* @chan: the DMA channel to free
|
||||
*/
|
||||
void dw_dma_cyclic_free(struct dma_chan *chan)
|
||||
{
|
||||
struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
|
||||
struct dw_dma *dw = to_dw_dma(dwc->chan.device);
|
||||
struct dw_cyclic_desc *cdesc = dwc->cdesc;
|
||||
int i;
|
||||
|
||||
dev_dbg(chan2dev(&dwc->chan), "cyclic free\n");
|
||||
|
||||
if (!cdesc)
|
||||
return;
|
||||
|
||||
spin_lock_bh(&dwc->lock);
|
||||
|
||||
channel_clear_bit(dw, CH_EN, dwc->mask);
|
||||
while (dma_readl(dw, CH_EN) & dwc->mask)
|
||||
cpu_relax();
|
||||
|
||||
dma_writel(dw, CLEAR.BLOCK, dwc->mask);
|
||||
dma_writel(dw, CLEAR.ERROR, dwc->mask);
|
||||
dma_writel(dw, CLEAR.XFER, dwc->mask);
|
||||
|
||||
spin_unlock_bh(&dwc->lock);
|
||||
|
||||
for (i = 0; i < cdesc->periods; i++)
|
||||
dwc_desc_put(dwc, cdesc->desc[i]);
|
||||
|
||||
kfree(cdesc->desc);
|
||||
kfree(cdesc);
|
||||
|
||||
clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
|
||||
}
|
||||
EXPORT_SYMBOL(dw_dma_cyclic_free);
|
||||
|
||||
/*----------------------------------------------------------------------*/
|
||||
|
||||
static void dw_dma_off(struct dw_dma *dw)
|
||||
|
|
|
@ -126,6 +126,10 @@ struct dw_dma_regs {
|
|||
|
||||
#define DW_REGLEN 0x400
|
||||
|
||||
enum dw_dmac_flags {
|
||||
DW_DMA_IS_CYCLIC = 0,
|
||||
};
|
||||
|
||||
struct dw_dma_chan {
|
||||
struct dma_chan chan;
|
||||
void __iomem *ch_regs;
|
||||
|
@ -134,10 +138,12 @@ struct dw_dma_chan {
|
|||
spinlock_t lock;
|
||||
|
||||
/* these other elements are all protected by lock */
|
||||
unsigned long flags;
|
||||
dma_cookie_t completed;
|
||||
struct list_head active_list;
|
||||
struct list_head queue;
|
||||
struct list_head free_list;
|
||||
struct dw_cyclic_desc *cdesc;
|
||||
|
||||
unsigned int descs_allocated;
|
||||
};
|
||||
|
@ -158,7 +164,6 @@ static inline struct dw_dma_chan *to_dw_dma_chan(struct dma_chan *chan)
|
|||
return container_of(chan, struct dw_dma_chan, chan);
|
||||
}
|
||||
|
||||
|
||||
struct dw_dma {
|
||||
struct dma_device dma;
|
||||
void __iomem *regs;
|
||||
|
|
|
@ -354,7 +354,6 @@ static struct fsl_desc_sw *fsl_dma_alloc_descriptor(
|
|||
dma_async_tx_descriptor_init(&desc_sw->async_tx,
|
||||
&fsl_chan->common);
|
||||
desc_sw->async_tx.tx_submit = fsl_dma_tx_submit;
|
||||
INIT_LIST_HEAD(&desc_sw->async_tx.tx_list);
|
||||
desc_sw->async_tx.phys = pdesc;
|
||||
}
|
||||
|
||||
|
|
|
@ -693,7 +693,6 @@ static struct ioat_desc_sw *ioat_dma_alloc_descriptor(
|
|||
desc_sw->async_tx.tx_submit = ioat2_tx_submit;
|
||||
break;
|
||||
}
|
||||
INIT_LIST_HEAD(&desc_sw->async_tx.tx_list);
|
||||
|
||||
desc_sw->hw = desc;
|
||||
desc_sw->async_tx.phys = phys;
|
||||
|
|
|
@ -498,7 +498,6 @@ static int iop_adma_alloc_chan_resources(struct dma_chan *chan)
|
|||
slot->async_tx.tx_submit = iop_adma_tx_submit;
|
||||
INIT_LIST_HEAD(&slot->chain_node);
|
||||
INIT_LIST_HEAD(&slot->slot_node);
|
||||
INIT_LIST_HEAD(&slot->async_tx.tx_list);
|
||||
hw_desc = (char *) iop_chan->device->dma_desc_pool;
|
||||
slot->async_tx.phys =
|
||||
(dma_addr_t) &hw_desc[idx * IOP_ADMA_SLOT_SIZE];
|
||||
|
|
|
@ -28,6 +28,9 @@
|
|||
#define FS_VF_IN_VALID 0x00000002
|
||||
#define FS_ENC_IN_VALID 0x00000001
|
||||
|
||||
static int ipu_disable_channel(struct idmac *idmac, struct idmac_channel *ichan,
|
||||
bool wait_for_stop);
|
||||
|
||||
/*
|
||||
* There can be only one, we could allocate it dynamically, but then we'd have
|
||||
* to add an extra parameter to some functions, and use something as ugly as
|
||||
|
@ -107,7 +110,7 @@ static uint32_t bytes_per_pixel(enum pixel_fmt fmt)
|
|||
}
|
||||
}
|
||||
|
||||
/* Enable / disable direct write to memory by the Camera Sensor Interface */
|
||||
/* Enable direct write to memory by the Camera Sensor Interface */
|
||||
static void ipu_ic_enable_task(struct ipu *ipu, enum ipu_channel channel)
|
||||
{
|
||||
uint32_t ic_conf, mask;
|
||||
|
@ -126,6 +129,7 @@ static void ipu_ic_enable_task(struct ipu *ipu, enum ipu_channel channel)
|
|||
idmac_write_icreg(ipu, ic_conf, IC_CONF);
|
||||
}
|
||||
|
||||
/* Called under spin_lock_irqsave(&ipu_data.lock) */
|
||||
static void ipu_ic_disable_task(struct ipu *ipu, enum ipu_channel channel)
|
||||
{
|
||||
uint32_t ic_conf, mask;
|
||||
|
@ -422,7 +426,7 @@ static void ipu_ch_param_set_size(union chan_param_mem *params,
|
|||
break;
|
||||
default:
|
||||
dev_err(ipu_data.dev,
|
||||
"mxc ipu: unimplemented pixel format %d\n", pixel_fmt);
|
||||
"mx3 ipu: unimplemented pixel format %d\n", pixel_fmt);
|
||||
break;
|
||||
}
|
||||
|
||||
|
@ -433,20 +437,20 @@ static void ipu_ch_param_set_burst_size(union chan_param_mem *params,
|
|||
uint16_t burst_pixels)
|
||||
{
|
||||
params->pp.npb = burst_pixels - 1;
|
||||
};
|
||||
}
|
||||
|
||||
static void ipu_ch_param_set_buffer(union chan_param_mem *params,
|
||||
dma_addr_t buf0, dma_addr_t buf1)
|
||||
{
|
||||
params->pp.eba0 = buf0;
|
||||
params->pp.eba1 = buf1;
|
||||
};
|
||||
}
|
||||
|
||||
static void ipu_ch_param_set_rotation(union chan_param_mem *params,
|
||||
enum ipu_rotate_mode rotate)
|
||||
{
|
||||
params->pp.bam = rotate;
|
||||
};
|
||||
}
|
||||
|
||||
static void ipu_write_param_mem(uint32_t addr, uint32_t *data,
|
||||
uint32_t num_words)
|
||||
|
@ -571,7 +575,7 @@ static uint32_t dma_param_addr(uint32_t dma_ch)
|
|||
{
|
||||
/* Channel Parameter Memory */
|
||||
return 0x10000 | (dma_ch << 4);
|
||||
};
|
||||
}
|
||||
|
||||
static void ipu_channel_set_priority(struct ipu *ipu, enum ipu_channel channel,
|
||||
bool prio)
|
||||
|
@ -611,7 +615,8 @@ static uint32_t ipu_channel_conf_mask(enum ipu_channel channel)
|
|||
|
||||
/**
|
||||
* ipu_enable_channel() - enable an IPU channel.
|
||||
* @channel: channel ID.
|
||||
* @idmac: IPU DMAC context.
|
||||
* @ichan: IDMAC channel.
|
||||
* @return: 0 on success or negative error code on failure.
|
||||
*/
|
||||
static int ipu_enable_channel(struct idmac *idmac, struct idmac_channel *ichan)
|
||||
|
@ -649,7 +654,7 @@ static int ipu_enable_channel(struct idmac *idmac, struct idmac_channel *ichan)
|
|||
|
||||
/**
|
||||
* ipu_init_channel_buffer() - initialize a buffer for logical IPU channel.
|
||||
* @channel: channel ID.
|
||||
* @ichan: IDMAC channel.
|
||||
* @pixel_fmt: pixel format of buffer. Pixel format is a FOURCC ASCII code.
|
||||
* @width: width of buffer in pixels.
|
||||
* @height: height of buffer in pixels.
|
||||
|
@ -687,7 +692,7 @@ static int ipu_init_channel_buffer(struct idmac_channel *ichan,
|
|||
}
|
||||
|
||||
/* IC channel's stride must be a multiple of 8 pixels */
|
||||
if ((channel <= 13) && (stride % 8)) {
|
||||
if ((channel <= IDMAC_IC_13) && (stride % 8)) {
|
||||
dev_err(ipu->dev, "Stride must be 8 pixel multiple\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
@ -752,7 +757,7 @@ static void ipu_select_buffer(enum ipu_channel channel, int buffer_n)
|
|||
|
||||
/**
|
||||
* ipu_update_channel_buffer() - update physical address of a channel buffer.
|
||||
* @channel: channel ID.
|
||||
* @ichan: IDMAC channel.
|
||||
* @buffer_n: buffer number to update.
|
||||
* 0 or 1 are the only valid values.
|
||||
* @phyaddr: buffer physical address.
|
||||
|
@ -760,9 +765,10 @@ static void ipu_select_buffer(enum ipu_channel channel, int buffer_n)
|
|||
* function will fail if the buffer is set to ready.
|
||||
*/
|
||||
/* Called under spin_lock(_irqsave)(&ichan->lock) */
|
||||
static int ipu_update_channel_buffer(enum ipu_channel channel,
|
||||
static int ipu_update_channel_buffer(struct idmac_channel *ichan,
|
||||
int buffer_n, dma_addr_t phyaddr)
|
||||
{
|
||||
enum ipu_channel channel = ichan->dma_chan.chan_id;
|
||||
uint32_t reg;
|
||||
unsigned long flags;
|
||||
|
||||
|
@ -771,8 +777,8 @@ static int ipu_update_channel_buffer(enum ipu_channel channel,
|
|||
if (buffer_n == 0) {
|
||||
reg = idmac_read_ipureg(&ipu_data, IPU_CHA_BUF0_RDY);
|
||||
if (reg & (1UL << channel)) {
|
||||
spin_unlock_irqrestore(&ipu_data.lock, flags);
|
||||
return -EACCES;
|
||||
ipu_ic_disable_task(&ipu_data, channel);
|
||||
ichan->status = IPU_CHANNEL_READY;
|
||||
}
|
||||
|
||||
/* 44.3.3.1.9 - Row Number 1 (WORD1, offset 0) */
|
||||
|
@ -782,8 +788,8 @@ static int ipu_update_channel_buffer(enum ipu_channel channel,
|
|||
} else {
|
||||
reg = idmac_read_ipureg(&ipu_data, IPU_CHA_BUF1_RDY);
|
||||
if (reg & (1UL << channel)) {
|
||||
spin_unlock_irqrestore(&ipu_data.lock, flags);
|
||||
return -EACCES;
|
||||
ipu_ic_disable_task(&ipu_data, channel);
|
||||
ichan->status = IPU_CHANNEL_READY;
|
||||
}
|
||||
|
||||
/* Check if double-buffering is already enabled */
|
||||
|
@ -804,6 +810,39 @@ static int ipu_update_channel_buffer(enum ipu_channel channel,
|
|||
return 0;
|
||||
}
|
||||
|
||||
/* Called under spin_lock_irqsave(&ichan->lock) */
|
||||
static int ipu_submit_buffer(struct idmac_channel *ichan,
|
||||
struct idmac_tx_desc *desc, struct scatterlist *sg, int buf_idx)
|
||||
{
|
||||
unsigned int chan_id = ichan->dma_chan.chan_id;
|
||||
struct device *dev = &ichan->dma_chan.dev->device;
|
||||
int ret;
|
||||
|
||||
if (async_tx_test_ack(&desc->txd))
|
||||
return -EINTR;
|
||||
|
||||
/*
|
||||
* On first invocation this shouldn't be necessary, the call to
|
||||
* ipu_init_channel_buffer() above will set addresses for us, so we
|
||||
* could make it conditional on status >= IPU_CHANNEL_ENABLED, but
|
||||
* doing it again shouldn't hurt either.
|
||||
*/
|
||||
ret = ipu_update_channel_buffer(ichan, buf_idx,
|
||||
sg_dma_address(sg));
|
||||
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "Updating sg %p on channel 0x%x buffer %d failed!\n",
|
||||
sg, chan_id, buf_idx);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ipu_select_buffer(chan_id, buf_idx);
|
||||
dev_dbg(dev, "Updated sg %p on channel 0x%x buffer %d\n",
|
||||
sg, chan_id, buf_idx);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Called under spin_lock_irqsave(&ichan->lock) */
|
||||
static int ipu_submit_channel_buffers(struct idmac_channel *ichan,
|
||||
struct idmac_tx_desc *desc)
|
||||
|
@ -815,20 +854,10 @@ static int ipu_submit_channel_buffers(struct idmac_channel *ichan,
|
|||
if (!ichan->sg[i]) {
|
||||
ichan->sg[i] = sg;
|
||||
|
||||
/*
|
||||
* On first invocation this shouldn't be necessary, the
|
||||
* call to ipu_init_channel_buffer() above will set
|
||||
* addresses for us, so we could make it conditional
|
||||
* on status >= IPU_CHANNEL_ENABLED, but doing it again
|
||||
* shouldn't hurt either.
|
||||
*/
|
||||
ret = ipu_update_channel_buffer(ichan->dma_chan.chan_id, i,
|
||||
sg_dma_address(sg));
|
||||
ret = ipu_submit_buffer(ichan, desc, sg, i);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
ipu_select_buffer(ichan->dma_chan.chan_id, i);
|
||||
|
||||
sg = sg_next(sg);
|
||||
}
|
||||
}
|
||||
|
@ -842,19 +871,22 @@ static dma_cookie_t idmac_tx_submit(struct dma_async_tx_descriptor *tx)
|
|||
struct idmac_channel *ichan = to_idmac_chan(tx->chan);
|
||||
struct idmac *idmac = to_idmac(tx->chan->device);
|
||||
struct ipu *ipu = to_ipu(idmac);
|
||||
struct device *dev = &ichan->dma_chan.dev->device;
|
||||
dma_cookie_t cookie;
|
||||
unsigned long flags;
|
||||
int ret;
|
||||
|
||||
/* Sanity check */
|
||||
if (!list_empty(&desc->list)) {
|
||||
/* The descriptor doesn't belong to client */
|
||||
dev_err(&ichan->dma_chan.dev->device,
|
||||
"Descriptor %p not prepared!\n", tx);
|
||||
dev_err(dev, "Descriptor %p not prepared!\n", tx);
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
mutex_lock(&ichan->chan_mutex);
|
||||
|
||||
async_tx_clear_ack(tx);
|
||||
|
||||
if (ichan->status < IPU_CHANNEL_READY) {
|
||||
struct idmac_video_param *video = &ichan->params.video;
|
||||
/*
|
||||
|
@ -878,16 +910,7 @@ static dma_cookie_t idmac_tx_submit(struct dma_async_tx_descriptor *tx)
|
|||
goto out;
|
||||
}
|
||||
|
||||
/* ipu->lock can be taken under ichan->lock, but not v.v. */
|
||||
spin_lock_irqsave(&ichan->lock, flags);
|
||||
|
||||
/* submit_buffers() atomically verifies and fills empty sg slots */
|
||||
cookie = ipu_submit_channel_buffers(ichan, desc);
|
||||
|
||||
spin_unlock_irqrestore(&ichan->lock, flags);
|
||||
|
||||
if (cookie < 0)
|
||||
goto out;
|
||||
dev_dbg(dev, "Submitting sg %p\n", &desc->sg[0]);
|
||||
|
||||
cookie = ichan->dma_chan.cookie;
|
||||
|
||||
|
@ -897,24 +920,40 @@ static dma_cookie_t idmac_tx_submit(struct dma_async_tx_descriptor *tx)
|
|||
/* from dmaengine.h: "last cookie value returned to client" */
|
||||
ichan->dma_chan.cookie = cookie;
|
||||
tx->cookie = cookie;
|
||||
|
||||
/* ipu->lock can be taken under ichan->lock, but not v.v. */
|
||||
spin_lock_irqsave(&ichan->lock, flags);
|
||||
|
||||
list_add_tail(&desc->list, &ichan->queue);
|
||||
/* submit_buffers() atomically verifies and fills empty sg slots */
|
||||
ret = ipu_submit_channel_buffers(ichan, desc);
|
||||
|
||||
spin_unlock_irqrestore(&ichan->lock, flags);
|
||||
|
||||
if (ret < 0) {
|
||||
cookie = ret;
|
||||
goto dequeue;
|
||||
}
|
||||
|
||||
if (ichan->status < IPU_CHANNEL_ENABLED) {
|
||||
int ret = ipu_enable_channel(idmac, ichan);
|
||||
ret = ipu_enable_channel(idmac, ichan);
|
||||
if (ret < 0) {
|
||||
cookie = ret;
|
||||
spin_lock_irqsave(&ichan->lock, flags);
|
||||
list_del_init(&desc->list);
|
||||
spin_unlock_irqrestore(&ichan->lock, flags);
|
||||
tx->cookie = cookie;
|
||||
ichan->dma_chan.cookie = cookie;
|
||||
goto dequeue;
|
||||
}
|
||||
}
|
||||
|
||||
dump_idmac_reg(ipu);
|
||||
|
||||
dequeue:
|
||||
if (cookie < 0) {
|
||||
spin_lock_irqsave(&ichan->lock, flags);
|
||||
list_del_init(&desc->list);
|
||||
spin_unlock_irqrestore(&ichan->lock, flags);
|
||||
tx->cookie = cookie;
|
||||
ichan->dma_chan.cookie = cookie;
|
||||
}
|
||||
|
||||
out:
|
||||
mutex_unlock(&ichan->chan_mutex);
|
||||
|
||||
|
@ -944,8 +983,6 @@ static int idmac_desc_alloc(struct idmac_channel *ichan, int n)
|
|||
memset(txd, 0, sizeof(*txd));
|
||||
dma_async_tx_descriptor_init(txd, &ichan->dma_chan);
|
||||
txd->tx_submit = idmac_tx_submit;
|
||||
txd->chan = &ichan->dma_chan;
|
||||
INIT_LIST_HEAD(&txd->tx_list);
|
||||
|
||||
list_add(&desc->list, &ichan->free_list);
|
||||
|
||||
|
@ -1161,6 +1198,24 @@ static int ipu_disable_channel(struct idmac *idmac, struct idmac_channel *ichan,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static struct scatterlist *idmac_sg_next(struct idmac_channel *ichan,
|
||||
struct idmac_tx_desc **desc, struct scatterlist *sg)
|
||||
{
|
||||
struct scatterlist *sgnew = sg ? sg_next(sg) : NULL;
|
||||
|
||||
if (sgnew)
|
||||
/* next sg-element in this list */
|
||||
return sgnew;
|
||||
|
||||
if ((*desc)->list.next == &ichan->queue)
|
||||
/* No more descriptors on the queue */
|
||||
return NULL;
|
||||
|
||||
/* Fetch next descriptor */
|
||||
*desc = list_entry((*desc)->list.next, struct idmac_tx_desc, list);
|
||||
return (*desc)->sg;
|
||||
}
|
||||
|
||||
/*
|
||||
* We have several possibilities here:
|
||||
* current BUF next BUF
|
||||
|
@ -1176,23 +1231,46 @@ static int ipu_disable_channel(struct idmac *idmac, struct idmac_channel *ichan,
|
|||
static irqreturn_t idmac_interrupt(int irq, void *dev_id)
|
||||
{
|
||||
struct idmac_channel *ichan = dev_id;
|
||||
struct device *dev = &ichan->dma_chan.dev->device;
|
||||
unsigned int chan_id = ichan->dma_chan.chan_id;
|
||||
struct scatterlist **sg, *sgnext, *sgnew = NULL;
|
||||
/* Next transfer descriptor */
|
||||
struct idmac_tx_desc *desc = NULL, *descnew;
|
||||
struct idmac_tx_desc *desc, *descnew;
|
||||
dma_async_tx_callback callback;
|
||||
void *callback_param;
|
||||
bool done = false;
|
||||
u32 ready0 = idmac_read_ipureg(&ipu_data, IPU_CHA_BUF0_RDY),
|
||||
ready1 = idmac_read_ipureg(&ipu_data, IPU_CHA_BUF1_RDY),
|
||||
curbuf = idmac_read_ipureg(&ipu_data, IPU_CHA_CUR_BUF);
|
||||
u32 ready0, ready1, curbuf, err;
|
||||
unsigned long flags;
|
||||
|
||||
/* IDMAC has cleared the respective BUFx_RDY bit, we manage the buffer */
|
||||
|
||||
pr_debug("IDMAC irq %d\n", irq);
|
||||
dev_dbg(dev, "IDMAC irq %d, buf %d\n", irq, ichan->active_buffer);
|
||||
|
||||
spin_lock_irqsave(&ipu_data.lock, flags);
|
||||
|
||||
ready0 = idmac_read_ipureg(&ipu_data, IPU_CHA_BUF0_RDY);
|
||||
ready1 = idmac_read_ipureg(&ipu_data, IPU_CHA_BUF1_RDY);
|
||||
curbuf = idmac_read_ipureg(&ipu_data, IPU_CHA_CUR_BUF);
|
||||
err = idmac_read_ipureg(&ipu_data, IPU_INT_STAT_4);
|
||||
|
||||
if (err & (1 << chan_id)) {
|
||||
idmac_write_ipureg(&ipu_data, 1 << chan_id, IPU_INT_STAT_4);
|
||||
spin_unlock_irqrestore(&ipu_data.lock, flags);
|
||||
/*
|
||||
* Doing this
|
||||
* ichan->sg[0] = ichan->sg[1] = NULL;
|
||||
* you can force channel re-enable on the next tx_submit(), but
|
||||
* this is dirty - think about descriptors with multiple
|
||||
* sg elements.
|
||||
*/
|
||||
dev_warn(dev, "NFB4EOF on channel %d, ready %x, %x, cur %x\n",
|
||||
chan_id, ready0, ready1, curbuf);
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
spin_unlock_irqrestore(&ipu_data.lock, flags);
|
||||
|
||||
/* Other interrupts do not interfere with this channel */
|
||||
spin_lock(&ichan->lock);
|
||||
|
||||
if (unlikely(chan_id != IDMAC_SDC_0 && chan_id != IDMAC_SDC_1 &&
|
||||
((curbuf >> chan_id) & 1) == ichan->active_buffer)) {
|
||||
int i = 100;
|
||||
|
@ -1207,19 +1285,23 @@ static irqreturn_t idmac_interrupt(int irq, void *dev_id)
|
|||
|
||||
if (!i) {
|
||||
spin_unlock(&ichan->lock);
|
||||
dev_dbg(ichan->dma_chan.device->dev,
|
||||
dev_dbg(dev,
|
||||
"IRQ on active buffer on channel %x, active "
|
||||
"%d, ready %x, %x, current %x!\n", chan_id,
|
||||
ichan->active_buffer, ready0, ready1, curbuf);
|
||||
return IRQ_NONE;
|
||||
}
|
||||
} else
|
||||
dev_dbg(dev,
|
||||
"Buffer deactivated on channel %x, active "
|
||||
"%d, ready %x, %x, current %x, rest %d!\n", chan_id,
|
||||
ichan->active_buffer, ready0, ready1, curbuf, i);
|
||||
}
|
||||
|
||||
if (unlikely((ichan->active_buffer && (ready1 >> chan_id) & 1) ||
|
||||
(!ichan->active_buffer && (ready0 >> chan_id) & 1)
|
||||
)) {
|
||||
spin_unlock(&ichan->lock);
|
||||
dev_dbg(ichan->dma_chan.device->dev,
|
||||
dev_dbg(dev,
|
||||
"IRQ with active buffer still ready on channel %x, "
|
||||
"active %d, ready %x, %x!\n", chan_id,
|
||||
ichan->active_buffer, ready0, ready1);
|
||||
|
@ -1227,8 +1309,9 @@ static irqreturn_t idmac_interrupt(int irq, void *dev_id)
|
|||
}
|
||||
|
||||
if (unlikely(list_empty(&ichan->queue))) {
|
||||
ichan->sg[ichan->active_buffer] = NULL;
|
||||
spin_unlock(&ichan->lock);
|
||||
dev_err(ichan->dma_chan.device->dev,
|
||||
dev_err(dev,
|
||||
"IRQ without queued buffers on channel %x, active %d, "
|
||||
"ready %x, %x!\n", chan_id,
|
||||
ichan->active_buffer, ready0, ready1);
|
||||
|
@ -1243,40 +1326,44 @@ static irqreturn_t idmac_interrupt(int irq, void *dev_id)
|
|||
sg = &ichan->sg[ichan->active_buffer];
|
||||
sgnext = ichan->sg[!ichan->active_buffer];
|
||||
|
||||
if (!*sg) {
|
||||
spin_unlock(&ichan->lock);
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
desc = list_entry(ichan->queue.next, struct idmac_tx_desc, list);
|
||||
descnew = desc;
|
||||
|
||||
dev_dbg(dev, "IDMAC irq %d, dma 0x%08x, next dma 0x%08x, current %d, curbuf 0x%08x\n",
|
||||
irq, sg_dma_address(*sg), sgnext ? sg_dma_address(sgnext) : 0, ichan->active_buffer, curbuf);
|
||||
|
||||
/* Find the descriptor of sgnext */
|
||||
sgnew = idmac_sg_next(ichan, &descnew, *sg);
|
||||
if (sgnext != sgnew)
|
||||
dev_err(dev, "Submitted buffer %p, next buffer %p\n", sgnext, sgnew);
|
||||
|
||||
/*
|
||||
* if sgnext == NULL sg must be the last element in a scatterlist and
|
||||
* queue must be empty
|
||||
*/
|
||||
if (unlikely(!sgnext)) {
|
||||
if (unlikely(sg_next(*sg))) {
|
||||
dev_err(ichan->dma_chan.device->dev,
|
||||
"Broken buffer-update locking on channel %x!\n",
|
||||
chan_id);
|
||||
/* We'll let the user catch up */
|
||||
if (!WARN_ON(sg_next(*sg)))
|
||||
dev_dbg(dev, "Underrun on channel %x\n", chan_id);
|
||||
ichan->sg[!ichan->active_buffer] = sgnew;
|
||||
|
||||
if (unlikely(sgnew)) {
|
||||
ipu_submit_buffer(ichan, descnew, sgnew, !ichan->active_buffer);
|
||||
} else {
|
||||
/* Underrun */
|
||||
spin_lock_irqsave(&ipu_data.lock, flags);
|
||||
ipu_ic_disable_task(&ipu_data, chan_id);
|
||||
dev_dbg(ichan->dma_chan.device->dev,
|
||||
"Underrun on channel %x\n", chan_id);
|
||||
spin_unlock_irqrestore(&ipu_data.lock, flags);
|
||||
ichan->status = IPU_CHANNEL_READY;
|
||||
/* Continue to check for complete descriptor */
|
||||
}
|
||||
}
|
||||
|
||||
desc = list_entry(ichan->queue.next, struct idmac_tx_desc, list);
|
||||
|
||||
/* First calculate and submit the next sg element */
|
||||
if (likely(sgnext))
|
||||
sgnew = sg_next(sgnext);
|
||||
|
||||
if (unlikely(!sgnew)) {
|
||||
/* Start a new scatterlist, if any queued */
|
||||
if (likely(desc->list.next != &ichan->queue)) {
|
||||
descnew = list_entry(desc->list.next,
|
||||
struct idmac_tx_desc, list);
|
||||
sgnew = &descnew->sg[0];
|
||||
}
|
||||
}
|
||||
/* Calculate and submit the next sg element */
|
||||
sgnew = idmac_sg_next(ichan, &descnew, sgnew);
|
||||
|
||||
if (unlikely(!sg_next(*sg)) || !sgnext) {
|
||||
/*
|
||||
|
@ -1289,17 +1376,13 @@ static irqreturn_t idmac_interrupt(int irq, void *dev_id)
|
|||
|
||||
*sg = sgnew;
|
||||
|
||||
if (likely(sgnew)) {
|
||||
int ret;
|
||||
|
||||
ret = ipu_update_channel_buffer(chan_id, ichan->active_buffer,
|
||||
sg_dma_address(*sg));
|
||||
if (ret < 0)
|
||||
dev_err(ichan->dma_chan.device->dev,
|
||||
"Failed to update buffer on channel %x buffer %d!\n",
|
||||
chan_id, ichan->active_buffer);
|
||||
else
|
||||
ipu_select_buffer(chan_id, ichan->active_buffer);
|
||||
if (likely(sgnew) &&
|
||||
ipu_submit_buffer(ichan, descnew, sgnew, ichan->active_buffer) < 0) {
|
||||
callback = desc->txd.callback;
|
||||
callback_param = desc->txd.callback_param;
|
||||
spin_unlock(&ichan->lock);
|
||||
callback(callback_param);
|
||||
spin_lock(&ichan->lock);
|
||||
}
|
||||
|
||||
/* Flip the active buffer - even if update above failed */
|
||||
|
@ -1327,13 +1410,20 @@ static void ipu_gc_tasklet(unsigned long arg)
|
|||
struct idmac_channel *ichan = ipu->channel + i;
|
||||
struct idmac_tx_desc *desc;
|
||||
unsigned long flags;
|
||||
int j;
|
||||
struct scatterlist *sg;
|
||||
int j, k;
|
||||
|
||||
for (j = 0; j < ichan->n_tx_desc; j++) {
|
||||
desc = ichan->desc + j;
|
||||
spin_lock_irqsave(&ichan->lock, flags);
|
||||
if (async_tx_test_ack(&desc->txd)) {
|
||||
list_move(&desc->list, &ichan->free_list);
|
||||
for_each_sg(desc->sg, sg, desc->sg_len, k) {
|
||||
if (ichan->sg[0] == sg)
|
||||
ichan->sg[0] = NULL;
|
||||
else if (ichan->sg[1] == sg)
|
||||
ichan->sg[1] = NULL;
|
||||
}
|
||||
async_tx_clear_ack(&desc->txd);
|
||||
}
|
||||
spin_unlock_irqrestore(&ichan->lock, flags);
|
||||
|
@ -1341,13 +1431,7 @@ static void ipu_gc_tasklet(unsigned long arg)
|
|||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* At the time .device_alloc_chan_resources() method is called, we cannot know,
|
||||
* whether the client will accept the channel. Thus we must only check, if we
|
||||
* can satisfy client's request but the only real criterion to verify, whether
|
||||
* the client has accepted our offer is the client_count. That's why we have to
|
||||
* perform the rest of our allocation tasks on the first call to this function.
|
||||
*/
|
||||
/* Allocate and initialise a transfer descriptor. */
|
||||
static struct dma_async_tx_descriptor *idmac_prep_slave_sg(struct dma_chan *chan,
|
||||
struct scatterlist *sgl, unsigned int sg_len,
|
||||
enum dma_data_direction direction, unsigned long tx_flags)
|
||||
|
@ -1358,8 +1442,8 @@ static struct dma_async_tx_descriptor *idmac_prep_slave_sg(struct dma_chan *chan
|
|||
unsigned long flags;
|
||||
|
||||
/* We only can handle these three channels so far */
|
||||
if (ichan->dma_chan.chan_id != IDMAC_SDC_0 && ichan->dma_chan.chan_id != IDMAC_SDC_1 &&
|
||||
ichan->dma_chan.chan_id != IDMAC_IC_7)
|
||||
if (chan->chan_id != IDMAC_SDC_0 && chan->chan_id != IDMAC_SDC_1 &&
|
||||
chan->chan_id != IDMAC_IC_7)
|
||||
return NULL;
|
||||
|
||||
if (direction != DMA_FROM_DEVICE && direction != DMA_TO_DEVICE) {
|
||||
|
@ -1400,7 +1484,7 @@ static void idmac_issue_pending(struct dma_chan *chan)
|
|||
|
||||
/* This is not always needed, but doesn't hurt either */
|
||||
spin_lock_irqsave(&ipu->lock, flags);
|
||||
ipu_select_buffer(ichan->dma_chan.chan_id, ichan->active_buffer);
|
||||
ipu_select_buffer(chan->chan_id, ichan->active_buffer);
|
||||
spin_unlock_irqrestore(&ipu->lock, flags);
|
||||
|
||||
/*
|
||||
|
@ -1432,8 +1516,7 @@ static void __idmac_terminate_all(struct dma_chan *chan)
|
|||
struct idmac_tx_desc *desc = ichan->desc + i;
|
||||
if (list_empty(&desc->list))
|
||||
/* Descriptor was prepared, but not submitted */
|
||||
list_add(&desc->list,
|
||||
&ichan->free_list);
|
||||
list_add(&desc->list, &ichan->free_list);
|
||||
|
||||
async_tx_clear_ack(&desc->txd);
|
||||
}
|
||||
|
@ -1458,6 +1541,28 @@ static void idmac_terminate_all(struct dma_chan *chan)
|
|||
mutex_unlock(&ichan->chan_mutex);
|
||||
}
|
||||
|
||||
#ifdef DEBUG
|
||||
static irqreturn_t ic_sof_irq(int irq, void *dev_id)
|
||||
{
|
||||
struct idmac_channel *ichan = dev_id;
|
||||
printk(KERN_DEBUG "Got SOF IRQ %d on Channel %d\n",
|
||||
irq, ichan->dma_chan.chan_id);
|
||||
disable_irq(irq);
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static irqreturn_t ic_eof_irq(int irq, void *dev_id)
|
||||
{
|
||||
struct idmac_channel *ichan = dev_id;
|
||||
printk(KERN_DEBUG "Got EOF IRQ %d on Channel %d\n",
|
||||
irq, ichan->dma_chan.chan_id);
|
||||
disable_irq(irq);
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static int ic_sof = -EINVAL, ic_eof = -EINVAL;
|
||||
#endif
|
||||
|
||||
static int idmac_alloc_chan_resources(struct dma_chan *chan)
|
||||
{
|
||||
struct idmac_channel *ichan = to_idmac_chan(chan);
|
||||
|
@ -1471,31 +1576,49 @@ static int idmac_alloc_chan_resources(struct dma_chan *chan)
|
|||
chan->cookie = 1;
|
||||
ichan->completed = -ENXIO;
|
||||
|
||||
ret = ipu_irq_map(ichan->dma_chan.chan_id);
|
||||
ret = ipu_irq_map(chan->chan_id);
|
||||
if (ret < 0)
|
||||
goto eimap;
|
||||
|
||||
ichan->eof_irq = ret;
|
||||
ret = request_irq(ichan->eof_irq, idmac_interrupt, 0,
|
||||
ichan->eof_name, ichan);
|
||||
if (ret < 0)
|
||||
goto erirq;
|
||||
|
||||
/*
|
||||
* Important to first disable the channel, because maybe someone
|
||||
* used it before us, e.g., the bootloader
|
||||
*/
|
||||
ipu_disable_channel(idmac, ichan, true);
|
||||
|
||||
ret = ipu_init_channel(idmac, ichan);
|
||||
if (ret < 0)
|
||||
goto eichan;
|
||||
|
||||
ret = request_irq(ichan->eof_irq, idmac_interrupt, 0,
|
||||
ichan->eof_name, ichan);
|
||||
if (ret < 0)
|
||||
goto erirq;
|
||||
|
||||
#ifdef DEBUG
|
||||
if (chan->chan_id == IDMAC_IC_7) {
|
||||
ic_sof = ipu_irq_map(69);
|
||||
if (ic_sof > 0)
|
||||
request_irq(ic_sof, ic_sof_irq, 0, "IC SOF", ichan);
|
||||
ic_eof = ipu_irq_map(70);
|
||||
if (ic_eof > 0)
|
||||
request_irq(ic_eof, ic_eof_irq, 0, "IC EOF", ichan);
|
||||
}
|
||||
#endif
|
||||
|
||||
ichan->status = IPU_CHANNEL_INITIALIZED;
|
||||
|
||||
dev_dbg(&ichan->dma_chan.dev->device, "Found channel 0x%x, irq %d\n",
|
||||
ichan->dma_chan.chan_id, ichan->eof_irq);
|
||||
dev_dbg(&chan->dev->device, "Found channel 0x%x, irq %d\n",
|
||||
chan->chan_id, ichan->eof_irq);
|
||||
|
||||
return ret;
|
||||
|
||||
eichan:
|
||||
free_irq(ichan->eof_irq, ichan);
|
||||
erirq:
|
||||
ipu_irq_unmap(ichan->dma_chan.chan_id);
|
||||
ipu_uninit_channel(idmac, ichan);
|
||||
eichan:
|
||||
ipu_irq_unmap(chan->chan_id);
|
||||
eimap:
|
||||
return ret;
|
||||
}
|
||||
|
@ -1510,8 +1633,22 @@ static void idmac_free_chan_resources(struct dma_chan *chan)
|
|||
__idmac_terminate_all(chan);
|
||||
|
||||
if (ichan->status > IPU_CHANNEL_FREE) {
|
||||
#ifdef DEBUG
|
||||
if (chan->chan_id == IDMAC_IC_7) {
|
||||
if (ic_sof > 0) {
|
||||
free_irq(ic_sof, ichan);
|
||||
ipu_irq_unmap(69);
|
||||
ic_sof = -EINVAL;
|
||||
}
|
||||
if (ic_eof > 0) {
|
||||
free_irq(ic_eof, ichan);
|
||||
ipu_irq_unmap(70);
|
||||
ic_eof = -EINVAL;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
free_irq(ichan->eof_irq, ichan);
|
||||
ipu_irq_unmap(ichan->dma_chan.chan_id);
|
||||
ipu_irq_unmap(chan->chan_id);
|
||||
}
|
||||
|
||||
ichan->status = IPU_CHANNEL_FREE;
|
||||
|
@ -1573,7 +1710,7 @@ static int __init ipu_idmac_init(struct ipu *ipu)
|
|||
dma_chan->device = &idmac->dma;
|
||||
dma_chan->cookie = 1;
|
||||
dma_chan->chan_id = i;
|
||||
list_add_tail(&ichan->dma_chan.device_node, &dma->channels);
|
||||
list_add_tail(&dma_chan->device_node, &dma->channels);
|
||||
}
|
||||
|
||||
idmac_write_icreg(ipu, 0x00000070, IDMAC_CONF);
|
||||
|
@ -1581,7 +1718,7 @@ static int __init ipu_idmac_init(struct ipu *ipu)
|
|||
return dma_async_device_register(&idmac->dma);
|
||||
}
|
||||
|
||||
static void ipu_idmac_exit(struct ipu *ipu)
|
||||
static void __exit ipu_idmac_exit(struct ipu *ipu)
|
||||
{
|
||||
int i;
|
||||
struct idmac *idmac = &ipu->idmac;
|
||||
|
@ -1600,7 +1737,7 @@ static void ipu_idmac_exit(struct ipu *ipu)
|
|||
* IPU common probe / remove
|
||||
*/
|
||||
|
||||
static int ipu_probe(struct platform_device *pdev)
|
||||
static int __init ipu_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct ipu_platform_data *pdata = pdev->dev.platform_data;
|
||||
struct resource *mem_ipu, *mem_ic;
|
||||
|
@ -1700,7 +1837,7 @@ err_noirq:
|
|||
return ret;
|
||||
}
|
||||
|
||||
static int ipu_remove(struct platform_device *pdev)
|
||||
static int __exit ipu_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct ipu *ipu = platform_get_drvdata(pdev);
|
||||
|
||||
|
@ -1725,7 +1862,7 @@ static struct platform_driver ipu_platform_driver = {
|
|||
.name = "ipu-core",
|
||||
.owner = THIS_MODULE,
|
||||
},
|
||||
.remove = ipu_remove,
|
||||
.remove = __exit_p(ipu_remove),
|
||||
};
|
||||
|
||||
static int __init ipu_init(void)
|
||||
|
|
|
@ -352,7 +352,7 @@ static struct irq_chip ipu_irq_chip = {
|
|||
};
|
||||
|
||||
/* Install the IRQ handler */
|
||||
int ipu_irq_attach_irq(struct ipu *ipu, struct platform_device *dev)
|
||||
int __init ipu_irq_attach_irq(struct ipu *ipu, struct platform_device *dev)
|
||||
{
|
||||
struct ipu_platform_data *pdata = dev->dev.platform_data;
|
||||
unsigned int irq, irq_base, i;
|
||||
|
|
|
@ -632,7 +632,6 @@ static int mv_xor_alloc_chan_resources(struct dma_chan *chan)
|
|||
slot->async_tx.tx_submit = mv_xor_tx_submit;
|
||||
INIT_LIST_HEAD(&slot->chain_node);
|
||||
INIT_LIST_HEAD(&slot->slot_node);
|
||||
INIT_LIST_HEAD(&slot->async_tx.tx_list);
|
||||
hw_desc = (char *) mv_chan->device->dma_desc_pool;
|
||||
slot->async_tx.phys =
|
||||
(dma_addr_t) &hw_desc[idx * MV_XOR_SLOT_SIZE];
|
||||
|
|
|
@ -1105,7 +1105,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
|
|||
1024 * 1024,
|
||||
MTRR_TYPE_WRCOMB, 1);
|
||||
if (dev_priv->mm.gtt_mtrr < 0) {
|
||||
DRM_INFO("MTRR allocation failed\n. Graphics "
|
||||
DRM_INFO("MTRR allocation failed. Graphics "
|
||||
"performance may suffer.\n");
|
||||
}
|
||||
|
||||
|
|
|
@ -279,7 +279,6 @@ typedef struct drm_i915_private {
|
|||
u8 saveAR_INDEX;
|
||||
u8 saveAR[21];
|
||||
u8 saveDACMASK;
|
||||
u8 saveDACDATA[256*3]; /* 256 3-byte colors */
|
||||
u8 saveCR[37];
|
||||
|
||||
struct {
|
||||
|
@ -457,6 +456,12 @@ struct drm_i915_gem_object {
|
|||
|
||||
/** for phy allocated objects */
|
||||
struct drm_i915_gem_phys_object *phys_obj;
|
||||
|
||||
/**
|
||||
* Used for checking the object doesn't appear more than once
|
||||
* in an execbuffer object list.
|
||||
*/
|
||||
int in_execbuffer;
|
||||
};
|
||||
|
||||
/**
|
||||
|
|
|
@ -1476,7 +1476,7 @@ static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
|
|||
struct drm_i915_gem_object *obj_priv = obj->driver_private;
|
||||
int regnum = obj_priv->fence_reg;
|
||||
int tile_width;
|
||||
uint32_t val;
|
||||
uint32_t fence_reg, val;
|
||||
uint32_t pitch_val;
|
||||
|
||||
if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
|
||||
|
@ -1503,7 +1503,11 @@ static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
|
|||
val |= pitch_val << I830_FENCE_PITCH_SHIFT;
|
||||
val |= I830_FENCE_REG_VALID;
|
||||
|
||||
I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
|
||||
if (regnum < 8)
|
||||
fence_reg = FENCE_REG_830_0 + (regnum * 4);
|
||||
else
|
||||
fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
|
||||
I915_WRITE(fence_reg, val);
|
||||
}
|
||||
|
||||
static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
|
||||
|
@ -1557,7 +1561,8 @@ i915_gem_object_get_fence_reg(struct drm_gem_object *obj, bool write)
|
|||
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||
struct drm_i915_gem_object *obj_priv = obj->driver_private;
|
||||
struct drm_i915_fence_reg *reg = NULL;
|
||||
int i, ret;
|
||||
struct drm_i915_gem_object *old_obj_priv = NULL;
|
||||
int i, ret, avail;
|
||||
|
||||
switch (obj_priv->tiling_mode) {
|
||||
case I915_TILING_NONE:
|
||||
|
@ -1580,25 +1585,46 @@ i915_gem_object_get_fence_reg(struct drm_gem_object *obj, bool write)
|
|||
}
|
||||
|
||||
/* First try to find a free reg */
|
||||
try_again:
|
||||
avail = 0;
|
||||
for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
|
||||
reg = &dev_priv->fence_regs[i];
|
||||
if (!reg->obj)
|
||||
break;
|
||||
|
||||
old_obj_priv = reg->obj->driver_private;
|
||||
if (!old_obj_priv->pin_count)
|
||||
avail++;
|
||||
}
|
||||
|
||||
/* None available, try to steal one or wait for a user to finish */
|
||||
if (i == dev_priv->num_fence_regs) {
|
||||
struct drm_i915_gem_object *old_obj_priv = NULL;
|
||||
uint32_t seqno = dev_priv->mm.next_gem_seqno;
|
||||
loff_t offset;
|
||||
|
||||
try_again:
|
||||
/* Could try to use LRU here instead... */
|
||||
if (avail == 0)
|
||||
return -ENOMEM;
|
||||
|
||||
for (i = dev_priv->fence_reg_start;
|
||||
i < dev_priv->num_fence_regs; i++) {
|
||||
uint32_t this_seqno;
|
||||
|
||||
reg = &dev_priv->fence_regs[i];
|
||||
old_obj_priv = reg->obj->driver_private;
|
||||
if (!old_obj_priv->pin_count)
|
||||
|
||||
if (old_obj_priv->pin_count)
|
||||
continue;
|
||||
|
||||
/* i915 uses fences for GPU access to tiled buffers */
|
||||
if (IS_I965G(dev) || !old_obj_priv->active)
|
||||
break;
|
||||
|
||||
/* find the seqno of the first available fence */
|
||||
this_seqno = old_obj_priv->last_rendering_seqno;
|
||||
if (this_seqno != 0 &&
|
||||
reg->obj->write_domain == 0 &&
|
||||
i915_seqno_passed(seqno, this_seqno))
|
||||
seqno = this_seqno;
|
||||
}
|
||||
|
||||
/*
|
||||
|
@ -1606,15 +1632,25 @@ try_again:
|
|||
* objects to finish before trying again.
|
||||
*/
|
||||
if (i == dev_priv->num_fence_regs) {
|
||||
ret = i915_gem_object_set_to_gtt_domain(reg->obj, 0);
|
||||
if (ret) {
|
||||
WARN(ret != -ERESTARTSYS,
|
||||
"switch to GTT domain failed: %d\n", ret);
|
||||
return ret;
|
||||
if (seqno == dev_priv->mm.next_gem_seqno) {
|
||||
i915_gem_flush(dev,
|
||||
I915_GEM_GPU_DOMAINS,
|
||||
I915_GEM_GPU_DOMAINS);
|
||||
seqno = i915_add_request(dev,
|
||||
I915_GEM_GPU_DOMAINS);
|
||||
if (seqno == 0)
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
ret = i915_wait_request(dev, seqno);
|
||||
if (ret)
|
||||
return ret;
|
||||
goto try_again;
|
||||
}
|
||||
|
||||
BUG_ON(old_obj_priv->active ||
|
||||
(reg->obj->write_domain & I915_GEM_GPU_DOMAINS));
|
||||
|
||||
/*
|
||||
* Zap this virtual mapping so we can set up a fence again
|
||||
* for this object next time we need it.
|
||||
|
@ -1655,8 +1691,17 @@ i915_gem_clear_fence_reg(struct drm_gem_object *obj)
|
|||
|
||||
if (IS_I965G(dev))
|
||||
I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
|
||||
else
|
||||
I915_WRITE(FENCE_REG_830_0 + (obj_priv->fence_reg * 4), 0);
|
||||
else {
|
||||
uint32_t fence_reg;
|
||||
|
||||
if (obj_priv->fence_reg < 8)
|
||||
fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
|
||||
else
|
||||
fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg -
|
||||
8) * 4;
|
||||
|
||||
I915_WRITE(fence_reg, 0);
|
||||
}
|
||||
|
||||
dev_priv->fence_regs[obj_priv->fence_reg].obj = NULL;
|
||||
obj_priv->fence_reg = I915_FENCE_REG_NONE;
|
||||
|
@ -2469,6 +2514,7 @@ i915_gem_execbuffer(struct drm_device *dev, void *data,
|
|||
struct drm_i915_gem_exec_object *exec_list = NULL;
|
||||
struct drm_gem_object **object_list = NULL;
|
||||
struct drm_gem_object *batch_obj;
|
||||
struct drm_i915_gem_object *obj_priv;
|
||||
int ret, i, pinned = 0;
|
||||
uint64_t exec_offset;
|
||||
uint32_t seqno, flush_domains;
|
||||
|
@ -2533,6 +2579,15 @@ i915_gem_execbuffer(struct drm_device *dev, void *data,
|
|||
ret = -EBADF;
|
||||
goto err;
|
||||
}
|
||||
|
||||
obj_priv = object_list[i]->driver_private;
|
||||
if (obj_priv->in_execbuffer) {
|
||||
DRM_ERROR("Object %p appears more than once in object list\n",
|
||||
object_list[i]);
|
||||
ret = -EBADF;
|
||||
goto err;
|
||||
}
|
||||
obj_priv->in_execbuffer = true;
|
||||
}
|
||||
|
||||
/* Pin and relocate */
|
||||
|
@ -2674,8 +2729,13 @@ err:
|
|||
for (i = 0; i < pinned; i++)
|
||||
i915_gem_object_unpin(object_list[i]);
|
||||
|
||||
for (i = 0; i < args->buffer_count; i++)
|
||||
for (i = 0; i < args->buffer_count; i++) {
|
||||
if (object_list[i]) {
|
||||
obj_priv = object_list[i]->driver_private;
|
||||
obj_priv->in_execbuffer = false;
|
||||
}
|
||||
drm_gem_object_unreference(object_list[i]);
|
||||
}
|
||||
|
||||
mutex_unlock(&dev->struct_mutex);
|
||||
|
||||
|
@ -2712,17 +2772,24 @@ i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
|
|||
ret = i915_gem_object_bind_to_gtt(obj, alignment);
|
||||
if (ret != 0) {
|
||||
if (ret != -EBUSY && ret != -ERESTARTSYS)
|
||||
DRM_ERROR("Failure to bind: %d", ret);
|
||||
DRM_ERROR("Failure to bind: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
/*
|
||||
* Pre-965 chips need a fence register set up in order to
|
||||
* properly handle tiled surfaces.
|
||||
*/
|
||||
if (!IS_I965G(dev) &&
|
||||
obj_priv->fence_reg == I915_FENCE_REG_NONE &&
|
||||
obj_priv->tiling_mode != I915_TILING_NONE) {
|
||||
ret = i915_gem_object_get_fence_reg(obj, true);
|
||||
if (ret != 0) {
|
||||
if (ret != -EBUSY && ret != -ERESTARTSYS)
|
||||
DRM_ERROR("Failure to install fence: %d\n",
|
||||
ret);
|
||||
return ret;
|
||||
}
|
||||
/*
|
||||
* Pre-965 chips need a fence register set up in order to
|
||||
* properly handle tiled surfaces.
|
||||
*/
|
||||
if (!IS_I965G(dev) &&
|
||||
obj_priv->fence_reg == I915_FENCE_REG_NONE &&
|
||||
obj_priv->tiling_mode != I915_TILING_NONE)
|
||||
i915_gem_object_get_fence_reg(obj, true);
|
||||
}
|
||||
obj_priv->pin_count++;
|
||||
|
||||
|
|
|
@ -184,6 +184,7 @@
|
|||
* Fence registers
|
||||
*/
|
||||
#define FENCE_REG_830_0 0x2000
|
||||
#define FENCE_REG_945_8 0x3000
|
||||
#define I830_FENCE_START_MASK 0x07f80000
|
||||
#define I830_FENCE_TILING_Y_SHIFT 12
|
||||
#define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
|
||||
|
|
|
@ -119,11 +119,6 @@ static void i915_save_vga(struct drm_device *dev)
|
|||
|
||||
/* VGA color palette registers */
|
||||
dev_priv->saveDACMASK = I915_READ8(VGA_DACMASK);
|
||||
/* DACCRX automatically increments during read */
|
||||
I915_WRITE8(VGA_DACRX, 0);
|
||||
/* Read 3 bytes of color data from each index */
|
||||
for (i = 0; i < 256 * 3; i++)
|
||||
dev_priv->saveDACDATA[i] = I915_READ8(VGA_DACDATA);
|
||||
|
||||
/* MSR bits */
|
||||
dev_priv->saveMSR = I915_READ8(VGA_MSR_READ);
|
||||
|
@ -225,12 +220,6 @@ static void i915_restore_vga(struct drm_device *dev)
|
|||
|
||||
/* VGA color palette registers */
|
||||
I915_WRITE8(VGA_DACMASK, dev_priv->saveDACMASK);
|
||||
/* DACCRX automatically increments during read */
|
||||
I915_WRITE8(VGA_DACWX, 0);
|
||||
/* Read 3 bytes of color data from each index */
|
||||
for (i = 0; i < 256 * 3; i++)
|
||||
I915_WRITE8(VGA_DACDATA, dev_priv->saveDACDATA[i]);
|
||||
|
||||
}
|
||||
|
||||
int i915_save_state(struct drm_device *dev)
|
||||
|
|
|
@ -543,8 +543,8 @@ config SENSORS_LM90
|
|||
help
|
||||
If you say yes here you get support for National Semiconductor LM90,
|
||||
LM86, LM89 and LM99, Analog Devices ADM1032 and ADT7461, and Maxim
|
||||
MAX6646, MAX6647, MAX6649, MAX6657, MAX6658, MAX6659, MAX6680 and
|
||||
MAX6681 sensor chips.
|
||||
MAX6646, MAX6647, MAX6648, MAX6649, MAX6657, MAX6658, MAX6659,
|
||||
MAX6680, MAX6681 and MAX6692 sensor chips.
|
||||
|
||||
This driver can also be built as a module. If so, the module
|
||||
will be called lm90.
|
||||
|
|
|
@ -760,8 +760,11 @@ static int abituguru3_read_increment_offset(struct abituguru3_data *data,
|
|||
|
||||
for (i = 0; i < offset_count; i++)
|
||||
if ((x = abituguru3_read(data, bank, offset + i, count,
|
||||
buf + i * count)) != count)
|
||||
return i * count + (i && (x < 0)) ? 0 : x;
|
||||
buf + i * count)) != count) {
|
||||
if (x < 0)
|
||||
return x;
|
||||
return i * count + x;
|
||||
}
|
||||
|
||||
return i * count;
|
||||
}
|
||||
|
|
|
@ -617,7 +617,7 @@ static void f75375_init(struct i2c_client *client, struct f75375_data *data,
|
|||
static int f75375_probe(struct i2c_client *client,
|
||||
const struct i2c_device_id *id)
|
||||
{
|
||||
struct f75375_data *data = i2c_get_clientdata(client);
|
||||
struct f75375_data *data;
|
||||
struct f75375s_platform_data *f75375s_pdata = client->dev.platform_data;
|
||||
int err;
|
||||
|
||||
|
|
|
@ -213,7 +213,7 @@ static inline u16 FAN16_TO_REG(long rpm)
|
|||
|
||||
#define TEMP_TO_REG(val) (SENSORS_LIMIT(((val)<0?(((val)-500)/1000):\
|
||||
((val)+500)/1000),-128,127))
|
||||
#define TEMP_FROM_REG(val) (((val)>0x80?(val)-0x100:(val))*1000)
|
||||
#define TEMP_FROM_REG(val) ((val) * 1000)
|
||||
|
||||
#define PWM_TO_REG(val) ((val) >> 1)
|
||||
#define PWM_FROM_REG(val) (((val)&0x7f) << 1)
|
||||
|
@ -267,9 +267,9 @@ struct it87_data {
|
|||
u8 has_fan; /* Bitfield, fans enabled */
|
||||
u16 fan[5]; /* Register values, possibly combined */
|
||||
u16 fan_min[5]; /* Register values, possibly combined */
|
||||
u8 temp[3]; /* Register value */
|
||||
u8 temp_high[3]; /* Register value */
|
||||
u8 temp_low[3]; /* Register value */
|
||||
s8 temp[3]; /* Register value */
|
||||
s8 temp_high[3]; /* Register value */
|
||||
s8 temp_low[3]; /* Register value */
|
||||
u8 sensor; /* Register value */
|
||||
u8 fan_div[3]; /* Register encoding, shifted right */
|
||||
u8 vid; /* Register encoding, combined */
|
||||
|
|
|
@ -72,6 +72,7 @@ I2C_CLIENT_INSMOD_7(lm85b, lm85c, adm1027, adt7463, adt7468, emc6d100,
|
|||
#define LM85_COMPANY_SMSC 0x5c
|
||||
#define LM85_VERSTEP_VMASK 0xf0
|
||||
#define LM85_VERSTEP_GENERIC 0x60
|
||||
#define LM85_VERSTEP_GENERIC2 0x70
|
||||
#define LM85_VERSTEP_LM85C 0x60
|
||||
#define LM85_VERSTEP_LM85B 0x62
|
||||
#define LM85_VERSTEP_ADM1027 0x60
|
||||
|
@ -334,6 +335,7 @@ static struct lm85_data *lm85_update_device(struct device *dev);
|
|||
static const struct i2c_device_id lm85_id[] = {
|
||||
{ "adm1027", adm1027 },
|
||||
{ "adt7463", adt7463 },
|
||||
{ "adt7468", adt7468 },
|
||||
{ "lm85", any_chip },
|
||||
{ "lm85b", lm85b },
|
||||
{ "lm85c", lm85c },
|
||||
|
@ -408,7 +410,8 @@ static ssize_t show_vid_reg(struct device *dev, struct device_attribute *attr,
|
|||
struct lm85_data *data = lm85_update_device(dev);
|
||||
int vid;
|
||||
|
||||
if (data->type == adt7463 && (data->vid & 0x80)) {
|
||||
if ((data->type == adt7463 || data->type == adt7468) &&
|
||||
(data->vid & 0x80)) {
|
||||
/* 6-pin VID (VRM 10) */
|
||||
vid = vid_from_reg(data->vid & 0x3f, data->vrm);
|
||||
} else {
|
||||
|
@ -1153,7 +1156,8 @@ static int lm85_detect(struct i2c_client *client, int kind,
|
|||
address, company, verstep);
|
||||
|
||||
/* All supported chips have the version in common */
|
||||
if ((verstep & LM85_VERSTEP_VMASK) != LM85_VERSTEP_GENERIC) {
|
||||
if ((verstep & LM85_VERSTEP_VMASK) != LM85_VERSTEP_GENERIC &&
|
||||
(verstep & LM85_VERSTEP_VMASK) != LM85_VERSTEP_GENERIC2) {
|
||||
dev_dbg(&adapter->dev, "Autodetection failed: "
|
||||
"unsupported version\n");
|
||||
return -ENODEV;
|
||||
|
|
|
@ -32,10 +32,10 @@
|
|||
* supported by this driver. These chips lack the remote temperature
|
||||
* offset feature.
|
||||
*
|
||||
* This driver also supports the MAX6646, MAX6647 and MAX6649 chips
|
||||
* made by Maxim. These are again similar to the LM86, but they use
|
||||
* unsigned temperature values and can report temperatures from 0 to
|
||||
* 145 degrees.
|
||||
* This driver also supports the MAX6646, MAX6647, MAX6648, MAX6649 and
|
||||
* MAX6692 chips made by Maxim. These are again similar to the LM86,
|
||||
* but they use unsigned temperature values and can report temperatures
|
||||
* from 0 to 145 degrees.
|
||||
*
|
||||
* This driver also supports the MAX6680 and MAX6681, two other sensor
|
||||
* chips made by Maxim. These are quite similar to the other Maxim
|
||||
|
|
|
@ -2490,12 +2490,14 @@ static int nes_disconnect(struct nes_qp *nesqp, int abrupt)
|
|||
int ret = 0;
|
||||
struct nes_vnic *nesvnic;
|
||||
struct nes_device *nesdev;
|
||||
struct nes_ib_device *nesibdev;
|
||||
|
||||
nesvnic = to_nesvnic(nesqp->ibqp.device);
|
||||
if (!nesvnic)
|
||||
return -EINVAL;
|
||||
|
||||
nesdev = nesvnic->nesdev;
|
||||
nesibdev = nesvnic->nesibdev;
|
||||
|
||||
nes_debug(NES_DBG_CM, "netdev refcnt = %u.\n",
|
||||
atomic_read(&nesvnic->netdev->refcnt));
|
||||
|
@ -2507,6 +2509,8 @@ static int nes_disconnect(struct nes_qp *nesqp, int abrupt)
|
|||
} else {
|
||||
/* Need to free the Last Streaming Mode Message */
|
||||
if (nesqp->ietf_frame) {
|
||||
if (nesqp->lsmm_mr)
|
||||
nesibdev->ibdev.dereg_mr(nesqp->lsmm_mr);
|
||||
pci_free_consistent(nesdev->pcidev,
|
||||
nesqp->private_data_len+sizeof(struct ietf_mpa_frame),
|
||||
nesqp->ietf_frame, nesqp->ietf_frame_pbase);
|
||||
|
@ -2543,6 +2547,12 @@ int nes_accept(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param)
|
|||
u32 crc_value;
|
||||
int ret;
|
||||
int passive_state;
|
||||
struct nes_ib_device *nesibdev;
|
||||
struct ib_mr *ibmr = NULL;
|
||||
struct ib_phys_buf ibphysbuf;
|
||||
struct nes_pd *nespd;
|
||||
|
||||
|
||||
|
||||
ibqp = nes_get_qp(cm_id->device, conn_param->qpn);
|
||||
if (!ibqp)
|
||||
|
@ -2601,6 +2611,26 @@ int nes_accept(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param)
|
|||
if (cm_id->remote_addr.sin_addr.s_addr !=
|
||||
cm_id->local_addr.sin_addr.s_addr) {
|
||||
u64temp = (unsigned long)nesqp;
|
||||
nesibdev = nesvnic->nesibdev;
|
||||
nespd = nesqp->nespd;
|
||||
ibphysbuf.addr = nesqp->ietf_frame_pbase;
|
||||
ibphysbuf.size = conn_param->private_data_len +
|
||||
sizeof(struct ietf_mpa_frame);
|
||||
ibmr = nesibdev->ibdev.reg_phys_mr((struct ib_pd *)nespd,
|
||||
&ibphysbuf, 1,
|
||||
IB_ACCESS_LOCAL_WRITE,
|
||||
(u64 *)&nesqp->ietf_frame);
|
||||
if (!ibmr) {
|
||||
nes_debug(NES_DBG_CM, "Unable to register memory region"
|
||||
"for lSMM for cm_node = %p \n",
|
||||
cm_node);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
ibmr->pd = &nespd->ibpd;
|
||||
ibmr->device = nespd->ibpd.device;
|
||||
nesqp->lsmm_mr = ibmr;
|
||||
|
||||
u64temp |= NES_SW_CONTEXT_ALIGN>>1;
|
||||
set_wqe_64bit_value(wqe->wqe_words,
|
||||
NES_IWARP_SQ_WQE_COMP_CTX_LOW_IDX,
|
||||
|
@ -2611,14 +2641,13 @@ int nes_accept(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param)
|
|||
wqe->wqe_words[NES_IWARP_SQ_WQE_TOTAL_PAYLOAD_IDX] =
|
||||
cpu_to_le32(conn_param->private_data_len +
|
||||
sizeof(struct ietf_mpa_frame));
|
||||
wqe->wqe_words[NES_IWARP_SQ_WQE_FRAG0_LOW_IDX] =
|
||||
cpu_to_le32((u32)nesqp->ietf_frame_pbase);
|
||||
wqe->wqe_words[NES_IWARP_SQ_WQE_FRAG0_HIGH_IDX] =
|
||||
cpu_to_le32((u32)((u64)nesqp->ietf_frame_pbase >> 32));
|
||||
set_wqe_64bit_value(wqe->wqe_words,
|
||||
NES_IWARP_SQ_WQE_FRAG0_LOW_IDX,
|
||||
(u64)nesqp->ietf_frame);
|
||||
wqe->wqe_words[NES_IWARP_SQ_WQE_LENGTH0_IDX] =
|
||||
cpu_to_le32(conn_param->private_data_len +
|
||||
sizeof(struct ietf_mpa_frame));
|
||||
wqe->wqe_words[NES_IWARP_SQ_WQE_STAG0_IDX] = 0;
|
||||
wqe->wqe_words[NES_IWARP_SQ_WQE_STAG0_IDX] = ibmr->lkey;
|
||||
|
||||
nesqp->nesqp_context->ird_ord_sizes |=
|
||||
cpu_to_le32(NES_QPCONTEXT_ORDIRD_LSMM_PRESENT |
|
||||
|
|
|
@ -1360,8 +1360,10 @@ static struct ib_qp *nes_create_qp(struct ib_pd *ibpd,
|
|||
NES_QPCONTEXT_MISC_RQ_SIZE_SHIFT);
|
||||
nesqp->nesqp_context->misc |= cpu_to_le32((u32)nesqp->hwqp.sq_encoded_size <<
|
||||
NES_QPCONTEXT_MISC_SQ_SIZE_SHIFT);
|
||||
if (!udata) {
|
||||
nesqp->nesqp_context->misc |= cpu_to_le32(NES_QPCONTEXT_MISC_PRIV_EN);
|
||||
nesqp->nesqp_context->misc |= cpu_to_le32(NES_QPCONTEXT_MISC_FAST_REGISTER_EN);
|
||||
}
|
||||
nesqp->nesqp_context->cqs = cpu_to_le32(nesqp->nesscq->hw_cq.cq_number +
|
||||
((u32)nesqp->nesrcq->hw_cq.cq_number << 16));
|
||||
u64temp = (u64)nesqp->hwqp.sq_pbase;
|
||||
|
|
|
@ -134,6 +134,7 @@ struct nes_qp {
|
|||
struct ietf_mpa_frame *ietf_frame;
|
||||
dma_addr_t ietf_frame_pbase;
|
||||
wait_queue_head_t state_waitq;
|
||||
struct ib_mr *lsmm_mr;
|
||||
unsigned long socket;
|
||||
struct nes_hw_qp hwqp;
|
||||
struct work_struct work;
|
||||
|
|
|
@ -269,12 +269,7 @@ static inline mddev_t *mddev_get(mddev_t *mddev)
|
|||
return mddev;
|
||||
}
|
||||
|
||||
static void mddev_delayed_delete(struct work_struct *ws)
|
||||
{
|
||||
mddev_t *mddev = container_of(ws, mddev_t, del_work);
|
||||
kobject_del(&mddev->kobj);
|
||||
kobject_put(&mddev->kobj);
|
||||
}
|
||||
static void mddev_delayed_delete(struct work_struct *ws);
|
||||
|
||||
static void mddev_put(mddev_t *mddev)
|
||||
{
|
||||
|
@ -3811,6 +3806,21 @@ static struct kobj_type md_ktype = {
|
|||
|
||||
int mdp_major = 0;
|
||||
|
||||
static void mddev_delayed_delete(struct work_struct *ws)
|
||||
{
|
||||
mddev_t *mddev = container_of(ws, mddev_t, del_work);
|
||||
|
||||
if (mddev->private == &md_redundancy_group) {
|
||||
sysfs_remove_group(&mddev->kobj, &md_redundancy_group);
|
||||
if (mddev->sysfs_action)
|
||||
sysfs_put(mddev->sysfs_action);
|
||||
mddev->sysfs_action = NULL;
|
||||
mddev->private = NULL;
|
||||
}
|
||||
kobject_del(&mddev->kobj);
|
||||
kobject_put(&mddev->kobj);
|
||||
}
|
||||
|
||||
static int md_alloc(dev_t dev, char *name)
|
||||
{
|
||||
static DEFINE_MUTEX(disks_mutex);
|
||||
|
@ -4313,13 +4323,9 @@ static int do_md_stop(mddev_t * mddev, int mode, int is_open)
|
|||
mddev->queue->merge_bvec_fn = NULL;
|
||||
mddev->queue->unplug_fn = NULL;
|
||||
mddev->queue->backing_dev_info.congested_fn = NULL;
|
||||
if (mddev->pers->sync_request) {
|
||||
sysfs_remove_group(&mddev->kobj, &md_redundancy_group);
|
||||
if (mddev->sysfs_action)
|
||||
sysfs_put(mddev->sysfs_action);
|
||||
mddev->sysfs_action = NULL;
|
||||
}
|
||||
module_put(mddev->pers->owner);
|
||||
if (mddev->pers->sync_request)
|
||||
mddev->private = &md_redundancy_group;
|
||||
mddev->pers = NULL;
|
||||
/* tell userspace to handle 'inactive' */
|
||||
sysfs_notify_dirent(mddev->sysfs_state);
|
||||
|
|
|
@ -1383,6 +1383,11 @@ int wm8350_device_init(struct wm8350 *wm8350, int irq,
|
|||
wm8350->power.rev_g_coeff = 1;
|
||||
break;
|
||||
|
||||
case 1:
|
||||
dev_info(wm8350->dev, "WM8351 Rev B\n");
|
||||
wm8350->power.rev_g_coeff = 1;
|
||||
break;
|
||||
|
||||
default:
|
||||
dev_err(wm8350->dev, "Unknown WM8351 CHIP_REV\n");
|
||||
ret = -ENODEV;
|
||||
|
|
|
@ -793,8 +793,7 @@ static void s3cmci_dma_setup(struct s3cmci_host *host,
|
|||
host->mem->start + host->sdidata);
|
||||
|
||||
if (!setup_ok) {
|
||||
s3c2410_dma_config(host->dma, 4,
|
||||
(S3C2410_DCON_HWTRIG | S3C2410_DCON_CH0_SDI));
|
||||
s3c2410_dma_config(host->dma, 4, 0);
|
||||
s3c2410_dma_set_buffdone_fn(host->dma,
|
||||
s3cmci_dma_done_callback);
|
||||
s3c2410_dma_setflags(host->dma, S3C2410_DMAF_AUTOSTART);
|
||||
|
|
|
@ -821,7 +821,8 @@ static struct flash_info *__devinit jedec_probe(struct spi_device *spi)
|
|||
if (!(info->flags & IS_POW2PS))
|
||||
return info;
|
||||
}
|
||||
}
|
||||
} else
|
||||
return info;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
@ -46,16 +46,19 @@ static int physmap_flash_remove(struct platform_device *dev)
|
|||
|
||||
physmap_data = dev->dev.platform_data;
|
||||
|
||||
if (info->cmtd) {
|
||||
#ifdef CONFIG_MTD_PARTITIONS
|
||||
if (info->nr_parts) {
|
||||
del_mtd_partitions(info->cmtd);
|
||||
kfree(info->parts);
|
||||
} else if (physmap_data->nr_parts)
|
||||
del_mtd_partitions(info->cmtd);
|
||||
else
|
||||
del_mtd_device(info->cmtd);
|
||||
if (info->nr_parts || physmap_data->nr_parts)
|
||||
del_mtd_partitions(info->cmtd);
|
||||
else
|
||||
del_mtd_device(info->cmtd);
|
||||
#else
|
||||
del_mtd_device(info->cmtd);
|
||||
del_mtd_device(info->cmtd);
|
||||
#endif
|
||||
}
|
||||
#ifdef CONFIG_MTD_PARTITIONS
|
||||
if (info->nr_parts)
|
||||
kfree(info->parts);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MTD_CONCAT
|
||||
|
|
|
@ -2649,8 +2649,6 @@ static int __devinit happy_meal_sbus_probe_one(struct of_device *op, int is_qfe)
|
|||
int err = -ENODEV;
|
||||
|
||||
sbus_dp = to_of_device(op->dev.parent)->node;
|
||||
if (is_qfe)
|
||||
sbus_dp = to_of_device(op->dev.parent->parent)->node;
|
||||
|
||||
/* We can match PCI devices too, do not accept those here. */
|
||||
if (strcmp(sbus_dp->name, "sbus"))
|
||||
|
|
|
@ -143,7 +143,7 @@ config HOTPLUG_PCI_SHPC
|
|||
|
||||
config HOTPLUG_PCI_RPA
|
||||
tristate "RPA PCI Hotplug driver"
|
||||
depends on PPC_PSERIES && PPC64 && !HOTPLUG_PCI_FAKE
|
||||
depends on PPC_PSERIES && EEH && !HOTPLUG_PCI_FAKE
|
||||
help
|
||||
Say Y here if you have a RPA system that supports PCI Hotplug.
|
||||
|
||||
|
|
|
@ -133,6 +133,9 @@ static void set_downstream_devices_error_reporting(struct pci_dev *dev,
|
|||
bool enable)
|
||||
{
|
||||
set_device_error_reporting(dev, &enable);
|
||||
|
||||
if (!dev->subordinate)
|
||||
return;
|
||||
pci_walk_bus(dev->subordinate, set_device_error_reporting, &enable);
|
||||
}
|
||||
|
||||
|
|
|
@ -103,6 +103,7 @@ static int __devinit pcie_portdrv_probe (struct pci_dev *dev,
|
|||
static void pcie_portdrv_remove (struct pci_dev *dev)
|
||||
{
|
||||
pcie_port_device_remove(dev);
|
||||
pci_disable_device(dev);
|
||||
kfree(pci_get_drvdata(dev));
|
||||
}
|
||||
|
||||
|
|
|
@ -23,6 +23,7 @@
|
|||
#include <linux/acpi.h>
|
||||
#include <linux/kallsyms.h>
|
||||
#include <linux/dmi.h>
|
||||
#include <linux/pci-aspm.h>
|
||||
#include "pci.h"
|
||||
|
||||
int isa_dma_bridge_buggy;
|
||||
|
@ -1749,6 +1750,30 @@ static void __devinit quirk_e100_interrupt(struct pci_dev *dev)
|
|||
}
|
||||
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_e100_interrupt);
|
||||
|
||||
/*
|
||||
* The 82575 and 82598 may experience data corruption issues when transitioning
|
||||
* out of L0S. To prevent this we need to disable L0S on the pci-e link
|
||||
*/
|
||||
static void __devinit quirk_disable_aspm_l0s(struct pci_dev *dev)
|
||||
{
|
||||
dev_info(&dev->dev, "Disabling L0s\n");
|
||||
pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
|
||||
}
|
||||
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
|
||||
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
|
||||
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
|
||||
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
|
||||
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
|
||||
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
|
||||
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
|
||||
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
|
||||
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
|
||||
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
|
||||
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
|
||||
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
|
||||
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
|
||||
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
|
||||
|
||||
static void __devinit fixup_rev1_53c810(struct pci_dev* dev)
|
||||
{
|
||||
/* rev 1 ncr53c810 chips don't set the class at all which means
|
||||
|
@ -2097,7 +2122,7 @@ static void __devinit ht_disable_msi_mapping(struct pci_dev *dev)
|
|||
|
||||
if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
|
||||
&flags) == 0) {
|
||||
dev_info(&dev->dev, "Enabling HT MSI Mapping\n");
|
||||
dev_info(&dev->dev, "Disabling HT MSI Mapping\n");
|
||||
|
||||
pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
|
||||
flags & ~HT_MSI_FLAGS_ENABLE);
|
||||
|
@ -2141,6 +2166,10 @@ static void __devinit nv_msi_ht_cap_quirk(struct pci_dev *dev)
|
|||
int pos;
|
||||
int found;
|
||||
|
||||
/* Enabling HT MSI mapping on this device breaks MCP51 */
|
||||
if (dev->device == 0x270)
|
||||
return;
|
||||
|
||||
/* check if there is HT MSI cap or enabled on this device */
|
||||
found = ht_check_msi_mapping(dev);
|
||||
|
||||
|
|
|
@ -1297,7 +1297,7 @@ static int __init acer_wmi_init(void)
|
|||
|
||||
set_quirks();
|
||||
|
||||
if (!acpi_video_backlight_support() && has_cap(ACER_CAP_BRIGHTNESS)) {
|
||||
if (acpi_video_backlight_support() && has_cap(ACER_CAP_BRIGHTNESS)) {
|
||||
interface->capability &= ~ACER_CAP_BRIGHTNESS;
|
||||
printk(ACER_INFO "Brightness must be controlled by "
|
||||
"generic video driver\n");
|
||||
|
|
|
@ -180,10 +180,13 @@ static int ds2760_battery_read_status(struct ds2760_device_info *di)
|
|||
di->empty_uAh = battery_interpolate(scale, di->temp_C / 10);
|
||||
di->empty_uAh *= 1000; /* convert to µAh */
|
||||
|
||||
/* From Maxim Application Note 131: remaining capacity =
|
||||
* ((ICA - Empty Value) / (Full Value - Empty Value)) x 100% */
|
||||
di->rem_capacity = ((di->accum_current_uAh - di->empty_uAh) * 100L) /
|
||||
(di->full_active_uAh - di->empty_uAh);
|
||||
if (di->full_active_uAh == di->empty_uAh)
|
||||
di->rem_capacity = 0;
|
||||
else
|
||||
/* From Maxim Application Note 131: remaining capacity =
|
||||
* ((ICA - Empty Value) / (Full Value - Empty Value)) x 100% */
|
||||
di->rem_capacity = ((di->accum_current_uAh - di->empty_uAh) * 100L) /
|
||||
(di->full_active_uAh - di->empty_uAh);
|
||||
|
||||
if (di->rem_capacity < 0)
|
||||
di->rem_capacity = 0;
|
||||
|
|
|
@ -129,7 +129,7 @@ static int wait_for_pin(struct bbc_i2c_bus *bp, u8 *status)
|
|||
bp->waiting = 1;
|
||||
add_wait_queue(&bp->wq, &wait);
|
||||
while (limit-- > 0) {
|
||||
unsigned long val;
|
||||
long val;
|
||||
|
||||
val = wait_event_interruptible_timeout(
|
||||
bp->wq,
|
||||
|
|
|
@ -38,9 +38,6 @@
|
|||
#include <linux/string.h>
|
||||
#include <linux/genhd.h>
|
||||
#include <linux/blkdev.h>
|
||||
|
||||
#define MAJOR_NR JSFD_MAJOR
|
||||
|
||||
#include <asm/uaccess.h>
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/io.h>
|
||||
|
|
|
@ -1853,13 +1853,14 @@ static void aty128_bl_exit(struct backlight_device *bd)
|
|||
* Initialisation
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_PPC_PMAC
|
||||
#ifdef CONFIG_PPC_PMAC__disabled
|
||||
static void aty128_early_resume(void *data)
|
||||
{
|
||||
struct aty128fb_par *par = data;
|
||||
|
||||
if (try_acquire_console_sem())
|
||||
return;
|
||||
pci_restore_state(par->pdev);
|
||||
aty128_do_resume(par->pdev);
|
||||
release_console_sem();
|
||||
}
|
||||
|
@ -1907,7 +1908,14 @@ static int __devinit aty128_init(struct pci_dev *pdev, const struct pci_device_i
|
|||
/* Indicate sleep capability */
|
||||
if (par->chip_gen == rage_M3) {
|
||||
pmac_call_feature(PMAC_FTR_DEVICE_CAN_WAKE, NULL, 0, 1);
|
||||
#if 0 /* Disable the early video resume hack for now as it's causing problems, among
|
||||
* others we now rely on the PCI core restoring the config space for us, which
|
||||
* isn't the case with that hack, and that code path causes various things to
|
||||
* be called with interrupts off while they shouldn't. I'm leaving the code in
|
||||
* as it can be useful for debugging purposes
|
||||
*/
|
||||
pmac_set_early_video_resume(aty128_early_resume, par);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* Find default mode */
|
||||
|
|
|
@ -2762,12 +2762,13 @@ int radeonfb_pci_resume(struct pci_dev *pdev)
|
|||
return rc;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PPC_OF
|
||||
#ifdef CONFIG_PPC_OF__disabled
|
||||
static void radeonfb_early_resume(void *data)
|
||||
{
|
||||
struct radeonfb_info *rinfo = data;
|
||||
|
||||
rinfo->no_schedule = 1;
|
||||
pci_restore_state(rinfo->pdev);
|
||||
radeonfb_pci_resume(rinfo->pdev);
|
||||
rinfo->no_schedule = 0;
|
||||
}
|
||||
|
@ -2834,7 +2835,14 @@ void radeonfb_pm_init(struct radeonfb_info *rinfo, int dynclk, int ignore_devlis
|
|||
*/
|
||||
if (rinfo->pm_mode != radeon_pm_none) {
|
||||
pmac_call_feature(PMAC_FTR_DEVICE_CAN_WAKE, rinfo->of_node, 0, 1);
|
||||
#if 0 /* Disable the early video resume hack for now as it's causing problems, among
|
||||
* others we now rely on the PCI core restoring the config space for us, which
|
||||
* isn't the case with that hack, and that code path causes various things to
|
||||
* be called with interrupts off while they shouldn't. I'm leaving the code in
|
||||
* as it can be useful for debugging purposes
|
||||
*/
|
||||
pmac_set_early_video_resume(radeonfb_early_resume, rinfo);
|
||||
#endif
|
||||
}
|
||||
|
||||
#if 0
|
||||
|
|
|
@ -993,6 +993,7 @@ static int i810_check_params(struct fb_var_screeninfo *var,
|
|||
struct i810fb_par *par = info->par;
|
||||
int line_length, vidmem, mode_valid = 0, retval = 0;
|
||||
u32 vyres = var->yres_virtual, vxres = var->xres_virtual;
|
||||
|
||||
/*
|
||||
* Memory limit
|
||||
*/
|
||||
|
@ -1002,12 +1003,12 @@ static int i810_check_params(struct fb_var_screeninfo *var,
|
|||
if (vidmem > par->fb.size) {
|
||||
vyres = par->fb.size/line_length;
|
||||
if (vyres < var->yres) {
|
||||
vyres = yres;
|
||||
vyres = info->var.yres;
|
||||
vxres = par->fb.size/vyres;
|
||||
vxres /= var->bits_per_pixel >> 3;
|
||||
line_length = get_line_length(par, vxres,
|
||||
var->bits_per_pixel);
|
||||
vidmem = line_length * yres;
|
||||
vidmem = line_length * info->var.yres;
|
||||
if (vxres < var->xres) {
|
||||
printk("i810fb: required video memory, "
|
||||
"%d bytes, for %dx%d-%d (virtual) "
|
||||
|
|
|
@ -446,7 +446,6 @@ static void sh_mobile_lcdc_stop(struct sh_mobile_lcdc_priv *priv)
|
|||
{
|
||||
struct sh_mobile_lcdc_chan *ch;
|
||||
struct sh_mobile_lcdc_board_cfg *board_cfg;
|
||||
unsigned long tmp;
|
||||
int k;
|
||||
|
||||
/* tell the board code to disable the panel */
|
||||
|
@ -456,9 +455,8 @@ static void sh_mobile_lcdc_stop(struct sh_mobile_lcdc_priv *priv)
|
|||
if (board_cfg->display_off)
|
||||
board_cfg->display_off(board_cfg->board_data);
|
||||
|
||||
/* cleanup deferred io if SYS bus */
|
||||
tmp = ch->cfg.sys_bus_cfg.deferred_io_msec;
|
||||
if (ch->ldmt1r_value & (1 << 12) && tmp) {
|
||||
/* cleanup deferred io if enabled */
|
||||
if (ch->info.fbdefio) {
|
||||
fb_deferred_io_cleanup(&ch->info);
|
||||
ch->info.fbdefio = NULL;
|
||||
}
|
||||
|
|
|
@ -39,7 +39,7 @@ static u8 w1_gpio_read_bit(void *data)
|
|||
{
|
||||
struct w1_gpio_platform_data *pdata = data;
|
||||
|
||||
return gpio_get_value(pdata->pin);
|
||||
return gpio_get_value(pdata->pin) ? 1 : 0;
|
||||
}
|
||||
|
||||
static int __init w1_gpio_probe(struct platform_device *pdev)
|
||||
|
|
|
@ -198,9 +198,6 @@ static int mknod_ptmx(struct super_block *sb)
|
|||
|
||||
fsi->ptmx_dentry = dentry;
|
||||
rc = 0;
|
||||
|
||||
printk(KERN_DEBUG "Created ptmx node in devpts ino %lu\n",
|
||||
inode->i_ino);
|
||||
out:
|
||||
mutex_unlock(&root->d_inode->i_mutex);
|
||||
return rc;
|
||||
|
@ -369,8 +366,6 @@ static int new_pts_mount(struct file_system_type *fs_type, int flags,
|
|||
struct pts_fs_info *fsi;
|
||||
struct pts_mount_opts *opts;
|
||||
|
||||
printk(KERN_NOTICE "devpts: newinstance mount\n");
|
||||
|
||||
err = get_sb_nodev(fs_type, flags, data, devpts_fill_super, mnt);
|
||||
if (err)
|
||||
return err;
|
||||
|
|
|
@ -202,9 +202,9 @@ static sector_t _fat_bmap(struct address_space *mapping, sector_t block)
|
|||
sector_t blocknr;
|
||||
|
||||
/* fat_get_cluster() assumes the requested blocknr isn't truncated. */
|
||||
mutex_lock(&mapping->host->i_mutex);
|
||||
down_read(&mapping->host->i_alloc_sem);
|
||||
blocknr = generic_block_bmap(mapping, block, fat_get_block);
|
||||
mutex_unlock(&mapping->host->i_mutex);
|
||||
up_read(&mapping->host->i_alloc_sem);
|
||||
|
||||
return blocknr;
|
||||
}
|
||||
|
|
|
@ -274,6 +274,7 @@ __sync_single_inode(struct inode *inode, struct writeback_control *wbc)
|
|||
int ret;
|
||||
|
||||
BUG_ON(inode->i_state & I_SYNC);
|
||||
WARN_ON(inode->i_state & I_NEW);
|
||||
|
||||
/* Set I_SYNC, reset I_DIRTY */
|
||||
dirty = inode->i_state & I_DIRTY;
|
||||
|
@ -298,6 +299,7 @@ __sync_single_inode(struct inode *inode, struct writeback_control *wbc)
|
|||
}
|
||||
|
||||
spin_lock(&inode_lock);
|
||||
WARN_ON(inode->i_state & I_NEW);
|
||||
inode->i_state &= ~I_SYNC;
|
||||
if (!(inode->i_state & I_FREEING)) {
|
||||
if (!(inode->i_state & I_DIRTY) &&
|
||||
|
@ -470,6 +472,11 @@ void generic_sync_sb_inodes(struct super_block *sb,
|
|||
break;
|
||||
}
|
||||
|
||||
if (inode->i_state & I_NEW) {
|
||||
requeue_io(inode);
|
||||
continue;
|
||||
}
|
||||
|
||||
if (wbc->nonblocking && bdi_write_congested(bdi)) {
|
||||
wbc->encountered_congestion = 1;
|
||||
if (!sb_is_blkdev_sb(sb))
|
||||
|
@ -531,7 +538,7 @@ void generic_sync_sb_inodes(struct super_block *sb,
|
|||
list_for_each_entry(inode, &sb->s_inodes, i_sb_list) {
|
||||
struct address_space *mapping;
|
||||
|
||||
if (inode->i_state & (I_FREEING|I_WILL_FREE))
|
||||
if (inode->i_state & (I_FREEING|I_WILL_FREE|I_NEW))
|
||||
continue;
|
||||
mapping = inode->i_mapping;
|
||||
if (mapping->nrpages == 0)
|
||||
|
|
|
@ -359,6 +359,7 @@ static int invalidate_list(struct list_head *head, struct list_head *dispose)
|
|||
invalidate_inode_buffers(inode);
|
||||
if (!atomic_read(&inode->i_count)) {
|
||||
list_move(&inode->i_list, dispose);
|
||||
WARN_ON(inode->i_state & I_NEW);
|
||||
inode->i_state |= I_FREEING;
|
||||
count++;
|
||||
continue;
|
||||
|
@ -460,6 +461,7 @@ static void prune_icache(int nr_to_scan)
|
|||
continue;
|
||||
}
|
||||
list_move(&inode->i_list, &freeable);
|
||||
WARN_ON(inode->i_state & I_NEW);
|
||||
inode->i_state |= I_FREEING;
|
||||
nr_pruned++;
|
||||
}
|
||||
|
@ -656,6 +658,7 @@ void unlock_new_inode(struct inode *inode)
|
|||
* just created it (so there can be no old holders
|
||||
* that haven't tested I_LOCK).
|
||||
*/
|
||||
WARN_ON((inode->i_state & (I_LOCK|I_NEW)) != (I_LOCK|I_NEW));
|
||||
inode->i_state &= ~(I_LOCK|I_NEW);
|
||||
wake_up_inode(inode);
|
||||
}
|
||||
|
@ -1145,6 +1148,7 @@ void generic_delete_inode(struct inode *inode)
|
|||
|
||||
list_del_init(&inode->i_list);
|
||||
list_del_init(&inode->i_sb_list);
|
||||
WARN_ON(inode->i_state & I_NEW);
|
||||
inode->i_state |= I_FREEING;
|
||||
inodes_stat.nr_inodes--;
|
||||
spin_unlock(&inode_lock);
|
||||
|
@ -1186,16 +1190,19 @@ static void generic_forget_inode(struct inode *inode)
|
|||
spin_unlock(&inode_lock);
|
||||
return;
|
||||
}
|
||||
WARN_ON(inode->i_state & I_NEW);
|
||||
inode->i_state |= I_WILL_FREE;
|
||||
spin_unlock(&inode_lock);
|
||||
write_inode_now(inode, 1);
|
||||
spin_lock(&inode_lock);
|
||||
WARN_ON(inode->i_state & I_NEW);
|
||||
inode->i_state &= ~I_WILL_FREE;
|
||||
inodes_stat.nr_unused--;
|
||||
hlist_del_init(&inode->i_hash);
|
||||
}
|
||||
list_del_init(&inode->i_list);
|
||||
list_del_init(&inode->i_sb_list);
|
||||
WARN_ON(inode->i_state & I_NEW);
|
||||
inode->i_state |= I_FREEING;
|
||||
inodes_stat.nr_inodes--;
|
||||
spin_unlock(&inode_lock);
|
||||
|
|
|
@ -699,12 +699,12 @@ pipe_rdwr_fasync(int fd, struct file *filp, int on)
|
|||
int retval;
|
||||
|
||||
mutex_lock(&inode->i_mutex);
|
||||
|
||||
retval = fasync_helper(fd, filp, on, &pipe->fasync_readers);
|
||||
|
||||
if (retval >= 0)
|
||||
if (retval >= 0) {
|
||||
retval = fasync_helper(fd, filp, on, &pipe->fasync_writers);
|
||||
|
||||
if (retval < 0) /* this can happen only if on == T */
|
||||
fasync_helper(-1, filp, 0, &pipe->fasync_readers);
|
||||
}
|
||||
mutex_unlock(&inode->i_mutex);
|
||||
|
||||
if (retval < 0)
|
||||
|
|
|
@ -80,7 +80,7 @@ static const struct file_operations proc_kpagecount_operations = {
|
|||
#define KPF_RECLAIM 9
|
||||
#define KPF_BUDDY 10
|
||||
|
||||
#define kpf_copy_bit(flags, srcpos, dstpos) (((flags >> srcpos) & 1) << dstpos)
|
||||
#define kpf_copy_bit(flags, dstpos, srcpos) (((flags >> srcpos) & 1) << dstpos)
|
||||
|
||||
static ssize_t kpageflags_read(struct file *file, char __user *buf,
|
||||
size_t count, loff_t *ppos)
|
||||
|
|
|
@ -184,15 +184,7 @@ int squashfs_read_data(struct super_block *sb, void **buffer, u64 index,
|
|||
offset = 0;
|
||||
}
|
||||
|
||||
if (msblk->stream.avail_out == 0) {
|
||||
if (page == pages) {
|
||||
ERROR("zlib_inflate tried to "
|
||||
"decompress too much data, "
|
||||
"expected %d bytes. Zlib "
|
||||
"data probably corrupt\n",
|
||||
srclength);
|
||||
goto release_mutex;
|
||||
}
|
||||
if (msblk->stream.avail_out == 0 && page < pages) {
|
||||
msblk->stream.next_out = buffer[page++];
|
||||
msblk->stream.avail_out = PAGE_CACHE_SIZE;
|
||||
}
|
||||
|
@ -209,25 +201,20 @@ int squashfs_read_data(struct super_block *sb, void **buffer, u64 index,
|
|||
zlib_init = 1;
|
||||
}
|
||||
|
||||
zlib_err = zlib_inflate(&msblk->stream, Z_NO_FLUSH);
|
||||
zlib_err = zlib_inflate(&msblk->stream, Z_SYNC_FLUSH);
|
||||
|
||||
if (msblk->stream.avail_in == 0 && k < b)
|
||||
put_bh(bh[k++]);
|
||||
} while (zlib_err == Z_OK);
|
||||
|
||||
if (zlib_err != Z_STREAM_END) {
|
||||
ERROR("zlib_inflate returned unexpected result"
|
||||
" 0x%x, srclength %d, avail_in %d,"
|
||||
" avail_out %d\n", zlib_err, srclength,
|
||||
msblk->stream.avail_in,
|
||||
msblk->stream.avail_out);
|
||||
ERROR("zlib_inflate error, data probably corrupt\n");
|
||||
goto release_mutex;
|
||||
}
|
||||
|
||||
zlib_err = zlib_inflateEnd(&msblk->stream);
|
||||
if (zlib_err != Z_OK) {
|
||||
ERROR("zlib_inflateEnd returned unexpected result 0x%x,"
|
||||
" srclength %d\n", zlib_err, srclength);
|
||||
ERROR("zlib_inflate error, data probably corrupt\n");
|
||||
goto release_mutex;
|
||||
}
|
||||
length = msblk->stream.total_out;
|
||||
|
|
|
@ -371,8 +371,10 @@ retry:
|
|||
continue;
|
||||
if (!grab_super(old))
|
||||
goto retry;
|
||||
if (s)
|
||||
if (s) {
|
||||
up_write(&s->s_umount);
|
||||
destroy_super(s);
|
||||
}
|
||||
return old;
|
||||
}
|
||||
}
|
||||
|
@ -387,6 +389,7 @@ retry:
|
|||
err = set(s, data);
|
||||
if (err) {
|
||||
spin_unlock(&sb_lock);
|
||||
up_write(&s->s_umount);
|
||||
destroy_super(s);
|
||||
return ERR_PTR(err);
|
||||
}
|
||||
|
|
|
@ -34,6 +34,12 @@
|
|||
#include <linux/backing-dev.h>
|
||||
#include <linux/freezer.h>
|
||||
|
||||
#include "xfs_sb.h"
|
||||
#include "xfs_inum.h"
|
||||
#include "xfs_ag.h"
|
||||
#include "xfs_dmapi.h"
|
||||
#include "xfs_mount.h"
|
||||
|
||||
static kmem_zone_t *xfs_buf_zone;
|
||||
STATIC int xfsbufd(void *);
|
||||
STATIC int xfsbufd_wakeup(int, gfp_t);
|
||||
|
@ -1435,10 +1441,12 @@ xfs_unregister_buftarg(
|
|||
|
||||
void
|
||||
xfs_free_buftarg(
|
||||
xfs_buftarg_t *btp)
|
||||
struct xfs_mount *mp,
|
||||
struct xfs_buftarg *btp)
|
||||
{
|
||||
xfs_flush_buftarg(btp, 1);
|
||||
xfs_blkdev_issue_flush(btp);
|
||||
if (mp->m_flags & XFS_MOUNT_BARRIER)
|
||||
xfs_blkdev_issue_flush(btp);
|
||||
xfs_free_bufhash(btp);
|
||||
iput(btp->bt_mapping->host);
|
||||
|
||||
|
|
|
@ -413,7 +413,7 @@ static inline int XFS_bwrite(xfs_buf_t *bp)
|
|||
* Handling of buftargs.
|
||||
*/
|
||||
extern xfs_buftarg_t *xfs_alloc_buftarg(struct block_device *, int);
|
||||
extern void xfs_free_buftarg(xfs_buftarg_t *);
|
||||
extern void xfs_free_buftarg(struct xfs_mount *, struct xfs_buftarg *);
|
||||
extern void xfs_wait_buftarg(xfs_buftarg_t *);
|
||||
extern int xfs_setsize_buftarg(xfs_buftarg_t *, unsigned int, unsigned int);
|
||||
extern int xfs_flush_buftarg(xfs_buftarg_t *, int);
|
||||
|
|
|
@ -734,15 +734,15 @@ xfs_close_devices(
|
|||
{
|
||||
if (mp->m_logdev_targp && mp->m_logdev_targp != mp->m_ddev_targp) {
|
||||
struct block_device *logdev = mp->m_logdev_targp->bt_bdev;
|
||||
xfs_free_buftarg(mp->m_logdev_targp);
|
||||
xfs_free_buftarg(mp, mp->m_logdev_targp);
|
||||
xfs_blkdev_put(logdev);
|
||||
}
|
||||
if (mp->m_rtdev_targp) {
|
||||
struct block_device *rtdev = mp->m_rtdev_targp->bt_bdev;
|
||||
xfs_free_buftarg(mp->m_rtdev_targp);
|
||||
xfs_free_buftarg(mp, mp->m_rtdev_targp);
|
||||
xfs_blkdev_put(rtdev);
|
||||
}
|
||||
xfs_free_buftarg(mp->m_ddev_targp);
|
||||
xfs_free_buftarg(mp, mp->m_ddev_targp);
|
||||
}
|
||||
|
||||
/*
|
||||
|
@ -811,9 +811,9 @@ xfs_open_devices(
|
|||
|
||||
out_free_rtdev_targ:
|
||||
if (mp->m_rtdev_targp)
|
||||
xfs_free_buftarg(mp->m_rtdev_targp);
|
||||
xfs_free_buftarg(mp, mp->m_rtdev_targp);
|
||||
out_free_ddev_targ:
|
||||
xfs_free_buftarg(mp->m_ddev_targp);
|
||||
xfs_free_buftarg(mp, mp->m_ddev_targp);
|
||||
out_close_rtdev:
|
||||
if (rtdev)
|
||||
xfs_blkdev_put(rtdev);
|
||||
|
|
|
@ -246,9 +246,6 @@ xfs_iget_cache_miss(
|
|||
goto out_destroy;
|
||||
}
|
||||
|
||||
if (lock_flags)
|
||||
xfs_ilock(ip, lock_flags);
|
||||
|
||||
/*
|
||||
* Preload the radix tree so we can insert safely under the
|
||||
* write spinlock. Note that we cannot sleep inside the preload
|
||||
|
@ -256,7 +253,16 @@ xfs_iget_cache_miss(
|
|||
*/
|
||||
if (radix_tree_preload(GFP_KERNEL)) {
|
||||
error = EAGAIN;
|
||||
goto out_unlock;
|
||||
goto out_destroy;
|
||||
}
|
||||
|
||||
/*
|
||||
* Because the inode hasn't been added to the radix-tree yet it can't
|
||||
* be found by another thread, so we can do the non-sleeping lock here.
|
||||
*/
|
||||
if (lock_flags) {
|
||||
if (!xfs_ilock_nowait(ip, lock_flags))
|
||||
BUG();
|
||||
}
|
||||
|
||||
mask = ~(((XFS_INODE_CLUSTER_SIZE(mp) >> mp->m_sb.sb_inodelog)) - 1);
|
||||
|
@ -284,7 +290,6 @@ xfs_iget_cache_miss(
|
|||
out_preload_end:
|
||||
write_unlock(&pag->pag_ici_lock);
|
||||
radix_tree_preload_end();
|
||||
out_unlock:
|
||||
if (lock_flags)
|
||||
xfs_iunlock(ip, lock_flags);
|
||||
out_destroy:
|
||||
|
|
|
@ -1455,10 +1455,19 @@ xlog_recover_add_to_trans(
|
|||
item = item->ri_prev;
|
||||
|
||||
if (item->ri_total == 0) { /* first region to be added */
|
||||
item->ri_total = in_f->ilf_size;
|
||||
ASSERT(item->ri_total <= XLOG_MAX_REGIONS_IN_ITEM);
|
||||
item->ri_buf = kmem_zalloc((item->ri_total *
|
||||
sizeof(xfs_log_iovec_t)), KM_SLEEP);
|
||||
if (in_f->ilf_size == 0 ||
|
||||
in_f->ilf_size > XLOG_MAX_REGIONS_IN_ITEM) {
|
||||
xlog_warn(
|
||||
"XFS: bad number of regions (%d) in inode log format",
|
||||
in_f->ilf_size);
|
||||
ASSERT(0);
|
||||
return XFS_ERROR(EIO);
|
||||
}
|
||||
|
||||
item->ri_total = in_f->ilf_size;
|
||||
item->ri_buf =
|
||||
kmem_zalloc(item->ri_total * sizeof(xfs_log_iovec_t),
|
||||
KM_SLEEP);
|
||||
}
|
||||
ASSERT(item->ri_total > item->ri_cnt);
|
||||
/* Description region is ri_buf[0] */
|
||||
|
|
|
@ -69,8 +69,8 @@ struct detailed_pixel_timing {
|
|||
u8 hborder;
|
||||
u8 vborder;
|
||||
u8 unknown0:1;
|
||||
u8 vsync_positive:1;
|
||||
u8 hsync_positive:1;
|
||||
u8 vsync_positive:1;
|
||||
u8 separate_sync:2;
|
||||
u8 stereo:1;
|
||||
u8 unknown6:1;
|
||||
|
|
|
@ -21,6 +21,15 @@
|
|||
#include <linux/spinlock.h>
|
||||
#include <linux/interrupt.h>
|
||||
|
||||
/* on architectures without dma-mapping capabilities we need to ensure
|
||||
* that the asynchronous path compiles away
|
||||
*/
|
||||
#ifdef CONFIG_HAS_DMA
|
||||
#define __async_inline
|
||||
#else
|
||||
#define __async_inline __always_inline
|
||||
#endif
|
||||
|
||||
/**
|
||||
* dma_chan_ref - object used to manage dma channels received from the
|
||||
* dmaengine core.
|
||||
|
|
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue