iommu/vt-d: Add Scalable Mode fault information
Intel VT-d specification revision 3 added support for Scalable Mode Translation for DMA remapping. Add the Scalable Mode fault reasons to show detailed fault reasons when the translation fault happens. Link: https://software.intel.com/sites/default/files/managed/c5/15/vt-directed-io-spec.pdf Reviewed-by: Sohil Mehta <sohil.mehta@intel.com> Signed-off-by: Kyung Min Park <kyung.min.park@intel.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
This commit is contained in:
Kyung Min Park
Joerg Roedel
parent
cfb94a372f
commit
fd730007a0
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@ -1519,6 +1519,64 @@ static const char *dma_remap_fault_reasons[] =
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"PCE for translation request specifies blocking",
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};
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static const char * const dma_remap_sm_fault_reasons[] = {
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"SM: Invalid Root Table Address",
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"SM: TTM 0 for request with PASID",
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"SM: TTM 0 for page group request",
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"Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x33-0x37 */
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"SM: Error attempting to access Root Entry",
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"SM: Present bit in Root Entry is clear",
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"SM: Non-zero reserved field set in Root Entry",
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"Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x3B-0x3F */
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"SM: Error attempting to access Context Entry",
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"SM: Present bit in Context Entry is clear",
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"SM: Non-zero reserved field set in the Context Entry",
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"SM: Invalid Context Entry",
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"SM: DTE field in Context Entry is clear",
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"SM: PASID Enable field in Context Entry is clear",
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"SM: PASID is larger than the max in Context Entry",
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"SM: PRE field in Context-Entry is clear",
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"SM: RID_PASID field error in Context-Entry",
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"Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x49-0x4F */
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"SM: Error attempting to access the PASID Directory Entry",
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"SM: Present bit in Directory Entry is clear",
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"SM: Non-zero reserved field set in PASID Directory Entry",
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"Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x53-0x57 */
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"SM: Error attempting to access PASID Table Entry",
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"SM: Present bit in PASID Table Entry is clear",
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"SM: Non-zero reserved field set in PASID Table Entry",
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"SM: Invalid Scalable-Mode PASID Table Entry",
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"SM: ERE field is clear in PASID Table Entry",
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"SM: SRE field is clear in PASID Table Entry",
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"Unknown", "Unknown",/* 0x5E-0x5F */
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"Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x60-0x67 */
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"Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x68-0x6F */
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"SM: Error attempting to access first-level paging entry",
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"SM: Present bit in first-level paging entry is clear",
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"SM: Non-zero reserved field set in first-level paging entry",
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"SM: Error attempting to access FL-PML4 entry",
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"SM: First-level entry address beyond MGAW in Nested translation",
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"SM: Read permission error in FL-PML4 entry in Nested translation",
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"SM: Read permission error in first-level paging entry in Nested translation",
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"SM: Write permission error in first-level paging entry in Nested translation",
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"SM: Error attempting to access second-level paging entry",
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"SM: Read/Write permission error in second-level paging entry",
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"SM: Non-zero reserved field set in second-level paging entry",
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"SM: Invalid second-level page table pointer",
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"SM: A/D bit update needed in second-level entry when set up in no snoop",
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"Unknown", "Unknown", "Unknown", /* 0x7D-0x7F */
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"SM: Address in first-level translation is not canonical",
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"SM: U/S set 0 for first-level translation with user privilege",
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"SM: No execute permission for request with PASID and ER=1",
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"SM: Address beyond the DMA hardware max",
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"SM: Second-level entry address beyond the max",
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"SM: No write permission for Write/AtomicOp request",
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"SM: No read permission for Read/AtomicOp request",
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"SM: Invalid address-interrupt address",
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"Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x88-0x8F */
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"SM: A/D bit update needed in first-level entry when set up in no snoop",
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};
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static const char *irq_remap_fault_reasons[] =
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{
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"Detected reserved fields in the decoded interrupt-remapped request",
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@ -1536,6 +1594,10 @@ static const char *dmar_get_fault_reason(u8 fault_reason, int *fault_type)
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ARRAY_SIZE(irq_remap_fault_reasons))) {
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*fault_type = INTR_REMAP;
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return irq_remap_fault_reasons[fault_reason - 0x20];
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} else if (fault_reason >= 0x30 && (fault_reason - 0x30 <
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ARRAY_SIZE(dma_remap_sm_fault_reasons))) {
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*fault_type = DMA_REMAP;
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return dma_remap_sm_fault_reasons[fault_reason - 0x30];
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} else if (fault_reason < ARRAY_SIZE(dma_remap_fault_reasons)) {
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*fault_type = DMA_REMAP;
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return dma_remap_fault_reasons[fault_reason];
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@ -1611,7 +1673,8 @@ void dmar_msi_read(int irq, struct msi_msg *msg)
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}
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static int dmar_fault_do_one(struct intel_iommu *iommu, int type,
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u8 fault_reason, u16 source_id, unsigned long long addr)
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u8 fault_reason, int pasid, u16 source_id,
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unsigned long long addr)
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{
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const char *reason;
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int fault_type;
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@ -1624,10 +1687,11 @@ static int dmar_fault_do_one(struct intel_iommu *iommu, int type,
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PCI_FUNC(source_id & 0xFF), addr >> 48,
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fault_reason, reason);
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else
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pr_err("[%s] Request device [%02x:%02x.%d] fault addr %llx [fault reason %02d] %s\n",
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pr_err("[%s] Request device [%02x:%02x.%d] PASID %x fault addr %llx [fault reason %02d] %s\n",
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type ? "DMA Read" : "DMA Write",
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source_id >> 8, PCI_SLOT(source_id & 0xFF),
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PCI_FUNC(source_id & 0xFF), addr, fault_reason, reason);
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PCI_FUNC(source_id & 0xFF), pasid, addr,
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fault_reason, reason);
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return 0;
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}
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@ -1659,8 +1723,9 @@ irqreturn_t dmar_fault(int irq, void *dev_id)
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u8 fault_reason;
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u16 source_id;
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u64 guest_addr;
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int type;
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int type, pasid;
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u32 data;
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bool pasid_present;
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/* highest 32 bits */
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data = readl(iommu->reg + reg +
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@ -1672,10 +1737,12 @@ irqreturn_t dmar_fault(int irq, void *dev_id)
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fault_reason = dma_frcd_fault_reason(data);
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type = dma_frcd_type(data);
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pasid = dma_frcd_pasid_value(data);
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data = readl(iommu->reg + reg +
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fault_index * PRIMARY_FAULT_REG_LEN + 8);
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source_id = dma_frcd_source_id(data);
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pasid_present = dma_frcd_pasid_present(data);
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guest_addr = dmar_readq(iommu->reg + reg +
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fault_index * PRIMARY_FAULT_REG_LEN);
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guest_addr = dma_frcd_page_addr(guest_addr);
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@ -1688,7 +1755,9 @@ irqreturn_t dmar_fault(int irq, void *dev_id)
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raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
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if (!ratelimited)
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/* Using pasid -1 if pasid is not present */
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dmar_fault_do_one(iommu, type, fault_reason,
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pasid_present ? pasid : -1,
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source_id, guest_addr);
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fault_index++;
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@ -272,6 +272,8 @@
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#define dma_frcd_type(d) ((d >> 30) & 1)
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#define dma_frcd_fault_reason(c) (c & 0xff)
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#define dma_frcd_source_id(c) (c & 0xffff)
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#define dma_frcd_pasid_value(c) (((c) >> 8) & 0xfffff)
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#define dma_frcd_pasid_present(c) (((c) >> 31) & 1)
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/* low 64 bit */
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#define dma_frcd_page_addr(d) (d & (((u64)-1) << PAGE_SHIFT))
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