MIPS: BCM63XX: add HSSPI IRQ and register offsets
Signed-off-by: Jonas Gorski <jogo@openwrt.org> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6179/
This commit is contained in:
Jonas Gorski
Ralf Baechle
parent
26b8c07f59
commit
fd034a1aae
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@ -145,6 +145,7 @@ enum bcm63xx_regs_set {
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RSET_UART1,
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RSET_GPIO,
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RSET_SPI,
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RSET_HSSPI,
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RSET_UDC0,
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RSET_OHCI0,
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RSET_OHCI_PRIV,
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@ -193,6 +194,7 @@ enum bcm63xx_regs_set {
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#define RSET_ENETDMAS_SIZE(chans) (16 * (chans))
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#define RSET_ENETSW_SIZE 65536
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#define RSET_UART_SIZE 24
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#define RSET_HSSPI_SIZE 1536
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#define RSET_UDC_SIZE 256
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#define RSET_OHCI_SIZE 256
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#define RSET_EHCI_SIZE 256
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@ -265,6 +267,7 @@ enum bcm63xx_regs_set {
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#define BCM_6328_UART1_BASE (0xb0000120)
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#define BCM_6328_GPIO_BASE (0xb0000080)
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#define BCM_6328_SPI_BASE (0xdeadbeef)
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#define BCM_6328_HSSPI_BASE (0xb0001000)
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#define BCM_6328_UDC0_BASE (0xdeadbeef)
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#define BCM_6328_USBDMA_BASE (0xb000c000)
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#define BCM_6328_OHCI0_BASE (0xb0002600)
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@ -313,6 +316,7 @@ enum bcm63xx_regs_set {
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#define BCM_6338_UART1_BASE (0xdeadbeef)
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#define BCM_6338_GPIO_BASE (0xfffe0400)
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#define BCM_6338_SPI_BASE (0xfffe0c00)
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#define BCM_6338_HSSPI_BASE (0xdeadbeef)
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#define BCM_6338_UDC0_BASE (0xdeadbeef)
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#define BCM_6338_USBDMA_BASE (0xfffe2400)
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#define BCM_6338_OHCI0_BASE (0xdeadbeef)
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@ -360,6 +364,7 @@ enum bcm63xx_regs_set {
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#define BCM_6345_UART1_BASE (0xdeadbeef)
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#define BCM_6345_GPIO_BASE (0xfffe0400)
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#define BCM_6345_SPI_BASE (0xdeadbeef)
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#define BCM_6345_HSSPI_BASE (0xdeadbeef)
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#define BCM_6345_UDC0_BASE (0xdeadbeef)
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#define BCM_6345_USBDMA_BASE (0xfffe2800)
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#define BCM_6345_ENET0_BASE (0xfffe1800)
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@ -406,6 +411,7 @@ enum bcm63xx_regs_set {
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#define BCM_6348_UART1_BASE (0xdeadbeef)
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#define BCM_6348_GPIO_BASE (0xfffe0400)
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#define BCM_6348_SPI_BASE (0xfffe0c00)
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#define BCM_6348_HSSPI_BASE (0xdeadbeef)
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#define BCM_6348_UDC0_BASE (0xfffe1000)
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#define BCM_6348_USBDMA_BASE (0xdeadbeef)
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#define BCM_6348_OHCI0_BASE (0xfffe1b00)
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@ -451,6 +457,7 @@ enum bcm63xx_regs_set {
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#define BCM_6358_UART1_BASE (0xfffe0120)
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#define BCM_6358_GPIO_BASE (0xfffe0080)
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#define BCM_6358_SPI_BASE (0xfffe0800)
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#define BCM_6358_HSSPI_BASE (0xdeadbeef)
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#define BCM_6358_UDC0_BASE (0xfffe0800)
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#define BCM_6358_USBDMA_BASE (0xdeadbeef)
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#define BCM_6358_OHCI0_BASE (0xfffe1400)
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@ -553,6 +560,7 @@ enum bcm63xx_regs_set {
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#define BCM_6368_UART1_BASE (0xb0000120)
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#define BCM_6368_GPIO_BASE (0xb0000080)
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#define BCM_6368_SPI_BASE (0xb0000800)
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#define BCM_6368_HSSPI_BASE (0xdeadbeef)
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#define BCM_6368_UDC0_BASE (0xdeadbeef)
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#define BCM_6368_USBDMA_BASE (0xb0004800)
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#define BCM_6368_OHCI0_BASE (0xb0001600)
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@ -604,6 +612,7 @@ extern const unsigned long *bcm63xx_regs_base;
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__GEN_RSET_BASE(__cpu, UART1) \
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__GEN_RSET_BASE(__cpu, GPIO) \
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__GEN_RSET_BASE(__cpu, SPI) \
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__GEN_RSET_BASE(__cpu, HSSPI) \
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__GEN_RSET_BASE(__cpu, UDC0) \
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__GEN_RSET_BASE(__cpu, OHCI0) \
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__GEN_RSET_BASE(__cpu, OHCI_PRIV) \
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@ -647,6 +656,7 @@ extern const unsigned long *bcm63xx_regs_base;
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[RSET_UART1] = BCM_## __cpu ##_UART1_BASE, \
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[RSET_GPIO] = BCM_## __cpu ##_GPIO_BASE, \
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[RSET_SPI] = BCM_## __cpu ##_SPI_BASE, \
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[RSET_HSSPI] = BCM_## __cpu ##_HSSPI_BASE, \
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[RSET_UDC0] = BCM_## __cpu ##_UDC0_BASE, \
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[RSET_OHCI0] = BCM_## __cpu ##_OHCI0_BASE, \
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[RSET_OHCI_PRIV] = BCM_## __cpu ##_OHCI_PRIV_BASE, \
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@ -727,6 +737,7 @@ enum bcm63xx_irq {
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IRQ_ENET0,
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IRQ_ENET1,
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IRQ_ENET_PHY,
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IRQ_HSSPI,
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IRQ_OHCI0,
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IRQ_EHCI0,
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IRQ_USBD,
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@ -815,6 +826,7 @@ enum bcm63xx_irq {
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#define BCM_6328_ENET0_IRQ 0
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#define BCM_6328_ENET1_IRQ 0
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#define BCM_6328_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)
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#define BCM_6328_HSSPI_IRQ (IRQ_INTERNAL_BASE + 29)
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#define BCM_6328_OHCI0_IRQ (BCM_6328_HIGH_IRQ_BASE + 9)
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#define BCM_6328_EHCI0_IRQ (BCM_6328_HIGH_IRQ_BASE + 10)
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#define BCM_6328_USBD_IRQ (IRQ_INTERNAL_BASE + 4)
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@ -860,6 +872,7 @@ enum bcm63xx_irq {
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#define BCM_6338_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
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#define BCM_6338_ENET1_IRQ 0
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#define BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
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#define BCM_6338_HSSPI_IRQ 0
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#define BCM_6338_OHCI0_IRQ 0
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#define BCM_6338_EHCI0_IRQ 0
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#define BCM_6338_USBD_IRQ 0
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@ -898,6 +911,7 @@ enum bcm63xx_irq {
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#define BCM_6345_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
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#define BCM_6345_ENET1_IRQ 0
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#define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)
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#define BCM_6345_HSSPI_IRQ 0
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#define BCM_6345_OHCI0_IRQ 0
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#define BCM_6345_EHCI0_IRQ 0
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#define BCM_6345_USBD_IRQ 0
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@ -936,6 +950,7 @@ enum bcm63xx_irq {
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#define BCM_6348_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
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#define BCM_6348_ENET1_IRQ (IRQ_INTERNAL_BASE + 7)
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#define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
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#define BCM_6348_HSSPI_IRQ 0
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#define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12)
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#define BCM_6348_EHCI0_IRQ 0
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#define BCM_6348_USBD_IRQ 0
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@ -974,6 +989,7 @@ enum bcm63xx_irq {
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#define BCM_6358_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
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#define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6)
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#define BCM_6358_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
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#define BCM_6358_HSSPI_IRQ 0
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#define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
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#define BCM_6358_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10)
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#define BCM_6358_USBD_IRQ 0
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@ -1086,6 +1102,7 @@ enum bcm63xx_irq {
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#define BCM_6368_ENET0_IRQ 0
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#define BCM_6368_ENET1_IRQ 0
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#define BCM_6368_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 15)
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#define BCM_6368_HSSPI_IRQ 0
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#define BCM_6368_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
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#define BCM_6368_EHCI0_IRQ (IRQ_INTERNAL_BASE + 7)
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#define BCM_6368_USBD_IRQ (IRQ_INTERNAL_BASE + 8)
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@ -1133,6 +1150,7 @@ extern const int *bcm63xx_irqs;
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[IRQ_ENET0] = BCM_## __cpu ##_ENET0_IRQ, \
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[IRQ_ENET1] = BCM_## __cpu ##_ENET1_IRQ, \
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[IRQ_ENET_PHY] = BCM_## __cpu ##_ENET_PHY_IRQ, \
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[IRQ_HSSPI] = BCM_## __cpu ##_HSSPI_IRQ, \
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[IRQ_OHCI0] = BCM_## __cpu ##_OHCI0_IRQ, \
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[IRQ_EHCI0] = BCM_## __cpu ##_EHCI0_IRQ, \
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[IRQ_USBD] = BCM_## __cpu ##_USBD_IRQ, \
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